diff options
Diffstat (limited to 'drivers/gpu')
413 files changed, 9775 insertions, 36641 deletions
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 24a066e1841c..a8acc197dec3 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -33,7 +33,7 @@ drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \ drm_kms_helper_common.o drm_dp_dual_mode_helper.o \ drm_simple_kms_helper.o drm_modeset_helper.o \ - drm_scdc_helper.o + drm_scdc_helper.o drm_gem_framebuffer_helper.o drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 51d1364cf185..12e71bbfd222 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -96,6 +96,7 @@ extern int amdgpu_bapm; extern int amdgpu_deep_color; extern int amdgpu_vm_size; extern int amdgpu_vm_block_size; +extern int amdgpu_vm_fragment_size; extern int amdgpu_vm_fault_stop; extern int amdgpu_vm_debug; extern int amdgpu_vm_update_mode; @@ -373,78 +374,10 @@ struct amdgpu_clock { }; /* - * BO. + * GEM. */ -struct amdgpu_bo_list_entry { - struct amdgpu_bo *robj; - struct ttm_validate_buffer tv; - struct amdgpu_bo_va *bo_va; - uint32_t priority; - struct page **user_pages; - int user_invalidated; -}; - -struct amdgpu_bo_va_mapping { - struct list_head list; - struct rb_node rb; - uint64_t start; - uint64_t last; - uint64_t __subtree_last; - uint64_t offset; - uint64_t flags; -}; - -/* bo virtual addresses in a specific vm */ -struct amdgpu_bo_va { - /* protected by bo being reserved */ - struct list_head bo_list; - struct dma_fence *last_pt_update; - unsigned ref_count; - - /* protected by vm mutex and spinlock */ - struct list_head vm_status; - - /* mappings for this bo_va */ - struct list_head invalids; - struct list_head valids; - - /* constant after initialization */ - struct amdgpu_vm *vm; - struct amdgpu_bo *bo; -}; #define AMDGPU_GEM_DOMAIN_MAX 0x3 - -struct amdgpu_bo { - /* Protected by tbo.reserved */ - u32 prefered_domains; - u32 allowed_domains; - struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; - struct ttm_placement placement; - struct ttm_buffer_object tbo; - struct ttm_bo_kmap_obj kmap; - u64 flags; - unsigned pin_count; - void *kptr; - u64 tiling_flags; - u64 metadata_flags; - void *metadata; - u32 metadata_size; - unsigned prime_shared_count; - /* list of all virtual address to which this bo - * is associated to - */ - struct list_head va; - /* Constant after initialization */ - struct drm_gem_object gem_base; - struct amdgpu_bo *parent; - struct amdgpu_bo *shadow; - - struct ttm_bo_kmap_obj dma_buf_vmap; - struct amdgpu_mn *mn; - struct list_head mn_list; - struct list_head shadow_list; -}; #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) void amdgpu_gem_object_free(struct drm_gem_object *obj); @@ -678,15 +611,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT /* overlap the doorbell assignment with VCN as they are mutually exclusive * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD */ - AMDGPU_DOORBELL64_RING0_1 = 0xF8, - AMDGPU_DOORBELL64_RING2_3 = 0xF9, - AMDGPU_DOORBELL64_RING4_5 = 0xFA, - AMDGPU_DOORBELL64_RING6_7 = 0xFB, + AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, + AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, + AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, + AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, - AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC, - AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD, - AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE, - AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF, + AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, + AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, + AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, + AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, AMDGPU_DOORBELL64_INVALID = 0xFFFF @@ -816,6 +749,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); struct amdgpu_fpriv { struct amdgpu_vm vm; struct amdgpu_bo_va *prt_va; + struct amdgpu_bo_va *csa_va; struct mutex bo_list_lock; struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; @@ -825,6 +759,14 @@ struct amdgpu_fpriv { /* * residency list */ +struct amdgpu_bo_list_entry { + struct amdgpu_bo *robj; + struct ttm_validate_buffer tv; + struct amdgpu_bo_va *bo_va; + uint32_t priority; + struct page **user_pages; + int user_invalidated; +}; struct amdgpu_bo_list { struct mutex lock; @@ -1191,10 +1133,6 @@ struct amdgpu_wb { int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); -int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb); -int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb); -void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb); -void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb); void amdgpu_get_pcie_info(struct amdgpu_device *adev); @@ -1488,7 +1426,7 @@ struct amdgpu_device { bool is_atom_fw; uint8_t *bios; uint32_t bios_size; - struct amdgpu_bo *stollen_vga_memory; + struct amdgpu_bo *stolen_vga_memory; uint32_t bios_scratch_reg_offset; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; @@ -1546,9 +1484,6 @@ struct amdgpu_device { struct amdgpu_mman mman; struct amdgpu_vram_scratch vram_scratch; struct amdgpu_wb wb; - atomic64_t vram_usage; - atomic64_t vram_vis_usage; - atomic64_t gtt_usage; atomic64_t num_bytes_moved; atomic64_t num_evictions; atomic64_t num_vram_cpu_page_faults; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 06879d1dcabd..a52795d9b458 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -285,19 +285,20 @@ static int acp_hw_init(void *handle) return 0; else if (r) return r; + if (adev->asic_type != CHIP_STONEY) { + adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); + if (adev->acp.acp_genpd == NULL) + return -ENOMEM; - adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); - if (adev->acp.acp_genpd == NULL) - return -ENOMEM; - - adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; - adev->acp.acp_genpd->gpd.power_off = acp_poweroff; - adev->acp.acp_genpd->gpd.power_on = acp_poweron; + adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; + adev->acp.acp_genpd->gpd.power_off = acp_poweroff; + adev->acp.acp_genpd->gpd.power_on = acp_poweron; - adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; + adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; - pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); + pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); + } adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS, GFP_KERNEL); @@ -319,14 +320,29 @@ static int acp_hw_init(void *handle) return -ENOMEM; } - i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; + switch (adev->asic_type) { + case CHIP_STONEY: + i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + break; + default: + i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; + } i2s_pdata[0].cap = DWC_I2S_PLAY; i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; + switch (adev->asic_type) { + case CHIP_STONEY: + i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_COMP_PARAM1 | + DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; + break; + default: + i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | + DW_I2S_QUIRK_COMP_PARAM1; + } - i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | - DW_I2S_QUIRK_COMP_PARAM1; i2s_pdata[1].cap = DWC_I2S_RECORD; i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; @@ -373,12 +389,14 @@ static int acp_hw_init(void *handle) if (r) return r; - for (i = 0; i < ACP_DEVS ; i++) { - dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); - r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); - if (r) { - dev_err(dev, "Failed to add dev to genpd\n"); - return r; + if (adev->asic_type != CHIP_STONEY) { + for (i = 0; i < ACP_DEVS ; i++) { + dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); + r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); + if (r) { + dev_err(dev, "Failed to add dev to genpd\n"); + return r; + } } } @@ -398,20 +416,22 @@ static int acp_hw_fini(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* return early if no ACP */ - if (!adev->acp.acp_genpd) + if (!adev->acp.acp_cell) return 0; - for (i = 0; i < ACP_DEVS ; i++) { - dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); - ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); - /* If removal fails, dont giveup and try rest */ - if (ret) - dev_err(dev, "remove dev from genpd failed\n"); + if (adev->acp.acp_genpd) { + for (i = 0; i < ACP_DEVS ; i++) { + dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); + ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev); + /* If removal fails, dont giveup and try rest */ + if (ret) + dev_err(dev, "remove dev from genpd failed\n"); + } + kfree(adev->acp.acp_genpd); } mfd_remove_devices(adev->acp.parent); kfree(adev->acp.acp_res); - kfree(adev->acp.acp_genpd); kfree(adev->acp.acp_cell); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index ef79551b4cb7..57afad79f55d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -30,10 +30,10 @@ #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> #include "amdgpu.h" +#include "amdgpu_pm.h" #include "amd_acpi.h" #include "atom.h" -extern void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); /* Call the ATIF method */ /** @@ -289,7 +289,7 @@ out: * handles it. * Returns NOTIFY code */ -int amdgpu_atif_handler(struct amdgpu_device *adev, +static int amdgpu_atif_handler(struct amdgpu_device *adev, struct acpi_bus_event *event) { struct amdgpu_atif *atif = &adev->atif; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 37971d9402e3..5432af39a674 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -27,16 +27,15 @@ #include "amdgpu_gfx.h" #include <linux/module.h> -const struct kfd2kgd_calls *kfd2kgd; const struct kgd2kfd_calls *kgd2kfd; -bool (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**); +bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**); int amdgpu_amdkfd_init(void) { int ret; #if defined(CONFIG_HSA_AMD_MODULE) - int (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**); + int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**); kgd2kfd_init_p = symbol_request(kgd2kfd_init); @@ -61,8 +60,21 @@ int amdgpu_amdkfd_init(void) return ret; } -bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev) +void amdgpu_amdkfd_fini(void) +{ + if (kgd2kfd) { + kgd2kfd->exit(); + symbol_put(kgd2kfd_init); + } +} + +void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) { + const struct kfd2kgd_calls *kfd2kgd; + + if (!kgd2kfd) + return; + switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_KAVERI: @@ -73,25 +85,12 @@ bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev) kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); break; default: - return false; + dev_info(adev->dev, "kfd not supported on this ASIC\n"); + return; } - return true; -} - -void amdgpu_amdkfd_fini(void) -{ - if (kgd2kfd) { - kgd2kfd->exit(); - symbol_put(kgd2kfd_init); - } -} - -void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) -{ - if (kgd2kfd) - adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev, - adev->pdev, kfd2kgd); + adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev, + adev->pdev, kfd2kgd); } void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) @@ -184,7 +183,8 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, return -ENOMEM; r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, &(*mem)->bo); + AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 0, + &(*mem)->bo); if (r) { dev_err(adev->dev, "failed to allocate BO for amdkfd (%d)\n", r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 73f83a10ae14..8d689ab7e429 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -26,6 +26,7 @@ #define AMDGPU_AMDKFD_H_INCLUDED #include <linux/types.h> +#include <linux/mmu_context.h> #include <kgd_kfd_interface.h> struct amdgpu_device; @@ -39,8 +40,6 @@ struct kgd_mem { int amdgpu_amdkfd_init(void); void amdgpu_amdkfd_fini(void); -bool amdgpu_amdkfd_load_interface(struct amdgpu_device *adev); - void amdgpu_amdkfd_suspend(struct amdgpu_device *adev); int amdgpu_amdkfd_resume(struct amdgpu_device *adev); void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, @@ -62,4 +61,19 @@ uint64_t get_gpu_clock_counter(struct kgd_dev *kgd); uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd); +#define read_user_wptr(mmptr, wptr, dst) \ + ({ \ + bool valid = false; \ + if ((mmptr) && (wptr)) { \ + if ((mmptr) == current->mm) { \ + valid = !get_user((dst), (wptr)); \ + } else if (current->mm == NULL) { \ + use_mm(mmptr); \ + valid = !get_user((dst), (wptr)); \ + unuse_mm(mmptr); \ + } \ + } \ + valid; \ + }) + #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 5254562fd0f9..b9dbbf9cb8b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -39,6 +39,12 @@ #include "gmc/gmc_7_1_sh_mask.h" #include "cik_structs.h" +enum hqd_dequeue_request_type { + NO_ACTION = 0, + DRAIN_PIPE, + RESET_WAVES +}; + enum { MAX_TRAPID = 8, /* 3 bits in the bitfield. */ MAX_WATCH_ADDRESSES = 4 @@ -96,12 +102,15 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); @@ -126,6 +135,33 @@ static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid); + +/* Because of REG_GET_FIELD() being used, we put this function in the + * asic specific file. + */ +static int get_tile_config(struct kgd_dev *kgd, + struct tile_config *config) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + + config->gb_addr_config = adev->gfx.config.gb_addr_config; + config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFBANK); + config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFRANKS); + + config->tile_config_ptr = adev->gfx.config.tile_mode_array; + config->num_tile_configs = + ARRAY_SIZE(adev->gfx.config.tile_mode_array); + config->macro_tile_config_ptr = + adev->gfx.config.macrotile_mode_array; + config->num_macro_tile_configs = + ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); + + return 0; +} static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, @@ -150,7 +186,9 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid, .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, .write_vmid_invalidate_request = write_vmid_invalidate_request, - .get_fw_version = get_fw_version + .get_fw_version = get_fw_version, + .set_scratch_backing_va = set_scratch_backing_va, + .get_tile_config = get_tile_config, }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) @@ -186,7 +224,7 @@ static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, { struct amdgpu_device *adev = get_amdgpu_device(kgd); - uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, queue_id, 0); @@ -290,20 +328,38 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm) { struct amdgpu_device *adev = get_amdgpu_device(kgd); - uint32_t wptr_shadow, is_wptr_shadow_valid; struct cik_mqd *m; + uint32_t *mqd_hqd; + uint32_t reg, wptr_val, data; m = get_mqd(mqd); - is_wptr_shadow_valid = !get_user(wptr_shadow, wptr); - if (is_wptr_shadow_valid) - m->cp_hqd_pq_wptr = wptr_shadow; - acquire_queue(kgd, pipe_id, queue_id); - gfx_v7_0_mqd_commit(adev, m); + + /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */ + mqd_hqd = &m->cp_mqd_base_addr_lo; + + for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) + WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); + + /* Copy userspace write pointer value to register. + * Activate doorbell logic to monitor subsequent changes. + */ + data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, + CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); + + if (read_user_wptr(mm, wptr, wptr_val)) + WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); + + data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); + WREG32(mmCP_HQD_ACTIVE, data); + release_queue(kgd); return 0; @@ -382,30 +438,99 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id) { struct amdgpu_device *adev = get_amdgpu_device(kgd); uint32_t temp; - int timeout = utimeout; + enum hqd_dequeue_request_type type; + unsigned long flags, end_jiffies; + int retry; acquire_queue(kgd, pipe_id, queue_id); WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); - WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type); + switch (reset_type) { + case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: + type = DRAIN_PIPE; + break; + case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: + type = RESET_WAVES; + break; + default: + type = DRAIN_PIPE; + break; + } + + /* Workaround: If IQ timer is active and the wait time is close to or + * equal to 0, dequeueing is not safe. Wait until either the wait time + * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is + * cleared before continuing. Also, ensure wait times are set to at + * least 0x3. + */ + local_irq_save(flags); + preempt_disable(); + retry = 5000; /* wait for 500 usecs at maximum */ + while (true) { + temp = RREG32(mmCP_HQD_IQ_TIMER); + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { + pr_debug("HW is processing IQ\n"); + goto loop; + } + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) + == 3) /* SEM-rearm is safe */ + break; + /* Wait time 3 is safe for CP, but our MMIO read/write + * time is close to 1 microsecond, so check for 10 to + * leave more buffer room + */ + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) + >= 10) + break; + pr_debug("IQ timer is active\n"); + } else + break; +loop: + if (!retry) { + pr_err("CP HQD IQ timer status time out\n"); + break; + } + ndelay(100); + --retry; + } + retry = 1000; + while (true) { + temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); + if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) + break; + pr_debug("Dequeue request is pending\n"); + if (!retry) { + pr_err("CP HQD dequeue request time out\n"); + break; + } + ndelay(100); + --retry; + } + local_irq_restore(flags); + preempt_enable(); + + WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); + + end_jiffies = (utimeout * HZ / 1000) + jiffies; while (true) { temp = RREG32(mmCP_HQD_ACTIVE); - if (temp & CP_HQD_ACTIVE__ACTIVE_MASK) + if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) break; - if (timeout <= 0) { - pr_err("kfd: cp queue preemption time out.\n"); + if (time_after(jiffies, end_jiffies)) { + pr_err("cp queue preemption time out\n"); release_queue(kgd); return -ETIME; } - msleep(20); - timeout -= 20; + usleep_range(500, 1000); } release_queue(kgd); @@ -556,6 +681,16 @@ static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); } +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid) +{ + struct amdgpu_device *adev = (struct amdgpu_device *) kgd; + + lock_srbm(kgd, 0, 0, 0, vmid); + WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); + unlock_srbm(kgd); +} + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) { struct amdgpu_device *adev = (struct amdgpu_device *) kgd; @@ -566,42 +701,42 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) switch (type) { case KGD_ENGINE_PFP: hdr = (const union amdgpu_firmware_header *) - adev->gfx.pfp_fw->data; + adev->gfx.pfp_fw->data; break; case KGD_ENGINE_ME: hdr = (const union amdgpu_firmware_header *) - adev->gfx.me_fw->data; + adev->gfx.me_fw->data; break; case KGD_ENGINE_CE: hdr = (const union amdgpu_firmware_header *) - adev->gfx.ce_fw->data; + adev->gfx.ce_fw->data; break; case KGD_ENGINE_MEC1: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec_fw->data; + adev->gfx.mec_fw->data; break; case KGD_ENGINE_MEC2: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw->data; break; case KGD_ENGINE_RLC: hdr = (const union amdgpu_firmware_header *) - adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw->data; break; case KGD_ENGINE_SDMA1: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[0].fw->data; + adev->sdma.instance[0].fw->data; break; case KGD_ENGINE_SDMA2: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[1].fw->data; + adev->sdma.instance[1].fw->data; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index 133d06671e46..fb6e5dbd5a03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -39,6 +39,12 @@ #include "vi_structs.h" #include "vid.h" +enum hqd_dequeue_request_type { + NO_ACTION = 0, + DRAIN_PIPE, + RESET_WAVES +}; + struct cik_sdma_rlc_registers; /* @@ -55,12 +61,15 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id); static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, @@ -85,6 +94,33 @@ static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, uint8_t vmid); static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid); + +/* Because of REG_GET_FIELD() being used, we put this function in the + * asic specific file. + */ +static int get_tile_config(struct kgd_dev *kgd, + struct tile_config *config) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + + config->gb_addr_config = adev->gfx.config.gb_addr_config; + config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFBANK); + config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, + MC_ARB_RAMCFG, NOOFRANKS); + + config->tile_config_ptr = adev->gfx.config.tile_mode_array; + config->num_tile_configs = + ARRAY_SIZE(adev->gfx.config.tile_mode_array); + config->macro_tile_config_ptr = + adev->gfx.config.macrotile_mode_array; + config->num_macro_tile_configs = + ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); + + return 0; +} static const struct kfd2kgd_calls kfd2kgd = { .init_gtt_mem_allocation = alloc_gtt_mem, @@ -111,12 +147,15 @@ static const struct kfd2kgd_calls kfd2kgd = { .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, .write_vmid_invalidate_request = write_vmid_invalidate_request, - .get_fw_version = get_fw_version + .get_fw_version = get_fw_version, + .set_scratch_backing_va = set_scratch_backing_va, + .get_tile_config = get_tile_config, }; struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) { return (struct kfd2kgd_calls *)&kfd2kgd; + return (struct kfd2kgd_calls *)&kfd2kgd; } static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) @@ -147,7 +186,7 @@ static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, { struct amdgpu_device *adev = get_amdgpu_device(kgd); - uint32_t mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, queue_id, 0); @@ -216,7 +255,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) uint32_t mec; uint32_t pipe; - mec = (++pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); lock_srbm(kgd, mec, pipe, 0, 0); @@ -244,20 +283,67 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm) { - struct vi_mqd *m; - uint32_t shadow_wptr, valid_wptr; struct amdgpu_device *adev = get_amdgpu_device(kgd); + struct vi_mqd *m; + uint32_t *mqd_hqd; + uint32_t reg, wptr_val, data; m = get_mqd(mqd); - valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr)); - if (valid_wptr == 0) - m->cp_hqd_pq_wptr = shadow_wptr; - acquire_queue(kgd, pipe_id, queue_id); - gfx_v8_0_mqd_commit(adev, mqd); + + /* HIQ is set during driver init period with vmid set to 0*/ + if (m->cp_hqd_vmid == 0) { + uint32_t value, mec, pipe; + + mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); + + pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", + mec, pipe, queue_id); + value = RREG32(mmRLC_CP_SCHEDULERS); + value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, + ((mec << 5) | (pipe << 3) | queue_id | 0x80)); + WREG32(mmRLC_CP_SCHEDULERS, value); + } + + /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ + mqd_hqd = &m->cp_mqd_base_addr_lo; + + for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) + WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); + + /* Tonga errata: EOP RPTR/WPTR should be left unmodified. + * This is safe since EOP RPTR==WPTR for any inactive HQD + * on ASICs that do not support context-save. + * EOP writes/reads can start anywhere in the ring. + */ + if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) { + WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); + WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); + WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); + } + + for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) + WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); + + /* Copy userspace write pointer value to register. + * Activate doorbell logic to monitor subsequent changes. + */ + data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, + CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); + WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); + + if (read_user_wptr(mm, wptr, wptr_val)) + WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); + + data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); + WREG32(mmCP_HQD_ACTIVE, data); + release_queue(kgd); return 0; @@ -308,29 +394,102 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, + enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id) { struct amdgpu_device *adev = get_amdgpu_device(kgd); uint32_t temp; - int timeout = utimeout; + enum hqd_dequeue_request_type type; + unsigned long flags, end_jiffies; + int retry; + struct vi_mqd *m = get_mqd(mqd); acquire_queue(kgd, pipe_id, queue_id); - WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type); + if (m->cp_hqd_vmid == 0) + WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); + + switch (reset_type) { + case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: + type = DRAIN_PIPE; + break; + case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: + type = RESET_WAVES; + break; + default: + type = DRAIN_PIPE; + break; + } + /* Workaround: If IQ timer is active and the wait time is close to or + * equal to 0, dequeueing is not safe. Wait until either the wait time + * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is + * cleared before continuing. Also, ensure wait times are set to at + * least 0x3. + */ + local_irq_save(flags); + preempt_disable(); + retry = 5000; /* wait for 500 usecs at maximum */ + while (true) { + temp = RREG32(mmCP_HQD_IQ_TIMER); + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { + pr_debug("HW is processing IQ\n"); + goto loop; + } + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) + == 3) /* SEM-rearm is safe */ + break; + /* Wait time 3 is safe for CP, but our MMIO read/write + * time is close to 1 microsecond, so check for 10 to + * leave more buffer room + */ + if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) + >= 10) + break; + pr_debug("IQ timer is active\n"); + } else + break; +loop: + if (!retry) { + pr_err("CP HQD IQ timer status time out\n"); + break; + } + ndelay(100); + --retry; + } + retry = 1000; + while (true) { + temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); + if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) + break; + pr_debug("Dequeue request is pending\n"); + + if (!retry) { + pr_err("CP HQD dequeue request time out\n"); + break; + } + ndelay(100); + --retry; + } + local_irq_restore(flags); + preempt_enable(); + + WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); + + end_jiffies = (utimeout * HZ / 1000) + jiffies; while (true) { temp = RREG32(mmCP_HQD_ACTIVE); - if (temp & CP_HQD_ACTIVE__ACTIVE_MASK) + if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) break; - if (timeout <= 0) { - pr_err("kfd: cp queue preemption time out.\n"); + if (time_after(jiffies, end_jiffies)) { + pr_err("cp queue preemption time out.\n"); release_queue(kgd); return -ETIME; } - msleep(20); - timeout -= 20; + usleep_range(500, 1000); } release_queue(kgd); @@ -444,6 +603,16 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, return 0; } +static void set_scratch_backing_va(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid) +{ + struct amdgpu_device *adev = (struct amdgpu_device *) kgd; + + lock_srbm(kgd, 0, 0, 0, vmid); + WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); + unlock_srbm(kgd); +} + static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) { struct amdgpu_device *adev = (struct amdgpu_device *) kgd; @@ -454,42 +623,42 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) switch (type) { case KGD_ENGINE_PFP: hdr = (const union amdgpu_firmware_header *) - adev->gfx.pfp_fw->data; + adev->gfx.pfp_fw->data; break; case KGD_ENGINE_ME: hdr = (const union amdgpu_firmware_header *) - adev->gfx.me_fw->data; + adev->gfx.me_fw->data; break; case KGD_ENGINE_CE: hdr = (const union amdgpu_firmware_header *) - adev->gfx.ce_fw->data; + adev->gfx.ce_fw->data; break; case KGD_ENGINE_MEC1: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec_fw->data; + adev->gfx.mec_fw->data; break; case KGD_ENGINE_MEC2: hdr = (const union amdgpu_firmware_header *) - adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw->data; break; case KGD_ENGINE_RLC: hdr = (const union amdgpu_firmware_header *) - adev->gfx.rlc_fw->data; + adev->gfx.rlc_fw->data; break; case KGD_ENGINE_SDMA1: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[0].fw->data; + adev->sdma.instance[0].fw->data; break; case KGD_ENGINE_SDMA2: hdr = (const union amdgpu_firmware_header *) - adev->sdma.instance[1].fw->data; + adev->sdma.instance[1].fw->data; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c index 2fb299afc12b..63ec1e1bb6aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -81,7 +81,7 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, n = AMDGPU_BENCHMARK_ITERATIONS; r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, sdomain, 0, NULL, - NULL, &sobj); + NULL, 0, &sobj); if (r) { goto out_cleanup; } @@ -94,7 +94,7 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, goto out_cleanup; } r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, ddomain, 0, NULL, - NULL, &dobj); + NULL, 0, &dobj); if (r) { goto out_cleanup; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index d324e1c24028..59089e027f4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -136,7 +136,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, } bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); if (usermm) { @@ -156,11 +156,11 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, entry->tv.bo = &entry->robj->tbo; entry->tv.shared = !entry->robj->prime_shared_count; - if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS) + if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_GDS) gds_obj = entry->robj; - if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GWS) + if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_GWS) gws_obj = entry->robj; - if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_OA) + if (entry->robj->preferred_domains == AMDGPU_GEM_DOMAIN_OA) oa_obj = entry->robj; total_size += amdgpu_bo_size(entry->robj); @@ -270,7 +270,7 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, struct amdgpu_fpriv *fpriv = filp->driver_priv; union drm_amdgpu_bo_list *args = data; uint32_t handle = args->in.list_handle; - const void __user *uptr = (const void*)(uintptr_t)args->in.bo_info_ptr; + const void __user *uptr = u64_to_user_ptr(args->in.bo_info_ptr); struct drm_amdgpu_bo_list_entry *info; struct amdgpu_bo_list *list; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index a99e0bca6812..fd435a96481c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -124,7 +124,7 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE, true, domain, flags, NULL, &placement, NULL, - &obj); + 0, &obj); if (ret) { DRM_ERROR("(%d) bo create failed\n", ret); return ret; @@ -166,7 +166,7 @@ static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t h r = amdgpu_bo_reserve(obj, true); if (unlikely(r != 0)) return r; - r = amdgpu_bo_pin_restricted(obj, obj->prefered_domains, + r = amdgpu_bo_pin_restricted(obj, obj->preferred_domains, min_offset, max_offset, mcaddr); amdgpu_bo_unreserve(obj); return r; @@ -659,7 +659,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, info->version = (uint16_t)le32_to_cpu(header->header.ucode_version); if (CGS_UCODE_ID_CP_MEC == type) - info->image_size = (header->jt_offset) << 2; + info->image_size = le32_to_cpu(header->jt_offset) << 2; info->fw_version = amdgpu_get_firmware_version(cgs_device, type); info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 33789510e663..15d4a28d73bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -54,7 +54,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, *offset = data->offset; - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { amdgpu_bo_unref(&p->uf_entry.robj); @@ -90,7 +90,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) } /* get chunks */ - chunk_array_user = (uint64_t __user *)(uintptr_t)(cs->in.chunks); + chunk_array_user = u64_to_user_ptr(cs->in.chunks); if (copy_from_user(chunk_array, chunk_array_user, sizeof(uint64_t)*cs->in.num_chunks)) { ret = -EFAULT; @@ -110,7 +110,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) struct drm_amdgpu_cs_chunk user_chunk; uint32_t __user *cdata; - chunk_ptr = (void __user *)(uintptr_t)chunk_array[i]; + chunk_ptr = u64_to_user_ptr(chunk_array[i]); if (copy_from_user(&user_chunk, chunk_ptr, sizeof(struct drm_amdgpu_cs_chunk))) { ret = -EFAULT; @@ -121,7 +121,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) p->chunks[i].length_dw = user_chunk.length_dw; size = p->chunks[i].length_dw; - cdata = (void __user *)(uintptr_t)user_chunk.chunk_data; + cdata = u64_to_user_ptr(user_chunk.chunk_data); p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); if (p->chunks[i].kdata == NULL) { @@ -246,7 +246,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, } total_vram = adev->mc.real_vram_size - adev->vram_pin_size; - used_vram = atomic64_read(&adev->vram_usage); + used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; spin_lock(&adev->mm_stats.lock); @@ -292,7 +292,8 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, /* Do the same for visible VRAM if half of it is free */ if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { u64 total_vis_vram = adev->mc.visible_vram_size; - u64 used_vis_vram = atomic64_read(&adev->vram_vis_usage); + u64 used_vis_vram = + amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); if (used_vis_vram < total_vis_vram) { u64 free_vis_vram = total_vis_vram - used_vis_vram; @@ -348,11 +349,11 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, * that. */ if (p->bytes_moved_vis < p->bytes_moved_vis_threshold) - domain = bo->prefered_domains; + domain = bo->preferred_domains; else domain = bo->allowed_domains; } else { - domain = bo->prefered_domains; + domain = bo->preferred_domains; } } else { domain = bo->allowed_domains; @@ -673,10 +674,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, } error_validate: - if (r) { - amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); + if (r) ttm_eu_backoff_reservation(&p->ticket, &p->validated); - } error_free_pages: @@ -724,21 +723,18 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) * If error is set than unvalidate buffer, otherwise just free memory * used by parsing context. **/ -static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) +static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, + bool backoff) { - struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; unsigned i; - if (!error) { - amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); - + if (!error) ttm_eu_fence_buffer_objects(&parser->ticket, &parser->validated, parser->fence); - } else if (backoff) { + else if (backoff) ttm_eu_backoff_reservation(&parser->ticket, &parser->validated); - } for (i = 0; i < parser->num_post_dep_syncobjs; i++) drm_syncobj_put(parser->post_dep_syncobjs[i]); @@ -791,7 +787,8 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) if (amdgpu_sriov_vf(adev)) { struct dma_fence *f; - bo_va = vm->csa_bo_va; + + bo_va = fpriv->csa_va; BUG_ON(!bo_va); r = amdgpu_vm_bo_update(adev, bo_va, false); if (r) @@ -828,7 +825,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) } - r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); + r = amdgpu_vm_clear_moved(adev, vm, &p->job->sync); if (amdgpu_vm_debug && p->bo_list) { /* Invalidate all BOs to test for userspace bugs */ @@ -1437,7 +1434,7 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, if (fences == NULL) return -ENOMEM; - fences_user = (void __user *)(uintptr_t)(wait->in.fences); + fences_user = u64_to_user_ptr(wait->in.fences); if (copy_from_user(fences, fences_user, sizeof(struct drm_amdgpu_fence) * fence_count)) { r = -EFAULT; @@ -1490,7 +1487,7 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, addr > mapping->last) continue; - *bo = lobj->bo_va->bo; + *bo = lobj->bo_va->base.bo; return mapping; } @@ -1499,7 +1496,7 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, addr > mapping->last) continue; - *bo = lobj->bo_va->bo; + *bo = lobj->bo_va->base.bo; return mapping; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6279956e92a4..1a459ac63df4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -336,51 +336,16 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) { - int r; - - if (adev->vram_scratch.robj == NULL) { - r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, - PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &adev->vram_scratch.robj); - if (r) { - return r; - } - } - - r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); - if (unlikely(r != 0)) - return r; - r = amdgpu_bo_pin(adev->vram_scratch.robj, - AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); - if (r) { - amdgpu_bo_unreserve(adev->vram_scratch.robj); - return r; - } - r = amdgpu_bo_kmap(adev->vram_scratch.robj, - (void **)&adev->vram_scratch.ptr); - if (r) - amdgpu_bo_unpin(adev->vram_scratch.robj); - amdgpu_bo_unreserve(adev->vram_scratch.robj); - - return r; + return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, + &adev->vram_scratch.robj, + &adev->vram_scratch.gpu_addr, + (void **)&adev->vram_scratch.ptr); } static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) { - int r; - - if (adev->vram_scratch.robj == NULL) { - return; - } - r = amdgpu_bo_reserve(adev->vram_scratch.robj, true); - if (likely(r == 0)) { - amdgpu_bo_kunmap(adev->vram_scratch.robj); - amdgpu_bo_unpin(adev->vram_scratch.robj); - amdgpu_bo_unreserve(adev->vram_scratch.robj); - } - amdgpu_bo_unref(&adev->vram_scratch.robj); + amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); } /** @@ -539,7 +504,8 @@ static int amdgpu_wb_init(struct amdgpu_device *adev) int r; if (adev->wb.wb_obj == NULL) { - r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t), + /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ + r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, &adev->wb.wb_obj, &adev->wb.gpu_addr, (void **)&adev->wb.wb); @@ -570,47 +536,10 @@ static int amdgpu_wb_init(struct amdgpu_device *adev) int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) { unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); - if (offset < adev->wb.num_wb) { - __set_bit(offset, adev->wb.used); - *wb = offset; - return 0; - } else { - return -EINVAL; - } -} -/** - * amdgpu_wb_get_64bit - Allocate a wb entry - * - * @adev: amdgpu_device pointer - * @wb: wb index - * - * Allocate a wb slot for use by the driver (all asics). - * Returns 0 on success or -EINVAL on failure. - */ -int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb) -{ - unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, - adev->wb.num_wb, 0, 2, 7, 0); - if ((offset + 1) < adev->wb.num_wb) { + if (offset < adev->wb.num_wb) { __set_bit(offset, adev->wb.used); - __set_bit(offset + 1, adev->wb.used); - *wb = offset; - return 0; - } else { - return -EINVAL; - } -} - -int amdgpu_wb_get_256Bit(struct amdgpu_device *adev, u32 *wb) -{ - int i = 0; - unsigned long offset = bitmap_find_next_zero_area_off(adev->wb.used, - adev->wb.num_wb, 0, 8, 63, 0); - if ((offset + 7) < adev->wb.num_wb) { - for (i = 0; i < 8; i++) - __set_bit(offset + i, adev->wb.used); - *wb = offset; + *wb = offset * 8; /* convert to dw offset */ return 0; } else { return -EINVAL; @@ -632,39 +561,6 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) } /** - * amdgpu_wb_free_64bit - Free a wb entry - * - * @adev: amdgpu_device pointer - * @wb: wb index - * - * Free a wb slot allocated for use by the driver (all asics) - */ -void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb) -{ - if ((wb + 1) < adev->wb.num_wb) { - __clear_bit(wb, adev->wb.used); - __clear_bit(wb + 1, adev->wb.used); - } -} - -/** - * amdgpu_wb_free_256bit - Free a wb entry - * - * @adev: amdgpu_device pointer - * @wb: wb index - * - * Free a wb slot allocated for use by the driver (all asics) - */ -void amdgpu_wb_free_256bit(struct amdgpu_device *adev, u32 wb) -{ - int i = 0; - - if ((wb + 7) < adev->wb.num_wb) - for (i = 0; i < 8; i++) - __clear_bit(wb + i, adev->wb.used); -} - -/** * amdgpu_vram_location - try to find VRAM location * @adev: amdgpu device structure holding all necessary informations * @mc: memory controller structure holding memory informations @@ -1180,6 +1076,13 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) amdgpu_gtt_size = -1; } + /* valid range is between 4 and 9 inclusive */ + if (amdgpu_vm_fragment_size != -1 && + (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { + dev_warn(adev->dev, "valid range is between 4 and 9\n"); + amdgpu_vm_fragment_size = -1; + } + amdgpu_check_vm_size(adev); amdgpu_check_block_size(adev); @@ -1948,7 +1851,8 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev) AMD_IP_BLOCK_TYPE_DCE, AMD_IP_BLOCK_TYPE_GFX, AMD_IP_BLOCK_TYPE_SDMA, - AMD_IP_BLOCK_TYPE_VCE, + AMD_IP_BLOCK_TYPE_UVD, + AMD_IP_BLOCK_TYPE_VCE }; for (i = 0; i < ARRAY_SIZE(ip_order); i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index cdf2ab20166a..6ad243293a78 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -482,7 +482,7 @@ static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - drm_gem_object_unreference_unlocked(amdgpu_fb->obj); + drm_gem_object_put_unlocked(amdgpu_fb->obj); drm_framebuffer_cleanup(fb); kfree(amdgpu_fb); } @@ -542,14 +542,14 @@ amdgpu_user_framebuffer_create(struct drm_device *dev, amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); if (amdgpu_fb == NULL) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(-ENOMEM); } ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); if (ret) { kfree(amdgpu_fb); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 5e9ce8a29669..e39ec981b11c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -68,9 +68,10 @@ * - 3.16.0 - Add reserved vmid support * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. * - 3.18.0 - Export gpu always on cu bitmap + * - 3.19.0 - Add support for UVD MJPEG decode */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 18 +#define KMS_DRIVER_MINOR 19 #define KMS_DRIVER_PATCHLEVEL 0 int amdgpu_vram_limit = 0; @@ -94,6 +95,7 @@ unsigned amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color = 0; int amdgpu_vm_size = -1; +int amdgpu_vm_fragment_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; @@ -183,6 +185,9 @@ module_param_named(deep_color, amdgpu_deep_color, int, 0444); MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); module_param_named(vm_size, amdgpu_vm_size, int, 0444); +MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); +module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); + MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 0a8ee2411180..9afa9c097e1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -118,7 +118,7 @@ static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) amdgpu_bo_unpin(abo); amdgpu_bo_unreserve(abo); } - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); } static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, @@ -250,7 +250,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start; info->fix.smem_start = adev->mc.aper_base + tmp; info->fix.smem_len = amdgpu_bo_size(abo); - info->screen_base = abo->kptr; + info->screen_base = amdgpu_bo_kptr(abo); info->screen_size = amdgpu_bo_size(abo); drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); @@ -280,7 +280,7 @@ out: } if (fb && ret) { - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); drm_framebuffer_unregister_private(fb); drm_framebuffer_cleanup(fb); kfree(fb); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 5cc4987cd887..94c1e2e8e34c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -144,7 +144,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &adev->gart.robj); + NULL, NULL, 0, &adev->gart.robj); if (r) { return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 917ac5e074a0..7171968f261e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -59,7 +59,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, retry: r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, - flags, NULL, NULL, &robj); + flags, NULL, NULL, 0, &robj); if (r) { if (r != -ERESTARTSYS) { if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { @@ -91,7 +91,7 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) spin_lock(&file->table_lock); idr_for_each_entry(&file->object_idr, gobj, handle) { WARN_ONCE(1, "And also active allocations!\n"); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); } idr_destroy(&file->object_idr); spin_unlock(&file->table_lock); @@ -225,9 +225,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_CPU_GTT_USWC | - AMDGPU_GEM_CREATE_VRAM_CLEARED| - AMDGPU_GEM_CREATE_SHADOW | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) + AMDGPU_GEM_CREATE_VRAM_CLEARED)) return -EINVAL; /* reject invalid gem domains */ @@ -263,7 +261,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (r) return r; @@ -306,7 +304,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return r; bo = gem_to_amdgpu_bo(gobj); - bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); if (r) @@ -341,7 +339,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (r) return r; @@ -355,7 +353,7 @@ unlock_mmap_sem: up_read(¤t->mm->mmap_sem); release_object: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -374,11 +372,11 @@ int amdgpu_mode_dumb_mmap(struct drm_file *filp, robj = gem_to_amdgpu_bo(gobj); if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return -EPERM; } *offset_p = amdgpu_bo_mmap_offset(robj); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return 0; } @@ -448,7 +446,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, } else r = ret; - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -491,7 +489,7 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, unreserve: amdgpu_bo_unreserve(robj); out: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -623,7 +621,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, switch (args->operation) { case AMDGPU_VA_OP_MAP: - r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, + r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, args->map_size); if (r) goto error_backoff; @@ -643,7 +641,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, args->map_size); break; case AMDGPU_VA_OP_REPLACE: - r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, + r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, args->map_size); if (r) goto error_backoff; @@ -664,7 +662,7 @@ error_backoff: ttm_eu_backoff_reservation(&ticket, &list); error_unref: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -689,11 +687,11 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, switch (args->op) { case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { struct drm_amdgpu_gem_create_in info; - void __user *out = (void __user *)(uintptr_t)args->value; + void __user *out = u64_to_user_ptr(args->value); info.bo_size = robj->gem_base.size; info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; - info.domains = robj->prefered_domains; + info.domains = robj->preferred_domains; info.domain_flags = robj->flags; amdgpu_bo_unreserve(robj); if (copy_to_user(out, &info, sizeof(info))) @@ -711,10 +709,10 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, amdgpu_bo_unreserve(robj); break; } - robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | + robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_CPU); - robj->allowed_domains = robj->prefered_domains; + robj->allowed_domains = robj->preferred_domains; if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; @@ -726,7 +724,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, } out: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -754,7 +752,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, r = drm_gem_handle_create(file_priv, gobj, &handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (r) { return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 5e6b90c6794f..9e05e257729f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -28,7 +28,7 @@ struct amdgpu_gtt_mgr { struct drm_mm mm; spinlock_t lock; - uint64_t available; + atomic64_t available; }; /** @@ -54,7 +54,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man, size = (adev->mc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); - mgr->available = p_size; + atomic64_set(&mgr->available, p_size); man->priv = mgr; return 0; } @@ -153,15 +153,6 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, return r; } -void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager *man) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); - struct amdgpu_gtt_mgr *mgr = man->priv; - - seq_printf(m, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n", - man->size, mgr->available, (u64)atomic64_read(&adev->gtt_usage) >> 20); - -} /** * amdgpu_gtt_mgr_new - allocate a new node * @@ -182,11 +173,11 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, int r; spin_lock(&mgr->lock); - if (mgr->available < mem->num_pages) { + if (atomic64_read(&mgr->available) < mem->num_pages) { spin_unlock(&mgr->lock); return 0; } - mgr->available -= mem->num_pages; + atomic64_sub(mem->num_pages, &mgr->available); spin_unlock(&mgr->lock); node = kzalloc(sizeof(*node), GFP_KERNEL); @@ -213,9 +204,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, return 0; err_out: - spin_lock(&mgr->lock); - mgr->available += mem->num_pages; - spin_unlock(&mgr->lock); + atomic64_add(mem->num_pages, &mgr->available); return r; } @@ -242,30 +231,47 @@ static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man, spin_lock(&mgr->lock); if (node->start != AMDGPU_BO_INVALID_OFFSET) drm_mm_remove_node(node); - mgr->available += mem->num_pages; spin_unlock(&mgr->lock); + atomic64_add(mem->num_pages, &mgr->available); kfree(node); mem->mm_node = NULL; } /** + * amdgpu_gtt_mgr_usage - return usage of GTT domain + * + * @man: TTM memory type manager + * + * Return how many bytes are used in the GTT domain + */ +uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man) +{ + struct amdgpu_gtt_mgr *mgr = man->priv; + + return (u64)(man->size - atomic64_read(&mgr->available)) * PAGE_SIZE; +} + +/** * amdgpu_gtt_mgr_debug - dump VRAM table * * @man: TTM memory type manager - * @prefix: text prefix + * @printer: DRM printer to use * * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_printer p = drm_debug_printer(prefix); spin_lock(&mgr->lock); - drm_mm_print(&mgr->mm, &p); + drm_mm_print(&mgr->mm, printer); spin_unlock(&mgr->lock); + + drm_printf(printer, "man size:%llu pages, gtt available:%llu pages, usage:%lluMB\n", + man->size, (u64)atomic64_read(&mgr->available), + amdgpu_gtt_mgr_usage(man) >> 20); } const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 09f833255ba1..e16229000a98 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -158,7 +158,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) "Error during ACPI methods call\n"); } - amdgpu_amdkfd_load_interface(adev); amdgpu_amdkfd_device_probe(adev); amdgpu_amdkfd_device_init(adev); @@ -456,13 +455,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VRAM_USAGE: - ui64 = atomic64_read(&adev->vram_usage); + ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VIS_VRAM_USAGE: - ui64 = atomic64_read(&adev->vram_vis_usage); + ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_GTT_USAGE: - ui64 = atomic64_read(&adev->gtt_usage); + ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_GDS_CONFIG: { struct drm_amdgpu_info_gds gds_info; @@ -498,7 +497,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file mem.vram.total_heap_size = adev->mc.real_vram_size; mem.vram.usable_heap_size = adev->mc.real_vram_size - adev->vram_pin_size; - mem.vram.heap_usage = atomic64_read(&adev->vram_usage); + mem.vram.heap_usage = + amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; mem.cpu_accessible_vram.total_heap_size = @@ -507,7 +507,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file adev->mc.visible_vram_size - (adev->vram_pin_size - adev->invisible_pin_size); mem.cpu_accessible_vram.heap_usage = - atomic64_read(&adev->vram_vis_usage); + amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); mem.cpu_accessible_vram.max_allocation = mem.cpu_accessible_vram.usable_heap_size * 3 / 4; @@ -515,7 +515,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file mem.gtt.total_heap_size *= PAGE_SIZE; mem.gtt.usable_heap_size = mem.gtt.total_heap_size - adev->gart_pin_size; - mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage); + mem.gtt.heap_usage = + amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]); mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; return copy_to_user(out, &mem, @@ -589,11 +590,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); - dev_info.pte_fragment_size = - (1 << AMDGPU_LOG2_PAGES_PER_FRAG(adev)) * - AMDGPU_GPU_PAGE_SIZE; + dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; - dev_info.cu_active_number = adev->gfx.cu_info.number; dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; dev_info.ce_ram_size = adev->gfx.ce_ram_size; @@ -842,7 +840,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) } if (amdgpu_sriov_vf(adev)) { - r = amdgpu_map_static_csa(adev, &fpriv->vm); + r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va); if (r) goto out_suspend; } @@ -895,8 +893,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, if (amdgpu_sriov_vf(adev)) { /* TODO: how to handle reserve failure */ BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); - amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va); - fpriv->vm.csa_bo_va = NULL; + amdgpu_vm_bo_rmv(adev, fpriv->csa_va); + fpriv->csa_va = NULL; amdgpu_bo_unreserve(adev->virt.csa_obj); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 3ec43cf9ad78..e7e899190bef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -37,55 +37,6 @@ #include "amdgpu.h" #include "amdgpu_trace.h" - - -static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, - struct ttm_mem_reg *mem) -{ - if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size) - return 0; - - return ((mem->start << PAGE_SHIFT) + mem->size) > - adev->mc.visible_vram_size ? - adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : - mem->size; -} - -static void amdgpu_update_memory_usage(struct amdgpu_device *adev, - struct ttm_mem_reg *old_mem, - struct ttm_mem_reg *new_mem) -{ - u64 vis_size; - if (!adev) - return; - - if (new_mem) { - switch (new_mem->mem_type) { - case TTM_PL_TT: - atomic64_add(new_mem->size, &adev->gtt_usage); - break; - case TTM_PL_VRAM: - atomic64_add(new_mem->size, &adev->vram_usage); - vis_size = amdgpu_get_vis_part_size(adev, new_mem); - atomic64_add(vis_size, &adev->vram_vis_usage); - break; - } - } - - if (old_mem) { - switch (old_mem->mem_type) { - case TTM_PL_TT: - atomic64_sub(old_mem->size, &adev->gtt_usage); - break; - case TTM_PL_VRAM: - atomic64_sub(old_mem->size, &adev->vram_usage); - vis_size = amdgpu_get_vis_part_size(adev, old_mem); - atomic64_sub(vis_size, &adev->vram_vis_usage); - break; - } - } -} - static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); @@ -94,7 +45,6 @@ static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) bo = container_of(tbo, struct amdgpu_bo, tbo); amdgpu_bo_kunmap(bo); - amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL); drm_gem_object_release(&bo->gem_base); amdgpu_bo_unref(&bo->parent); @@ -220,7 +170,7 @@ static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, } /** - * amdgpu_bo_create_kernel - create BO for kernel use + * amdgpu_bo_create_reserved - create reserved BO for kernel use * * @adev: amdgpu device object * @size: size for the new BO @@ -230,24 +180,30 @@ static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, * @gpu_addr: GPU addr of the pinned BO * @cpu_addr: optional CPU address mapping * - * Allocates and pins a BO for kernel internal use. + * Allocates and pins a BO for kernel internal use, and returns it still + * reserved. * * Returns 0 on success, negative error code otherwise. */ -int amdgpu_bo_create_kernel(struct amdgpu_device *adev, - unsigned long size, int align, - u32 domain, struct amdgpu_bo **bo_ptr, - u64 *gpu_addr, void **cpu_addr) +int amdgpu_bo_create_reserved(struct amdgpu_device *adev, + unsigned long size, int align, + u32 domain, struct amdgpu_bo **bo_ptr, + u64 *gpu_addr, void **cpu_addr) { + bool free = false; int r; - r = amdgpu_bo_create(adev, size, align, true, domain, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, bo_ptr); - if (r) { - dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r); - return r; + if (!*bo_ptr) { + r = amdgpu_bo_create(adev, size, align, true, domain, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, + NULL, NULL, 0, bo_ptr); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", + r); + return r; + } + free = true; } r = amdgpu_bo_reserve(*bo_ptr, false); @@ -270,20 +226,52 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev, } } - amdgpu_bo_unreserve(*bo_ptr); - return 0; error_unreserve: amdgpu_bo_unreserve(*bo_ptr); error_free: - amdgpu_bo_unref(bo_ptr); + if (free) + amdgpu_bo_unref(bo_ptr); return r; } /** + * amdgpu_bo_create_kernel - create BO for kernel use + * + * @adev: amdgpu device object + * @size: size for the new BO + * @align: alignment for the new BO + * @domain: where to place it + * @bo_ptr: resulting BO + * @gpu_addr: GPU addr of the pinned BO + * @cpu_addr: optional CPU address mapping + * + * Allocates and pins a BO for kernel internal use. + * + * Returns 0 on success, negative error code otherwise. + */ +int amdgpu_bo_create_kernel(struct amdgpu_device *adev, + unsigned long size, int align, + u32 domain, struct amdgpu_bo **bo_ptr, + u64 *gpu_addr, void **cpu_addr) +{ + int r; + + r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, + gpu_addr, cpu_addr); + + if (r) + return r; + + amdgpu_bo_unreserve(*bo_ptr); + + return 0; +} + +/** * amdgpu_bo_free_kernel - free BO for kernel use * * @bo: amdgpu BO to free @@ -318,6 +306,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, struct sg_table *sg, struct ttm_placement *placement, struct reservation_object *resv, + uint64_t init_value, struct amdgpu_bo **bo_ptr) { struct amdgpu_bo *bo; @@ -352,13 +341,13 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, } INIT_LIST_HEAD(&bo->shadow_list); INIT_LIST_HEAD(&bo->va); - bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | + bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA); - bo->allowed_domains = bo->prefered_domains; + bo->allowed_domains = bo->preferred_domains; if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; @@ -418,7 +407,7 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { struct dma_fence *fence; - r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence); + r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence); if (unlikely(r)) goto fail_unreserve; @@ -470,6 +459,7 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, &placement, bo->tbo.resv, + 0, &bo->shadow); if (!r) { bo->shadow->parent = amdgpu_bo_ref(bo); @@ -481,11 +471,15 @@ static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, return r; } +/* init_value will only take effect when flags contains + * AMDGPU_GEM_CREATE_VRAM_CLEARED. + */ int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags, struct sg_table *sg, struct reservation_object *resv, + uint64_t init_value, struct amdgpu_bo **bo_ptr) { struct ttm_placement placement = {0}; @@ -500,7 +494,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel, domain, flags, sg, &placement, - resv, bo_ptr); + resv, init_value, bo_ptr); if (r) return r; @@ -562,7 +556,7 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo) if (bo->pin_count) return 0; - domain = bo->prefered_domains; + domain = bo->preferred_domains; retry: amdgpu_ttm_placement_from_domain(bo, domain); @@ -609,16 +603,16 @@ err: int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) { - bool is_iomem; + void *kptr; long r; if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) return -EPERM; - if (bo->kptr) { - if (ptr) { - *ptr = bo->kptr; - } + kptr = amdgpu_bo_kptr(bo); + if (kptr) { + if (ptr) + *ptr = kptr; return 0; } @@ -631,19 +625,23 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) if (r) return r; - bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); if (ptr) - *ptr = bo->kptr; + *ptr = amdgpu_bo_kptr(bo); return 0; } +void *amdgpu_bo_kptr(struct amdgpu_bo *bo) +{ + bool is_iomem; + + return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); +} + void amdgpu_bo_kunmap(struct amdgpu_bo *bo) { - if (bo->kptr == NULL) - return; - bo->kptr = NULL; - ttm_bo_kunmap(&bo->kmap); + if (bo->kmap.bo) + ttm_bo_kunmap(&bo->kmap); } struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) @@ -944,8 +942,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, return; /* move_notify is called before move happens */ - amdgpu_update_memory_usage(adev, &bo->mem, new_mem); - trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 833b172a2c2a..a288fa6d72c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -33,6 +33,61 @@ #define AMDGPU_BO_INVALID_OFFSET LONG_MAX +/* bo virtual addresses in a vm */ +struct amdgpu_bo_va_mapping { + struct list_head list; + struct rb_node rb; + uint64_t start; + uint64_t last; + uint64_t __subtree_last; + uint64_t offset; + uint64_t flags; +}; + +/* User space allocated BO in a VM */ +struct amdgpu_bo_va { + struct amdgpu_vm_bo_base base; + + /* protected by bo being reserved */ + struct dma_fence *last_pt_update; + unsigned ref_count; + + /* mappings for this bo_va */ + struct list_head invalids; + struct list_head valids; +}; + +struct amdgpu_bo { + /* Protected by tbo.reserved */ + u32 preferred_domains; + u32 allowed_domains; + struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; + struct ttm_placement placement; + struct ttm_buffer_object tbo; + struct ttm_bo_kmap_obj kmap; + u64 flags; + unsigned pin_count; + u64 tiling_flags; + u64 metadata_flags; + void *metadata; + u32 metadata_size; + unsigned prime_shared_count; + /* list of all virtual address to which this bo is associated to */ + struct list_head va; + /* Constant after initialization */ + struct drm_gem_object gem_base; + struct amdgpu_bo *parent; + struct amdgpu_bo *shadow; + + struct ttm_bo_kmap_obj dma_buf_vmap; + struct amdgpu_mn *mn; + + union { + struct list_head mn_list; + struct list_head shadow_list; + }; +}; + /** * amdgpu_mem_type_to_domain - return domain corresponding to mem_type * @mem_type: ttm memory type @@ -132,6 +187,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bool kernel, u32 domain, u64 flags, struct sg_table *sg, struct reservation_object *resv, + uint64_t init_value, struct amdgpu_bo **bo_ptr); int amdgpu_bo_create_restricted(struct amdgpu_device *adev, unsigned long size, int byte_align, @@ -139,7 +195,12 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev, struct sg_table *sg, struct ttm_placement *placement, struct reservation_object *resv, + uint64_t init_value, struct amdgpu_bo **bo_ptr); +int amdgpu_bo_create_reserved(struct amdgpu_device *adev, + unsigned long size, int align, + u32 domain, struct amdgpu_bo **bo_ptr, + u64 *gpu_addr, void **cpu_addr); int amdgpu_bo_create_kernel(struct amdgpu_device *adev, unsigned long size, int align, u32 domain, struct amdgpu_bo **bo_ptr, @@ -147,6 +208,7 @@ int amdgpu_bo_create_kernel(struct amdgpu_device *adev, void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, void **cpu_addr); int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); +void *amdgpu_bo_kptr(struct amdgpu_bo *bo); void amdgpu_bo_kunmap(struct amdgpu_bo *bo); struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); void amdgpu_bo_unref(struct amdgpu_bo **bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h index c19c4d138751..f21a7716b90e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h @@ -30,6 +30,7 @@ struct cg_flag_name const char *name; }; +void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); int amdgpu_pm_sysfs_init(struct amdgpu_device *adev); void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev); void amdgpu_pm_print_power_states(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index 6bdc866570ab..5b3f92891f89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -69,7 +69,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, ww_mutex_lock(&resv->lock, NULL); ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false, - AMDGPU_GEM_DOMAIN_GTT, 0, sg, resv, &bo); + AMDGPU_GEM_DOMAIN_GTT, 0, sg, resv, 0, &bo); ww_mutex_unlock(&resv->lock); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 15b7149d1204..6c5646b48d1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -184,47 +184,22 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, return r; } - if (ring->funcs->support_64bit_ptrs) { - r = amdgpu_wb_get_64bit(adev, &ring->rptr_offs); - if (r) { - dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); - return r; - } - - r = amdgpu_wb_get_64bit(adev, &ring->wptr_offs); - if (r) { - dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); - return r; - } - - } else { - r = amdgpu_wb_get(adev, &ring->rptr_offs); - if (r) { - dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); - return r; - } - - r = amdgpu_wb_get(adev, &ring->wptr_offs); - if (r) { - dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); - return r; - } - + r = amdgpu_wb_get(adev, &ring->rptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); + return r; } - if (amdgpu_sriov_vf(adev) && ring->funcs->type == AMDGPU_RING_TYPE_GFX) { - r = amdgpu_wb_get_256Bit(adev, &ring->fence_offs); - if (r) { - dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); - return r; - } + r = amdgpu_wb_get(adev, &ring->wptr_offs); + if (r) { + dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); + return r; + } - } else { - r = amdgpu_wb_get(adev, &ring->fence_offs); - if (r) { - dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); - return r; - } + r = amdgpu_wb_get(adev, &ring->fence_offs); + if (r) { + dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); + return r; } r = amdgpu_wb_get(adev, &ring->cond_exe_offs); @@ -286,19 +261,15 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) { ring->ready = false; - if (ring->funcs->support_64bit_ptrs) { - amdgpu_wb_free_64bit(ring->adev, ring->rptr_offs); - amdgpu_wb_free_64bit(ring->adev, ring->wptr_offs); - } else { - amdgpu_wb_free(ring->adev, ring->rptr_offs); - amdgpu_wb_free(ring->adev, ring->wptr_offs); - } + /* Not to finish a ring which is not initialized */ + if (!(ring->adev) || !(ring->adev->rings[ring->idx])) + return; + + amdgpu_wb_free(ring->adev, ring->rptr_offs); + amdgpu_wb_free(ring->adev, ring->wptr_offs); amdgpu_wb_free(ring->adev, ring->cond_exe_offs); - if (amdgpu_sriov_vf(ring->adev) && ring->funcs->type == AMDGPU_RING_TYPE_GFX) - amdgpu_wb_free_256bit(ring->adev, ring->fence_offs); - else - amdgpu_wb_free(ring->adev, ring->fence_offs); + amdgpu_wb_free(ring->adev, ring->fence_offs); amdgpu_bo_free_kernel(&ring->ring_obj, &ring->gpu_addr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index 5ca75a456ad2..3144400435b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -64,7 +64,7 @@ int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&sa_manager->flist[i]); r = amdgpu_bo_create(adev, size, align, true, domain, - 0, NULL, NULL, &sa_manager->bo); + 0, NULL, NULL, 0, &sa_manager->bo); if (r) { dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index a6899180b265..c586f44312f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -244,6 +244,12 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct dma_fence *f = e->fence; struct amd_sched_fence *s_fence = to_amd_sched_fence(f); + if (dma_fence_is_signaled(f)) { + hash_del(&e->node); + dma_fence_put(f); + kmem_cache_free(amdgpu_sync_slab, e); + continue; + } if (ring && s_fence) { /* For fences from the same ring it is sufficient * when they are scheduled. @@ -256,13 +262,6 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, } } - if (dma_fence_is_signaled(f)) { - hash_del(&e->node); - dma_fence_put(f); - kmem_cache_free(amdgpu_sync_slab, e); - continue; - } - return f; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index 3c4d7574d704..ed8c3739015b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c @@ -61,7 +61,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, - NULL, NULL, &vram_obj); + NULL, NULL, 0, &vram_obj); if (r) { DRM_ERROR("Failed to create VRAM object\n"); goto out_cleanup; @@ -82,7 +82,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT, 0, NULL, - NULL, gtt_obj + i); + NULL, 0, gtt_obj + i); if (r) { DRM_ERROR("Failed to create GTT object %d\n", i); goto out_lclean; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 509f7a63d40c..1c88bd5e29ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -14,6 +14,62 @@ #define AMDGPU_JOB_GET_TIMELINE_NAME(job) \ job->base.s_fence->finished.ops->get_timeline_name(&job->base.s_fence->finished) +TRACE_EVENT(amdgpu_ttm_tt_populate, + TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address), + TP_ARGS(adev, dma_address, phys_address), + TP_STRUCT__entry( + __field(uint16_t, domain) + __field(uint8_t, bus) + __field(uint8_t, slot) + __field(uint8_t, func) + __field(uint64_t, dma) + __field(uint64_t, phys) + ), + TP_fast_assign( + __entry->domain = pci_domain_nr(adev->pdev->bus); + __entry->bus = adev->pdev->bus->number; + __entry->slot = PCI_SLOT(adev->pdev->devfn); + __entry->func = PCI_FUNC(adev->pdev->devfn); + __entry->dma = dma_address; + __entry->phys = phys_address; + ), + TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx", + (unsigned)__entry->domain, + (unsigned)__entry->bus, + (unsigned)__entry->slot, + (unsigned)__entry->func, + (unsigned long long)__entry->dma, + (unsigned long long)__entry->phys) +); + +TRACE_EVENT(amdgpu_ttm_tt_unpopulate, + TP_PROTO(struct amdgpu_device *adev, uint64_t dma_address, uint64_t phys_address), + TP_ARGS(adev, dma_address, phys_address), + TP_STRUCT__entry( + __field(uint16_t, domain) + __field(uint8_t, bus) + __field(uint8_t, slot) + __field(uint8_t, func) + __field(uint64_t, dma) + __field(uint64_t, phys) + ), + TP_fast_assign( + __entry->domain = pci_domain_nr(adev->pdev->bus); + __entry->bus = adev->pdev->bus->number; + __entry->slot = PCI_SLOT(adev->pdev->devfn); + __entry->func = PCI_FUNC(adev->pdev->devfn); + __entry->dma = dma_address; + __entry->phys = phys_address; + ), + TP_printk("%04x:%02x:%02x.%x: 0x%llx => 0x%llx", + (unsigned)__entry->domain, + (unsigned)__entry->bus, + (unsigned)__entry->slot, + (unsigned)__entry->func, + (unsigned long long)__entry->dma, + (unsigned long long)__entry->phys) +); + TRACE_EVENT(amdgpu_mm_rreg, TP_PROTO(unsigned did, uint32_t reg, uint32_t value), TP_ARGS(did, reg, value), @@ -105,12 +161,12 @@ TRACE_EVENT(amdgpu_bo_create, __entry->bo = bo; __entry->pages = bo->tbo.num_pages; __entry->type = bo->tbo.mem.mem_type; - __entry->prefer = bo->prefered_domains; + __entry->prefer = bo->preferred_domains; __entry->allow = bo->allowed_domains; __entry->visible = bo->flags; ), - TP_printk("bo=%p, pages=%u, type=%d, prefered=%d, allowed=%d, visible=%d", + TP_printk("bo=%p, pages=%u, type=%d, preferred=%d, allowed=%d, visible=%d", __entry->bo, __entry->pages, __entry->type, __entry->prefer, __entry->allow, __entry->visible) ); @@ -228,7 +284,7 @@ TRACE_EVENT(amdgpu_vm_bo_map, ), TP_fast_assign( - __entry->bo = bo_va ? bo_va->bo : NULL; + __entry->bo = bo_va ? bo_va->base.bo : NULL; __entry->start = mapping->start; __entry->last = mapping->last; __entry->offset = mapping->offset; @@ -252,7 +308,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, ), TP_fast_assign( - __entry->bo = bo_va->bo; + __entry->bo = bo_va->base.bo; __entry->start = mapping->start; __entry->last = mapping->last; __entry->offset = mapping->offset; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index e6f9a54c959d..8b2c294f6f79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -43,6 +43,7 @@ #include <linux/pagemap.h> #include <linux/debugfs.h> #include "amdgpu.h" +#include "amdgpu_trace.h" #include "bif/bif_4_1_d.h" #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) @@ -662,6 +663,38 @@ release_pages: return r; } +static void amdgpu_trace_dma_map(struct ttm_tt *ttm) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + if (unlikely(trace_amdgpu_ttm_tt_populate_enabled())) { + for (i = 0; i < ttm->num_pages; i++) { + trace_amdgpu_ttm_tt_populate( + adev, + gtt->ttm.dma_address[i], + page_to_phys(ttm->pages[i])); + } + } +} + +static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + if (unlikely(trace_amdgpu_ttm_tt_unpopulate_enabled())) { + for (i = 0; i < ttm->num_pages; i++) { + trace_amdgpu_ttm_tt_unpopulate( + adev, + gtt->ttm.dma_address[i], + page_to_phys(ttm->pages[i])); + } + } +} + /* prepare the sg table with the user pages */ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) { @@ -688,6 +721,8 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm) drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, gtt->ttm.dma_address, ttm->num_pages); + amdgpu_trace_dma_map(ttm); + return 0; release_sg: @@ -721,6 +756,8 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm) put_page(page); } + amdgpu_trace_dma_unmap(ttm); + sg_free_table(ttm->sg); } @@ -753,7 +790,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) { struct amdgpu_ttm_tt *gtt = (void*)ttm; - int r; + int r = 0; if (gtt->userptr) { r = amdgpu_ttm_tt_pin_userptr(ttm); @@ -892,7 +929,7 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) { - struct amdgpu_device *adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev); struct amdgpu_ttm_tt *gtt = (void *)ttm; unsigned i; int r; @@ -915,14 +952,14 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, gtt->ttm.dma_address, ttm->num_pages); ttm->state = tt_unbound; - return 0; + r = 0; + goto trace_mappings; } - adev = amdgpu_ttm_adev(ttm->bdev); - #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { - return ttm_dma_populate(>t->ttm, adev->dev); + r = ttm_dma_populate(>t->ttm, adev->dev); + goto trace_mappings; } #endif @@ -945,7 +982,12 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm) return -EFAULT; } } - return 0; + + r = 0; +trace_mappings: + if (likely(!r)) + amdgpu_trace_dma_map(ttm); + return r; } static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) @@ -966,6 +1008,8 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm) adev = amdgpu_ttm_adev(ttm->bdev); + amdgpu_trace_dma_unmap(ttm); + #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { ttm_dma_unpopulate(>t->ttm, adev->dev); @@ -1232,23 +1276,12 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) /* Change the size here instead of the init above so only lpfn is affected */ amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); - r = amdgpu_bo_create(adev, adev->mc.stolen_size, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &adev->stollen_vga_memory); - if (r) { - return r; - } - r = amdgpu_bo_reserve(adev->stollen_vga_memory, false); + r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->stolen_vga_memory, + NULL, NULL); if (r) return r; - r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL); - amdgpu_bo_unreserve(adev->stollen_vga_memory); - if (r) { - amdgpu_bo_unref(&adev->stollen_vga_memory); - return r; - } DRM_INFO("amdgpu: %uM of VRAM memory ready\n", (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); @@ -1319,13 +1352,13 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) if (!adev->mman.initialized) return; amdgpu_ttm_debugfs_fini(adev); - if (adev->stollen_vga_memory) { - r = amdgpu_bo_reserve(adev->stollen_vga_memory, true); + if (adev->stolen_vga_memory) { + r = amdgpu_bo_reserve(adev->stolen_vga_memory, true); if (r == 0) { - amdgpu_bo_unpin(adev->stollen_vga_memory); - amdgpu_bo_unreserve(adev->stollen_vga_memory); + amdgpu_bo_unpin(adev->stolen_vga_memory); + amdgpu_bo_unreserve(adev->stolen_vga_memory); } - amdgpu_bo_unref(&adev->stollen_vga_memory); + amdgpu_bo_unref(&adev->stolen_vga_memory); } ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); @@ -1509,11 +1542,12 @@ error_free: } int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, + uint64_t src_data, struct reservation_object *resv, struct dma_fence **fence) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/ uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; @@ -1545,7 +1579,9 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, num_pages -= mm_node->size; ++mm_node; } - num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; + + /* 10 double words for each SDMA_OP_PTEPDE cmd */ + num_dw = num_loops * 10; /* for IB padding */ num_dw += 64; @@ -1570,12 +1606,16 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, uint32_t byte_count = mm_node->size << PAGE_SHIFT; uint64_t dst_addr; + WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8"); + dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem); while (byte_count) { uint32_t cur_size_in_bytes = min(byte_count, max_bytes); - amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, - dst_addr, cur_size_in_bytes); + amdgpu_vm_set_pte_pde(adev, &job->ibs[0], + dst_addr, 0, + cur_size_in_bytes >> 3, 0, + src_data); dst_addr += cur_size_in_bytes; byte_count -= cur_size_in_bytes; @@ -1601,32 +1641,16 @@ error_free: #if defined(CONFIG_DEBUG_FS) -extern void amdgpu_gtt_mgr_print(struct seq_file *m, struct ttm_mem_type_manager - *man); static int amdgpu_mm_dump_table(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; unsigned ttm_pl = *(int *)node->info_ent->data; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; - struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv; - struct ttm_bo_global *glob = adev->mman.bdev.glob; + struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl]; struct drm_printer p = drm_seq_file_printer(m); - spin_lock(&glob->lru_lock); - drm_mm_print(mm, &p); - spin_unlock(&glob->lru_lock); - switch (ttm_pl) { - case TTM_PL_VRAM: - seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", - adev->mman.bdev.man[ttm_pl].size, - (u64)atomic64_read(&adev->vram_usage) >> 20, - (u64)atomic64_read(&adev->vram_vis_usage) >> 20); - break; - case TTM_PL_TT: - amdgpu_gtt_mgr_print(m, &adev->mman.bdev.man[TTM_PL_TT]); - break; - } + man->func->debug(man, &p); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index f137c2458ee8..f22a4758719d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -66,6 +66,10 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, struct ttm_buffer_object *tbo, const struct ttm_place *place, struct ttm_mem_reg *mem); +uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man); + +uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); +uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man); int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, @@ -73,7 +77,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, struct dma_fence **fence, bool direct_submit, bool vm_needs_flush); int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, + uint64_t src_data, struct reservation_object *resv, struct dma_fence **fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index fcfb9d4f7477..36c763310df5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -358,8 +358,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, (le32_to_cpu(header->jt_offset) * 4); memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); - ucode->ucode_size += le32_to_cpu(header->jt_size) * 4; - return 0; } @@ -381,7 +379,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, bo); + NULL, NULL, 0, bo); if (err) { dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); goto failed; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 2ca09f111f08..e19928dae8e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -588,6 +588,10 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, } break; + case 8: /* MJPEG */ + min_dpb_size = 0; + break; + case 16: /* H265 */ image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; image_size = ALIGN(image_size, 256); @@ -1051,7 +1055,7 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &bo); + NULL, NULL, 0, &bo); if (r) return r; @@ -1101,7 +1105,7 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &bo); + NULL, NULL, 0, &bo); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index b692ad402252..c855366521ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -937,9 +937,9 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) unsigned i; int r, timeout = adev->usec_timeout; - /* workaround VCE ring test slow issue for sriov*/ + /* skip ring test for sriov*/ if (amdgpu_sriov_vf(adev)) - timeout *= 10; + return 0; r = amdgpu_ring_alloc(ring, 16); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 09190fadd228..041e0121590c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -209,9 +209,9 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) if (fences == 0) { if (adev->pm.dpm_enabled) { + /* might be used when with pg/cg amdgpu_dpm_enable_uvd(adev, false); - } else { - amdgpu_asic_set_uvd_clocks(adev, 0, 0); + */ } } else { schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); @@ -223,12 +223,10 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); - if (set_clocks) { - if (adev->pm.dpm_enabled) { - amdgpu_dpm_enable_uvd(adev, true); - } else { - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - } + if (set_clocks && adev->pm.dpm_enabled) { + /* might be used when with pg/cg + amdgpu_dpm_enable_uvd(adev, true); + */ } } @@ -361,7 +359,7 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &bo); + NULL, NULL, 0, &bo); if (r) return r; @@ -413,7 +411,7 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, &bo); + NULL, NULL, 0, &bo); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 8a081e162d13..ab05121b9272 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -46,14 +46,14 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev) * address within META_DATA init package to support SRIOV gfx preemption. */ -int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm) +int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_bo_va **bo_va) { - int r; - struct amdgpu_bo_va *bo_va; struct ww_acquire_ctx ticket; struct list_head list; struct amdgpu_bo_list_entry pd; struct ttm_validate_buffer csa_tv; + int r; INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&csa_tv.head); @@ -69,34 +69,33 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm) return r; } - bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); - if (!bo_va) { + *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); + if (!*bo_va) { ttm_eu_backoff_reservation(&ticket, &list); DRM_ERROR("failed to create bo_va for static CSA\n"); return -ENOMEM; } - r = amdgpu_vm_alloc_pts(adev, bo_va->vm, AMDGPU_CSA_VADDR, - AMDGPU_CSA_SIZE); + r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, AMDGPU_CSA_VADDR, + AMDGPU_CSA_SIZE); if (r) { DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r); - amdgpu_vm_bo_rmv(adev, bo_va); + amdgpu_vm_bo_rmv(adev, *bo_va); ttm_eu_backoff_reservation(&ticket, &list); return r; } - r = amdgpu_vm_bo_map(adev, bo_va, AMDGPU_CSA_VADDR, 0,AMDGPU_CSA_SIZE, - AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | - AMDGPU_PTE_EXECUTABLE); + r = amdgpu_vm_bo_map(adev, *bo_va, AMDGPU_CSA_VADDR, 0, AMDGPU_CSA_SIZE, + AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | + AMDGPU_PTE_EXECUTABLE); if (r) { DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r); - amdgpu_vm_bo_rmv(adev, bo_va); + amdgpu_vm_bo_rmv(adev, *bo_va); ttm_eu_backoff_reservation(&ticket, &list); return r; } - vm->csa_bo_va = bo_va; ttm_eu_backoff_reservation(&ticket, &list); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index e5b1baf387c1..afcfb8bcfb65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -90,7 +90,8 @@ static inline bool is_virtual_machine(void) struct amdgpu_vm; int amdgpu_allocate_static_csa(struct amdgpu_device *adev); -int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm); +int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_bo_va **bo_va); void amdgpu_virt_init_setting(struct amdgpu_device *adev); uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 250c8e80e646..6b1343e5541d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -159,11 +159,20 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, */ static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, int (*validate)(void *, struct amdgpu_bo *), - void *param, bool use_cpu_for_update) + void *param, bool use_cpu_for_update, + struct ttm_bo_global *glob) { unsigned i; int r; + if (parent->bo->shadow) { + struct amdgpu_bo *shadow = parent->bo->shadow; + + r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); + if (r) + return r; + } + if (use_cpu_for_update) { r = amdgpu_bo_kmap(parent->bo, NULL); if (r) @@ -183,12 +192,18 @@ static int amdgpu_vm_validate_level(struct amdgpu_vm_pt *parent, if (r) return r; + spin_lock(&glob->lru_lock); + ttm_bo_move_to_lru_tail(&entry->bo->tbo); + if (entry->bo->shadow) + ttm_bo_move_to_lru_tail(&entry->bo->shadow->tbo); + spin_unlock(&glob->lru_lock); + /* * Recurse into the sub directory. This is harmless because we * have only a maximum of 5 layers. */ r = amdgpu_vm_validate_level(entry, validate, param, - use_cpu_for_update); + use_cpu_for_update, glob); if (r) return r; } @@ -220,54 +235,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, return 0; return amdgpu_vm_validate_level(&vm->root, validate, param, - vm->use_cpu_for_update); + vm->use_cpu_for_update, + adev->mman.bdev.glob); } /** - * amdgpu_vm_move_level_in_lru - move one level of PT BOs to the LRU tail - * - * @adev: amdgpu device instance - * @vm: vm providing the BOs - * - * Move the PT BOs to the tail of the LRU. - */ -static void amdgpu_vm_move_level_in_lru(struct amdgpu_vm_pt *parent) -{ - unsigned i; - - if (!parent->entries) - return; - - for (i = 0; i <= parent->last_entry_used; ++i) { - struct amdgpu_vm_pt *entry = &parent->entries[i]; - - if (!entry->bo) - continue; - - ttm_bo_move_to_lru_tail(&entry->bo->tbo); - amdgpu_vm_move_level_in_lru(entry); - } -} - -/** - * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail - * - * @adev: amdgpu device instance - * @vm: vm providing the BOs - * - * Move the PT BOs to the tail of the LRU. - */ -void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, - struct amdgpu_vm *vm) -{ - struct ttm_bo_global *glob = adev->mman.bdev.glob; - - spin_lock(&glob->lru_lock); - amdgpu_vm_move_level_in_lru(&vm->root); - spin_unlock(&glob->lru_lock); -} - - /** * amdgpu_vm_alloc_levels - allocate the PD/PT levels * * @adev: amdgpu_device pointer @@ -288,6 +260,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, unsigned pt_idx, from, to; int r; u64 flags; + uint64_t init_value = 0; if (!parent->entries) { unsigned num_entries = amdgpu_vm_num_entries(adev, level); @@ -321,6 +294,12 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_SHADOW); + if (vm->pte_support_ats) { + init_value = AMDGPU_PTE_SYSTEM; + if (level != adev->vm_manager.num_level - 1) + init_value |= AMDGPU_PDE_PTE; + } + /* walk over the address space and allocate the page tables */ for (pt_idx = from; pt_idx <= to; ++pt_idx) { struct reservation_object *resv = vm->root.bo->tbo.resv; @@ -333,7 +312,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, AMDGPU_GPU_PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, flags, - NULL, resv, &pt); + NULL, resv, init_value, &pt); if (r) return r; @@ -352,7 +331,6 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, entry->bo = pt; entry->addr = 0; - entry->huge_page = false; } if (level < adev->vm_manager.num_level) { @@ -892,8 +870,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, { struct amdgpu_bo_va *bo_va; - list_for_each_entry(bo_va, &bo->va, bo_list) { - if (bo_va->vm == vm) { + list_for_each_entry(bo_va, &bo->va, base.bo_list) { + if (bo_va->base.vm == vm) { return bo_va; } } @@ -1060,18 +1038,13 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, shadow = parent->bo->shadow; if (vm->use_cpu_for_update) { - pd_addr = (unsigned long)parent->bo->kptr; + pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo); r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); if (unlikely(r)) return r; params.func = amdgpu_vm_cpu_set_ptes; } else { - if (shadow) { - r = amdgpu_ttm_bind(&shadow->tbo, &shadow->tbo.mem); - if (r) - return r; - } ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); @@ -1107,22 +1080,14 @@ static int amdgpu_vm_update_level(struct amdgpu_device *adev, if (bo == NULL) continue; - if (bo->shadow) { - struct amdgpu_bo *pt_shadow = bo->shadow; - - r = amdgpu_ttm_bind(&pt_shadow->tbo, - &pt_shadow->tbo.mem); - if (r) - return r; - } - pt = amdgpu_bo_gpu_offset(bo); pt = amdgpu_gart_get_vm_pde(adev, pt); - if (parent->entries[pt_idx].addr == pt || - parent->entries[pt_idx].huge_page) + /* Don't update huge pages here */ + if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) || + parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID)) continue; - parent->entries[pt_idx].addr = pt; + parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; pde = pd_addr + pt_idx * 8; if (((last_pde + 8 * count) != pde) || @@ -1300,15 +1265,14 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, * * Check if we can update the PD with a huge page. */ -static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, - struct amdgpu_vm_pt *entry, - struct amdgpu_vm_pt *parent, - unsigned nptes, uint64_t dst, - uint64_t flags) +static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, + struct amdgpu_vm_pt *entry, + struct amdgpu_vm_pt *parent, + unsigned nptes, uint64_t dst, + uint64_t flags) { bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); uint64_t pd_addr, pde; - int r; /* In the case of a mixed PT the PDE must point to it*/ if (p->adev->asic_type < CHIP_VEGA10 || @@ -1320,21 +1284,17 @@ static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, dst = amdgpu_gart_get_vm_pde(p->adev, dst); flags = AMDGPU_PTE_VALID; } else { + /* Set the huge page flag to stop scanning at this PDE */ flags |= AMDGPU_PDE_PTE; } - if (entry->addr == dst && - entry->huge_page == !!(flags & AMDGPU_PDE_PTE)) - return 0; + if (entry->addr == (dst | flags)) + return; - entry->addr = dst; - entry->huge_page = !!(flags & AMDGPU_PDE_PTE); + entry->addr = (dst | flags); if (use_cpu_update) { - r = amdgpu_bo_kmap(parent->bo, (void *)&pd_addr); - if (r) - return r; - + pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo); pde = pd_addr + (entry - parent->entries) * 8; amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); } else { @@ -1347,8 +1307,6 @@ static int amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, pde = pd_addr + (entry - parent->entries) * 8; amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); } - - return 0; } /** @@ -1375,7 +1333,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, struct amdgpu_bo *pt; unsigned nptes; bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); - int r; /* walk over the address space and update the page tables */ for (addr = start; addr < end; addr += nptes, @@ -1391,17 +1348,15 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, else nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); - r = amdgpu_vm_handle_huge_pages(params, entry, parent, - nptes, dst, flags); - if (r) - return r; - - if (entry->huge_page) + amdgpu_vm_handle_huge_pages(params, entry, parent, + nptes, dst, flags); + /* We don't need to update PTEs for huge pages */ + if (entry->addr & AMDGPU_PDE_PTE) continue; pt = entry->bo; if (use_cpu_update) { - pe_start = (unsigned long)pt->kptr; + pe_start = (unsigned long)amdgpu_bo_kptr(pt); } else { if (pt->shadow) { pe_start = amdgpu_bo_gpu_offset(pt->shadow); @@ -1455,9 +1410,7 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, * Userspace can support this by aligning virtual base address and * allocation size to the fragment size. */ - - /* SI and newer are optimized for 64KB */ - unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev); + unsigned pages_per_frag = params->adev->vm_manager.fragment_size; uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag); uint64_t frag_align = 1 << pages_per_frag; @@ -1771,7 +1724,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, bool clear) { - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo *bo = bo_va->base.bo; + struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_bo_va_mapping *mapping; dma_addr_t *pages_addr = NULL; uint64_t gtt_flags, flags; @@ -1780,27 +1734,27 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct dma_fence *exclusive; int r; - if (clear || !bo_va->bo) { + if (clear || !bo_va->base.bo) { mem = NULL; nodes = NULL; exclusive = NULL; } else { struct ttm_dma_tt *ttm; - mem = &bo_va->bo->tbo.mem; + mem = &bo_va->base.bo->tbo.mem; nodes = mem->mm_node; if (mem->mem_type == TTM_PL_TT) { - ttm = container_of(bo_va->bo->tbo.ttm, struct - ttm_dma_tt, ttm); + ttm = container_of(bo_va->base.bo->tbo.ttm, + struct ttm_dma_tt, ttm); pages_addr = ttm->dma_address; } - exclusive = reservation_object_get_excl(bo_va->bo->tbo.resv); + exclusive = reservation_object_get_excl(bo->tbo.resv); } - if (bo_va->bo) { - flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); - gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) && - adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ? + if (bo) { + flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); + gtt_flags = (amdgpu_ttm_is_bound(bo->tbo.ttm) && + adev == amdgpu_ttm_adev(bo->tbo.bdev)) ? flags : 0; } else { flags = 0x0; @@ -1808,7 +1762,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, } spin_lock(&vm->status_lock); - if (!list_empty(&bo_va->vm_status)) + if (!list_empty(&bo_va->base.vm_status)) list_splice_init(&bo_va->valids, &bo_va->invalids); spin_unlock(&vm->status_lock); @@ -1831,9 +1785,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, spin_lock(&vm->status_lock); list_splice_init(&bo_va->invalids, &bo_va->valids); - list_del_init(&bo_va->vm_status); + list_del_init(&bo_va->base.vm_status); if (clear) - list_add(&bo_va->vm_status, &vm->cleared); + list_add(&bo_va->base.vm_status, &vm->cleared); spin_unlock(&vm->status_lock); if (vm->use_cpu_for_update) { @@ -1995,15 +1949,19 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping; struct dma_fence *f = NULL; int r; + uint64_t init_pte_value = 0; while (!list_empty(&vm->freed)) { mapping = list_first_entry(&vm->freed, struct amdgpu_bo_va_mapping, list); list_del(&mapping->list); + if (vm->pte_support_ats) + init_pte_value = AMDGPU_PTE_SYSTEM; + r = amdgpu_vm_bo_update_mapping(adev, NULL, 0, NULL, vm, mapping->start, mapping->last, - 0, 0, &f); + init_pte_value, 0, &f); amdgpu_vm_free_mapping(adev, vm, mapping, f); if (r) { dma_fence_put(f); @@ -2023,26 +1981,26 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, } /** - * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT + * amdgpu_vm_clear_moved - clear moved BOs in the PT * * @adev: amdgpu_device pointer * @vm: requested vm * - * Make sure all invalidated BOs are cleared in the PT. + * Make sure all moved BOs are cleared in the PT. * Returns 0 for success. * * PTs have to be reserved and mutex must be locked! */ -int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, - struct amdgpu_vm *vm, struct amdgpu_sync *sync) +int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_sync *sync) { struct amdgpu_bo_va *bo_va = NULL; int r = 0; spin_lock(&vm->status_lock); - while (!list_empty(&vm->invalidated)) { - bo_va = list_first_entry(&vm->invalidated, - struct amdgpu_bo_va, vm_status); + while (!list_empty(&vm->moved)) { + bo_va = list_first_entry(&vm->moved, + struct amdgpu_bo_va, base.vm_status); spin_unlock(&vm->status_lock); r = amdgpu_vm_bo_update(adev, bo_va, true); @@ -2082,16 +2040,17 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, if (bo_va == NULL) { return NULL; } - bo_va->vm = vm; - bo_va->bo = bo; + bo_va->base.vm = vm; + bo_va->base.bo = bo; + INIT_LIST_HEAD(&bo_va->base.bo_list); + INIT_LIST_HEAD(&bo_va->base.vm_status); + bo_va->ref_count = 1; - INIT_LIST_HEAD(&bo_va->bo_list); INIT_LIST_HEAD(&bo_va->valids); INIT_LIST_HEAD(&bo_va->invalids); - INIT_LIST_HEAD(&bo_va->vm_status); if (bo) - list_add_tail(&bo_va->bo_list, &bo->va); + list_add_tail(&bo_va->base.bo_list, &bo->va); return bo_va; } @@ -2116,7 +2075,8 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, uint64_t size, uint64_t flags) { struct amdgpu_bo_va_mapping *mapping, *tmp; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo *bo = bo_va->base.bo; + struct amdgpu_vm *vm = bo_va->base.vm; uint64_t eaddr; /* validate the parameters */ @@ -2127,7 +2087,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, /* make sure object fit at this offset */ eaddr = saddr + size - 1; if (saddr >= eaddr || - (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) + (bo && offset + size > amdgpu_bo_size(bo))) return -EINVAL; saddr /= AMDGPU_GPU_PAGE_SIZE; @@ -2137,7 +2097,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, if (tmp) { /* bo and tmp overlap, invalid addr */ dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " - "0x%010Lx-0x%010Lx\n", bo_va->bo, saddr, eaddr, + "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, tmp->start, tmp->last + 1); return -EINVAL; } @@ -2182,7 +2142,8 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, uint64_t size, uint64_t flags) { struct amdgpu_bo_va_mapping *mapping; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_bo *bo = bo_va->base.bo; + struct amdgpu_vm *vm = bo_va->base.vm; uint64_t eaddr; int r; @@ -2194,7 +2155,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, /* make sure object fit at this offset */ eaddr = saddr + size - 1; if (saddr >= eaddr || - (bo_va->bo && offset + size > amdgpu_bo_size(bo_va->bo))) + (bo && offset + size > amdgpu_bo_size(bo))) return -EINVAL; /* Allocate all the needed memory */ @@ -2202,7 +2163,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, if (!mapping) return -ENOMEM; - r = amdgpu_vm_bo_clear_mappings(adev, bo_va->vm, saddr, size); + r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); if (r) { kfree(mapping); return r; @@ -2242,7 +2203,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, uint64_t saddr) { struct amdgpu_bo_va_mapping *mapping; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_vm *vm = bo_va->base.vm; bool valid = true; saddr /= AMDGPU_GPU_PAGE_SIZE; @@ -2390,12 +2351,12 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va) { struct amdgpu_bo_va_mapping *mapping, *next; - struct amdgpu_vm *vm = bo_va->vm; + struct amdgpu_vm *vm = bo_va->base.vm; - list_del(&bo_va->bo_list); + list_del(&bo_va->base.bo_list); spin_lock(&vm->status_lock); - list_del(&bo_va->vm_status); + list_del(&bo_va->base.vm_status); spin_unlock(&vm->status_lock); list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { @@ -2427,13 +2388,14 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, struct amdgpu_bo *bo) { - struct amdgpu_bo_va *bo_va; + struct amdgpu_vm_bo_base *bo_base; - list_for_each_entry(bo_va, &bo->va, bo_list) { - spin_lock(&bo_va->vm->status_lock); - if (list_empty(&bo_va->vm_status)) - list_add(&bo_va->vm_status, &bo_va->vm->invalidated); - spin_unlock(&bo_va->vm->status_lock); + list_for_each_entry(bo_base, &bo->va, bo_list) { + spin_lock(&bo_base->vm->status_lock); + if (list_empty(&bo_base->vm_status)) + list_add(&bo_base->vm_status, + &bo_base->vm->moved); + spin_unlock(&bo_base->vm->status_lock); } } @@ -2451,12 +2413,26 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) } /** - * amdgpu_vm_adjust_size - adjust vm size and block size + * amdgpu_vm_set_fragment_size - adjust fragment size in PTE + * + * @adev: amdgpu_device pointer + * @fragment_size_default: the default fragment size if it's set auto + */ +void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default) +{ + if (amdgpu_vm_fragment_size == -1) + adev->vm_manager.fragment_size = fragment_size_default; + else + adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; +} + +/** + * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size * * @adev: amdgpu_device pointer * @vm_size: the default vm size if it's set auto */ -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default) { /* adjust vm size firstly */ if (amdgpu_vm_size == -1) @@ -2471,8 +2447,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size) else adev->vm_manager.block_size = amdgpu_vm_block_size; - DRM_INFO("vm size is %llu GB, block size is %u-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size); + amdgpu_vm_set_fragment_size(adev, fragment_size_default); + + DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", + adev->vm_manager.vm_size, adev->vm_manager.block_size, + adev->vm_manager.fragment_size); } /** @@ -2494,13 +2473,14 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amd_sched_rq *rq; int r, i; u64 flags; + uint64_t init_pde_value = 0; vm->va = RB_ROOT; vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) vm->reserved_vmid[i] = NULL; spin_lock_init(&vm->status_lock); - INIT_LIST_HEAD(&vm->invalidated); + INIT_LIST_HEAD(&vm->moved); INIT_LIST_HEAD(&vm->cleared); INIT_LIST_HEAD(&vm->freed); @@ -2515,10 +2495,17 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (r) return r; - if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) + vm->pte_support_ats = false; + + if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_COMPUTE); - else + + if (adev->asic_type == CHIP_RAVEN) { + vm->pte_support_ats = true; + init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE; + } + } else vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_GFX); DRM_DEBUG_DRIVER("VM update mode is %s\n", @@ -2538,7 +2525,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, AMDGPU_GEM_DOMAIN_VRAM, flags, - NULL, NULL, &vm->root.bo); + NULL, NULL, init_pde_value, &vm->root.bo); if (r) goto error_free_sched_entity; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 34d9174ebff2..ba6691b58ee7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -50,11 +50,6 @@ struct amdgpu_bo_list_entry; /* PTBs (Page Table Blocks) need to be aligned to 32K */ #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 -/* LOG2 number of continuous pages for the fragment field */ -#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \ - ((adev)->asic_type < CHIP_VEGA10 ? 4 : \ - (adev)->vm_manager.block_size) - #define AMDGPU_PTE_VALID (1ULL << 0) #define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SNOOPED (1ULL << 2) @@ -99,11 +94,22 @@ struct amdgpu_bo_list_entry; #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) +/* base structure for tracking BO usage in a VM */ +struct amdgpu_vm_bo_base { + /* constant after initialization */ + struct amdgpu_vm *vm; + struct amdgpu_bo *bo; + + /* protected by bo being reserved */ + struct list_head bo_list; + + /* protected by spinlock */ + struct list_head vm_status; +}; struct amdgpu_vm_pt { struct amdgpu_bo *bo; uint64_t addr; - bool huge_page; /* array of page tables, one for each directory entry */ struct amdgpu_vm_pt *entries; @@ -118,7 +124,7 @@ struct amdgpu_vm { spinlock_t status_lock; /* BOs moved, but not yet updated in the PT */ - struct list_head invalidated; + struct list_head moved; /* BOs cleared in the PT because of a move */ struct list_head cleared; @@ -141,11 +147,12 @@ struct amdgpu_vm { u64 client_id; /* dedicated to vm */ struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; - /* each VM will map on CSA */ - struct amdgpu_bo_va *csa_bo_va; /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ bool use_cpu_for_update; + + /* Flag to indicate ATS support from PTE for GFX9 */ + bool pte_support_ats; }; struct amdgpu_vm_id { @@ -188,6 +195,7 @@ struct amdgpu_vm_manager { uint32_t num_level; uint64_t vm_size; uint32_t block_size; + uint32_t fragment_size; /* vram base address for page table entry */ u64 vram_base_offset; /* vm pte handling */ @@ -220,8 +228,6 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, int (*callback)(void *p, struct amdgpu_bo *bo), void *param); -void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, - struct amdgpu_vm *vm); int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t saddr, uint64_t size); @@ -237,8 +243,8 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence); -int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, - struct amdgpu_sync *sync); +int amdgpu_vm_clear_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct amdgpu_sync *sync); int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, bool clear); @@ -265,7 +271,10 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, uint64_t saddr, uint64_t size); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); +void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, + uint32_t fragment_size_default); +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, + uint32_t fragment_size_default); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index a2c59a08b2bd..26e900627971 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -28,6 +28,8 @@ struct amdgpu_vram_mgr { struct drm_mm mm; spinlock_t lock; + atomic64_t usage; + atomic64_t vis_usage; }; /** @@ -79,6 +81,27 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man) } /** + * amdgpu_vram_mgr_vis_size - Calculate visible node size + * + * @adev: amdgpu device structure + * @node: MM node structure + * + * Calculate how many bytes of the MM node are inside visible VRAM + */ +static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev, + struct drm_mm_node *node) +{ + uint64_t start = node->start << PAGE_SHIFT; + uint64_t end = (node->size + node->start) << PAGE_SHIFT; + + if (start >= adev->mc.visible_vram_size) + return 0; + + return (end > adev->mc.visible_vram_size ? + adev->mc.visible_vram_size : end) - start; +} + +/** * amdgpu_vram_mgr_new - allocate new ranges * * @man: TTM memory type manager @@ -93,11 +116,13 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, const struct ttm_place *place, struct ttm_mem_reg *mem) { + struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_vram_mgr *mgr = man->priv; struct drm_mm *mm = &mgr->mm; struct drm_mm_node *nodes; enum drm_mm_insert_mode mode; unsigned long lpfn, num_nodes, pages_per_node, pages_left; + uint64_t usage = 0, vis_usage = 0; unsigned i; int r; @@ -142,6 +167,9 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, if (unlikely(r)) goto error; + usage += nodes[i].size << PAGE_SHIFT; + vis_usage += amdgpu_vram_mgr_vis_size(adev, &nodes[i]); + /* Calculate a virtual BO start address to easily check if * everything is CPU accessible. */ @@ -155,6 +183,9 @@ static int amdgpu_vram_mgr_new(struct ttm_mem_type_manager *man, } spin_unlock(&mgr->lock); + atomic64_add(usage, &mgr->usage); + atomic64_add(vis_usage, &mgr->vis_usage); + mem->mm_node = nodes; return 0; @@ -181,8 +212,10 @@ error: static void amdgpu_vram_mgr_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { + struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_vram_mgr *mgr = man->priv; struct drm_mm_node *nodes = mem->mm_node; + uint64_t usage = 0, vis_usage = 0; unsigned pages = mem->num_pages; if (!mem->mm_node) @@ -192,31 +225,67 @@ static void amdgpu_vram_mgr_del(struct ttm_mem_type_manager *man, while (pages) { pages -= nodes->size; drm_mm_remove_node(nodes); + usage += nodes->size << PAGE_SHIFT; + vis_usage += amdgpu_vram_mgr_vis_size(adev, nodes); ++nodes; } spin_unlock(&mgr->lock); + atomic64_sub(usage, &mgr->usage); + atomic64_sub(vis_usage, &mgr->vis_usage); + kfree(mem->mm_node); mem->mm_node = NULL; } /** + * amdgpu_vram_mgr_usage - how many bytes are used in this domain + * + * @man: TTM memory type manager + * + * Returns how many bytes are used in this domain. + */ +uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + + return atomic64_read(&mgr->usage); +} + +/** + * amdgpu_vram_mgr_vis_usage - how many bytes are used in the visible part + * + * @man: TTM memory type manager + * + * Returns how many bytes are used in the visible part of VRAM + */ +uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man) +{ + struct amdgpu_vram_mgr *mgr = man->priv; + + return atomic64_read(&mgr->vis_usage); +} + +/** * amdgpu_vram_mgr_debug - dump VRAM table * * @man: TTM memory type manager - * @prefix: text prefix + * @printer: DRM printer to use * * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { struct amdgpu_vram_mgr *mgr = man->priv; - struct drm_printer p = drm_debug_printer(prefix); spin_lock(&mgr->lock); - drm_mm_print(&mgr->mm, &p); + drm_mm_print(&mgr->mm, printer); spin_unlock(&mgr->lock); + + drm_printf(printer, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", + man->size, amdgpu_vram_mgr_usage(man) >> 20, + amdgpu_vram_mgr_vis_usage(man) >> 20); } const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func = { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 490e84944851..4e519dc42916 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2431,7 +2431,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, aobj = gem_to_amdgpu_bo(obj); ret = amdgpu_bo_reserve(aobj, false); if (ret != 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2439,7 +2439,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, amdgpu_bo_unreserve(aobj); if (ret) { DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2473,7 +2473,7 @@ unpin: amdgpu_bo_unpin(aobj); amdgpu_bo_unreserve(aobj); } - drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 921c6f772f11..11edc75edaa9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2506,7 +2506,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, aobj = gem_to_amdgpu_bo(obj); ret = amdgpu_bo_reserve(aobj, false); if (ret != 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2514,7 +2514,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, amdgpu_bo_unreserve(aobj); if (ret) { DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2548,7 +2548,7 @@ unpin: amdgpu_bo_unpin(aobj); amdgpu_bo_unreserve(aobj); } - drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index bcd9521237f4..a51e35f824a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -42,6 +42,7 @@ #include "dce/dce_6_0_d.h" #include "dce/dce_6_0_sh_mask.h" #include "gca/gfx_7_2_enum.h" +#include "dce_v6_0.h" #include "si_enums.h" static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); @@ -2321,7 +2322,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, aobj = gem_to_amdgpu_bo(obj); ret = amdgpu_bo_reserve(aobj, false); if (ret != 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2329,7 +2330,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, amdgpu_bo_unreserve(aobj); if (ret) { DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2363,7 +2364,7 @@ unpin: amdgpu_bo_unpin(aobj); amdgpu_bo_unreserve(aobj); } - drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 609438fe8584..9cf14b8b2db9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2335,7 +2335,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, aobj = gem_to_amdgpu_bo(obj); ret = amdgpu_bo_reserve(aobj, false); if (ret != 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2343,7 +2343,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, amdgpu_bo_unreserve(aobj); if (ret) { DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -2377,7 +2377,7 @@ unpin: amdgpu_bo_unpin(aobj); amdgpu_bo_unreserve(aobj); } - drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); + drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index 5ed919e45351..b9ee9073cb0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -479,6 +479,8 @@ static int dce_virtual_hw_init(void *handle) #endif /* no DCE */ break; + case CHIP_VEGA10: + break; default: DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 4ac85f47f287..d228f5a99044 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2217,40 +2217,9 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev) { - int r; - - if (adev->gfx.rlc.save_restore_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); - - amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); - adev->gfx.rlc.save_restore_obj = NULL; - } - - if (adev->gfx.rlc.clear_state_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - - amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); - adev->gfx.rlc.clear_state_obj = NULL; - } - - if (adev->gfx.rlc.cp_table_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); - - amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); - adev->gfx.rlc.cp_table_obj = NULL; - } + amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); } static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) @@ -2273,43 +2242,23 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) if (src_ptr) { /* save restore block */ - if (adev->gfx.rlc.save_restore_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - NULL, NULL, - &adev->gfx.rlc.save_restore_obj); - - if (r) { - dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); - if (unlikely(r != 0)) { - gfx_v6_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.save_restore_gpu_addr); + r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.save_restore_obj, + &adev->gfx.rlc.save_restore_gpu_addr, + (void **)&adev->gfx.rlc.sr_ptr); if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); - dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); + dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", + r); gfx_v6_0_rlc_fini(adev); return r; } - r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); - if (r) { - dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); - gfx_v6_0_rlc_fini(adev); - return r; - } /* write the sr buffer */ dst_ptr = adev->gfx.rlc.sr_ptr; for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) dst_ptr[i] = cpu_to_le32(src_ptr[i]); + amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); } @@ -2319,39 +2268,17 @@ static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); dws = adev->gfx.rlc.clear_state_size + (256 / 4); - if (adev->gfx.rlc.clear_state_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - NULL, NULL, - &adev->gfx.rlc.clear_state_obj); - - if (r) { - dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); - gfx_v6_0_rlc_fini(adev); - return r; - } - } - r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); - if (unlikely(r != 0)) { - gfx_v6_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.clear_state_gpu_addr); + r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); gfx_v6_0_rlc_fini(adev); return r; } - r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); - if (r) { - dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); - gfx_v6_0_rlc_fini(adev); - return r; - } /* set up the cs buffer */ dst_ptr = adev->gfx.rlc.cs_ptr; reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 17b7c6934b0a..00868764a0dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -1823,7 +1823,7 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) } /** - * gmc_v7_0_init_compute_vmid - gart enable + * gfx_v7_0_init_compute_vmid - gart enable * * @adev: amdgpu_device pointer * @@ -1833,7 +1833,7 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) #define DEFAULT_SH_MEM_BASES (0x6000) #define FIRST_COMPUTE_VMID (8) #define LAST_COMPUTE_VMID (16) -static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) +static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) { int i; uint32_t sh_mem_config; @@ -1921,6 +1921,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) ELEMENT_SIZE, 1); sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, INDEX_STRIDE, 3); + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); mutex_lock(&adev->srbm_mutex); for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { @@ -1934,12 +1935,11 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); WREG32(mmSH_MEM_BASES, sh_mem_base); - WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); } cik_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - gmc_v7_0_init_compute_vmid(adev); + gfx_v7_0_init_compute_vmid(adev); WREG32(mmSX_DEBUG_1, 0x20); @@ -2774,39 +2774,18 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) */ static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) { - int i, r; + int i; for (i = 0; i < adev->gfx.num_compute_rings; i++) { struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; - if (ring->mqd_obj) { - r = amdgpu_bo_reserve(ring->mqd_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); - - amdgpu_bo_unpin(ring->mqd_obj); - amdgpu_bo_unreserve(ring->mqd_obj); - - amdgpu_bo_unref(&ring->mqd_obj); - ring->mqd_obj = NULL; - } + amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); } } static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) { - int r; - - if (adev->gfx.mec.hpd_eop_obj) { - r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); - amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); - - amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); - adev->gfx.mec.hpd_eop_obj = NULL; - } + amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); } static int gfx_v7_0_mec_init(struct amdgpu_device *adev) @@ -2823,33 +2802,14 @@ static int gfx_v7_0_mec_init(struct amdgpu_device *adev) /* allocate space for ALL pipes (even the ones we don't own) */ mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * GFX7_MEC_HPD_SIZE * 2; - if (adev->gfx.mec.hpd_eop_obj == NULL) { - r = amdgpu_bo_create(adev, - mec_hpd_size, - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &adev->gfx.mec.hpd_eop_obj); - if (r) { - dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); - return r; - } - } - r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); - if (unlikely(r != 0)) { - gfx_v7_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, - &adev->gfx.mec.hpd_eop_gpu_addr); - if (r) { - dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); - gfx_v7_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); + r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_obj, + &adev->gfx.mec.hpd_eop_gpu_addr, + (void **)&hpd); if (r) { - dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); + dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); gfx_v7_0_mec_fini(adev); return r; } @@ -3108,32 +3068,12 @@ static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) struct cik_mqd *mqd; struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; - if (ring->mqd_obj == NULL) { - r = amdgpu_bo_create(adev, - sizeof(struct cik_mqd), - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &ring->mqd_obj); - if (r) { - dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(ring->mqd_obj, false); - if (unlikely(r != 0)) - goto out; - - r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, - &mqd_gpu_addr); - if (r) { - dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); - goto out_unreserve; - } - r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&mqd); + r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &mqd_gpu_addr, (void **)&mqd); if (r) { - dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); - goto out_unreserve; + dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); + return r; } mutex_lock(&adev->srbm_mutex); @@ -3147,9 +3087,7 @@ static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) mutex_unlock(&adev->srbm_mutex); amdgpu_bo_kunmap(ring->mqd_obj); -out_unreserve: amdgpu_bo_unreserve(ring->mqd_obj); -out: return 0; } @@ -3361,43 +3299,9 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, */ static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) { - int r; - - /* save restore block */ - if (adev->gfx.rlc.save_restore_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); - - amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); - adev->gfx.rlc.save_restore_obj = NULL; - } - - /* clear state block */ - if (adev->gfx.rlc.clear_state_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - - amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); - adev->gfx.rlc.clear_state_obj = NULL; - } - - /* clear state block */ - if (adev->gfx.rlc.cp_table_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); - - amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); - adev->gfx.rlc.cp_table_obj = NULL; - } + amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); } static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) @@ -3432,39 +3336,17 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) if (src_ptr) { /* save restore block */ - if (adev->gfx.rlc.save_restore_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, - &adev->gfx.rlc.save_restore_obj); - if (r) { - dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); - if (unlikely(r != 0)) { - gfx_v7_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.save_restore_gpu_addr); + r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.save_restore_obj, + &adev->gfx.rlc.save_restore_gpu_addr, + (void **)&adev->gfx.rlc.sr_ptr); if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); - dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); + dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r); gfx_v7_0_rlc_fini(adev); return r; } - r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); - if (r) { - dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); - gfx_v7_0_rlc_fini(adev); - return r; - } /* write the sr buffer */ dst_ptr = adev->gfx.rlc.sr_ptr; for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) @@ -3477,39 +3359,17 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) /* clear state block */ adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); - if (adev->gfx.rlc.clear_state_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, - &adev->gfx.rlc.clear_state_obj); - if (r) { - dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); - gfx_v7_0_rlc_fini(adev); - return r; - } - } - r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); - if (unlikely(r != 0)) { - gfx_v7_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.clear_state_gpu_addr); + r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); gfx_v7_0_rlc_fini(adev); return r; } - r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); - if (r) { - dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); - gfx_v7_0_rlc_fini(adev); - return r; - } /* set up the cs buffer */ dst_ptr = adev->gfx.rlc.cs_ptr; gfx_v7_0_get_csb_buffer(adev, dst_ptr); @@ -3518,37 +3378,14 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) } if (adev->gfx.rlc.cp_table_size) { - if (adev->gfx.rlc.cp_table_obj == NULL) { - r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, - &adev->gfx.rlc.cp_table_obj); - if (r) { - dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); - gfx_v7_0_rlc_fini(adev); - return r; - } - } - r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); - if (unlikely(r != 0)) { - dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); - gfx_v7_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.cp_table_gpu_addr); - if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); - dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); - gfx_v7_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); + r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); if (r) { - dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); + dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); gfx_v7_0_rlc_fini(adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 05436b8730b4..832e592fcd07 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1238,29 +1238,8 @@ static void cz_init_cp_jump_table(struct amdgpu_device *adev) static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) { - int r; - - /* clear state block */ - if (adev->gfx.rlc.clear_state_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC cbs bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); - adev->gfx.rlc.clear_state_obj = NULL; - } - - /* jump table block */ - if (adev->gfx.rlc.cp_table_obj) { - r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); - amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); - amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); - adev->gfx.rlc.cp_table_obj = NULL; - } + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); } static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) @@ -1278,39 +1257,17 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) /* clear state block */ adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); - if (adev->gfx.rlc.clear_state_obj == NULL) { - r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, - &adev->gfx.rlc.clear_state_obj); - if (r) { - dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); - gfx_v8_0_rlc_fini(adev); - return r; - } - } - r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); - if (unlikely(r != 0)) { - gfx_v8_0_rlc_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.clear_state_gpu_addr); + r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); - dev_warn(adev->dev, "(%d) pin RLC cbs bo failed\n", r); + dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); gfx_v8_0_rlc_fini(adev); return r; } - r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); - if (r) { - dev_warn(adev->dev, "(%d) map RLC cbs bo failed\n", r); - gfx_v8_0_rlc_fini(adev); - return r; - } /* set up the cs buffer */ dst_ptr = adev->gfx.rlc.cs_ptr; gfx_v8_0_get_csb_buffer(adev, dst_ptr); @@ -1321,34 +1278,13 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) if ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY)) { adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ - if (adev->gfx.rlc.cp_table_obj == NULL) { - r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, - &adev->gfx.rlc.cp_table_obj); - if (r) { - dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); - if (unlikely(r != 0)) { - dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); - return r; - } - r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.cp_table_gpu_addr); - if (r) { - amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); - dev_warn(adev->dev, "(%d) pin RLC cp table bo failed\n", r); - return r; - } - r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); + r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); if (r) { - dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); + dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); return r; } @@ -1363,17 +1299,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) { - int r; - - if (adev->gfx.mec.hpd_eop_obj) { - r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); - amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); - amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); - adev->gfx.mec.hpd_eop_obj = NULL; - } + amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); } static int gfx_v8_0_mec_init(struct amdgpu_device *adev) @@ -1389,34 +1315,13 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; - if (adev->gfx.mec.hpd_eop_obj == NULL) { - r = amdgpu_bo_create(adev, - mec_hpd_size, - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &adev->gfx.mec.hpd_eop_obj); - if (r) { - dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); - if (unlikely(r != 0)) { - gfx_v8_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, - &adev->gfx.mec.hpd_eop_gpu_addr); + r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_obj, + &adev->gfx.mec.hpd_eop_gpu_addr, + (void **)&hpd); if (r) { - dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); - gfx_v8_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); - if (r) { - dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); - gfx_v8_0_mec_fini(adev); + dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); return r; } @@ -3802,6 +3707,8 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) ELEMENT_SIZE, 1); sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, INDEX_STRIDE, 3); + WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); + mutex_lock(&adev->srbm_mutex); for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { vi_srbm_select(adev, 0, 0, 0, i); @@ -3825,7 +3732,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) WREG32(mmSH_MEM_APE1_BASE, 1); WREG32(mmSH_MEM_APE1_LIMIT, 0); - WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); } vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 435db6f5efcf..69182eeca264 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -116,7 +116,9 @@ static const u32 golden_settings_gc_9_0[] = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, + SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000, SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107, + SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000, SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, @@ -772,18 +774,16 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) if (cs_data) { /* clear state block */ adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); - if (adev->gfx.rlc.clear_state_obj == NULL) { - r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.clear_state_obj, - &adev->gfx.rlc.clear_state_gpu_addr, - (void **)&adev->gfx.rlc.cs_ptr); - if (r) { - dev_err(adev->dev, - "(%d) failed to create rlc csb bo\n", r); - gfx_v9_0_rlc_fini(adev); - return r; - } + r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + if (r) { + dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", + r); + gfx_v9_0_rlc_fini(adev); + return r; } /* set up the cs buffer */ dst_ptr = adev->gfx.rlc.cs_ptr; @@ -795,18 +795,16 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) if (adev->asic_type == CHIP_RAVEN) { /* TODO: double check the cp_table_size for RV */ adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ - if (adev->gfx.rlc.cp_table_obj == NULL) { - r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size, - PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, - &adev->gfx.rlc.cp_table_obj, - &adev->gfx.rlc.cp_table_gpu_addr, - (void **)&adev->gfx.rlc.cp_table_ptr); - if (r) { - dev_err(adev->dev, - "(%d) failed to create cp table bo\n", r); - gfx_v9_0_rlc_fini(adev); - return r; - } + r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); + if (r) { + dev_err(adev->dev, + "(%d) failed to create cp table bo\n", r); + gfx_v9_0_rlc_fini(adev); + return r; } rv_init_cp_jump_table(adev); @@ -821,28 +819,8 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) { - int r; - - if (adev->gfx.mec.hpd_eop_obj) { - r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); - amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); - - amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); - adev->gfx.mec.hpd_eop_obj = NULL; - } - if (adev->gfx.mec.mec_fw_obj) { - r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true); - if (unlikely(r != 0)) - dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r); - amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj); - amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); - - amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj); - adev->gfx.mec.mec_fw_obj = NULL; - } + amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); } static int gfx_v9_0_mec_init(struct amdgpu_device *adev) @@ -862,33 +840,13 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) amdgpu_gfx_compute_queue_acquire(adev); mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; - if (adev->gfx.mec.hpd_eop_obj == NULL) { - r = amdgpu_bo_create(adev, - mec_hpd_size, - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &adev->gfx.mec.hpd_eop_obj); - if (r) { - dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); - if (unlikely(r != 0)) { - gfx_v9_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, - &adev->gfx.mec.hpd_eop_gpu_addr); + r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_obj, + &adev->gfx.mec.hpd_eop_gpu_addr, + (void **)&hpd); if (r) { - dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); - gfx_v9_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); - if (r) { - dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); + dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); gfx_v9_0_mec_fini(adev); return r; } @@ -905,42 +863,22 @@ static int gfx_v9_0_mec_init(struct amdgpu_device *adev) le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; - if (adev->gfx.mec.mec_fw_obj == NULL) { - r = amdgpu_bo_create(adev, - mec_hdr->header.ucode_size_bytes, - PAGE_SIZE, true, - AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, - &adev->gfx.mec.mec_fw_obj); - if (r) { - dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); - return r; - } - } - - r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false); - if (unlikely(r != 0)) { - gfx_v9_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT, - &adev->gfx.mec.mec_fw_gpu_addr); - if (r) { - dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r); - gfx_v9_0_mec_fini(adev); - return r; - } - r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw); + r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.mec_fw_obj, + &adev->gfx.mec.mec_fw_gpu_addr, + (void **)&fw); if (r) { - dev_warn(adev->dev, "(%d) map firmware bo failed\n", r); + dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); gfx_v9_0_mec_fini(adev); return r; } + memcpy(fw, fw_data, fw_size); amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); - return 0; } @@ -2219,7 +2157,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; const struct cs_section_def *sect = NULL; const struct cs_extent_def *ext = NULL; - int r, i; + int r, i, tmp; /* init the CP */ WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); @@ -2227,7 +2165,7 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_enable(adev, true); - r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4); + r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); if (r) { DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); return r; @@ -2265,6 +2203,12 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, 0x8000); amdgpu_ring_write(ring, 0x8000); + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); + tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | + (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); + amdgpu_ring_write(ring, tmp); + amdgpu_ring_write(ring, 0); + amdgpu_ring_commit(ring); return 0; @@ -4158,7 +4102,7 @@ static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, return 0; } -const struct amd_ip_funcs gfx_v9_0_ip_funcs = { +static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { .name = "gfx_v9_0", .early_init = gfx_v9_0_early_init, .late_init = gfx_v9_0_late_init, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h index 56ef652a575d..fa5a3fbaf6ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h @@ -24,7 +24,6 @@ #ifndef __GFX_V9_0_H__ #define __GFX_V9_0_H__ -extern const struct amd_ip_funcs gfx_v9_0_ip_funcs; extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block; void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index 408723ef157c..4f2788b61a08 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) { - uint32_t tmp; + uint32_t tmp, field; /* Setup L2 cache */ tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); @@ -143,9 +143,10 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); + field = adev->vm_manager.fragment_size; tmp = mmVM_L2_CNTL3_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h index d2dbb085f480..206e29cad753 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h @@ -30,7 +30,5 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value); void gfxhub_v1_0_init(struct amdgpu_device *adev); u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev); -extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs; -extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 93c45f26b7c8..12b0c4cd7a5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -461,6 +461,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) { int r, i; + u32 field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); @@ -488,10 +489,12 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) WREG32(mmVM_L2_CNTL2, VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); + + field = adev->vm_manager.fragment_size; WREG32(mmVM_L2_CNTL3, VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | - (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) | - (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); + (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | + (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); @@ -811,7 +814,7 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - amdgpu_vm_adjust_size(adev, 64); + amdgpu_vm_adjust_size(adev, 64, 4); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; adev->mc.mc_mask = 0xffffffffffULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 4a9e84062874..e42c1ad3af5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -562,7 +562,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) { int r, i; - u32 tmp; + u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); @@ -592,10 +592,12 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32(mmVM_L2_CNTL2, tmp); + + field = adev->vm_manager.fragment_size; tmp = RREG32(mmVM_L2_CNTL3); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); WREG32(mmVM_L2_CNTL3, tmp); /* setup context0 */ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); @@ -948,7 +950,7 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64); + amdgpu_vm_adjust_size(adev, 64, 4); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; /* Set the internal MC address mask diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 85c937b5e40b..7ca2dae8237a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -762,7 +762,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) { int r, i; - u32 tmp; + u32 tmp, field; if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); @@ -793,10 +793,12 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32(mmVM_L2_CNTL2, tmp); + + field = adev->vm_manager.fragment_size; tmp = RREG32(mmVM_L2_CNTL3); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); WREG32(mmVM_L2_CNTL3, tmp); /* XXX: set to enable PTE/PDE in system memory */ tmp = RREG32(mmVM_L2_CNTL4); @@ -1046,7 +1048,7 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64); + amdgpu_vm_adjust_size(adev, 64, 4); adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; /* Set the internal MC address mask diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index c22899a08106..2769c2b3b56e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -541,9 +541,10 @@ static int gmc_v9_0_sw_init(void *handle) adev->vm_manager.vm_size = 1U << 18; adev->vm_manager.block_size = 9; adev->vm_manager.num_level = 3; + amdgpu_vm_set_fragment_size(adev, 9); } else { - /* vm_size is 64GB for legacy 2-level page support*/ - amdgpu_vm_adjust_size(adev, 64); + /* vm_size is 64GB for legacy 2-level page support */ + amdgpu_vm_adjust_size(adev, 64, 9); adev->vm_manager.num_level = 1; } break; @@ -558,14 +559,16 @@ static int gmc_v9_0_sw_init(void *handle) adev->vm_manager.vm_size = 1U << 18; adev->vm_manager.block_size = 9; adev->vm_manager.num_level = 3; + amdgpu_vm_set_fragment_size(adev, 9); break; default: break; } - DRM_INFO("vm size is %llu GB, block size is %u-bit\n", + DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n", adev->vm_manager.vm_size, - adev->vm_manager.block_size); + adev->vm_manager.block_size, + adev->vm_manager.fragment_size); /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index ad8def3cc343..4395a4f12149 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -138,7 +138,7 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) { - uint32_t tmp; + uint32_t tmp, field; /* Setup L2 cache */ tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); @@ -157,9 +157,10 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); + field = adev->vm_manager.fragment_size; tmp = mmVM_L2_CNTL3_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6); WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); tmp = mmVM_L2_CNTL4_DEFAULT; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h index 57bb940c0ecd..5d38229baf69 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h @@ -36,7 +36,4 @@ void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev); void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, bool enable); -extern const struct amd_ip_funcs mmhub_v1_0_ip_funcs; -extern const struct amdgpu_ip_block_version mmhub_v1_0_ip_block; - #endif diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 591f3e7fb508..fd7c72aaafa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -291,6 +291,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) DRM_DEBUG("Setting write pointer\n"); if (ring->use_doorbell) { + u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; + DRM_DEBUG("Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr) << 2 == 0x%08x " @@ -299,8 +301,7 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) lower_32_bits(ring->wptr << 2), upper_32_bits(ring->wptr << 2)); /* XXX check if swapping is necessary on BE */ - adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); - adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); + WRITE_ONCE(*wb, (ring->wptr << 2)); DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", ring->doorbell_index, ring->wptr << 2); WDOORBELL64(ring->doorbell_index, ring->wptr << 2); @@ -573,12 +574,13 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) { struct amdgpu_ring *ring; - u32 rb_cntl, ib_cntl; + u32 rb_cntl, ib_cntl, wptr_poll_cntl; u32 rb_bufsz; u32 wb_offset; u32 doorbell; u32 doorbell_offset; u32 temp; + u64 wptr_gpu_addr; int i, r; for (i = 0; i < adev->sdma.num_instances; i++) { @@ -660,6 +662,19 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp); } + /* setup the wptr shadow polling */ + wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); + if (amdgpu_sriov_vf(adev)) + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); + else + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); + WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); + /* enable DMA RB */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); @@ -687,6 +702,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) if (adev->mman.buffer_funcs_ring == ring) amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); + } return 0; @@ -783,15 +799,12 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) const struct sdma_firmware_header_v1_0 *hdr; const __le32 *fw_data; u32 fw_size; - u32 digest_size = 0; int i, j; /* halt the MEs */ sdma_v4_0_enable(adev, false); for (i = 0; i < adev->sdma.num_instances; i++) { - uint16_t version_major; - uint16_t version_minor; if (!adev->sdma.instance[i].fw) return -EINVAL; @@ -799,23 +812,12 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) amdgpu_ucode_print_sdma_hdr(&hdr->header); fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; - version_major = le16_to_cpu(hdr->header.header_version_major); - version_minor = le16_to_cpu(hdr->header.header_version_minor); - - if (version_major == 1 && version_minor >= 1) { - const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = (const struct sdma_firmware_header_v1_1 *) hdr; - digest_size = le32_to_cpu(sdma_v1_1_hdr->digest_size); - } - - fw_size -= digest_size; - fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0); - for (j = 0; j < fw_size; j++) WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index e79befd80eed..7f408f85fdb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -250,6 +250,7 @@ #define PACKET3_SET_UCONFIG_REG 0x79 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28) #define PACKET3_SCRATCH_RAM_WRITE 0x7D #define PACKET3_SCRATCH_RAM_READ 0x7E #define PACKET3_LOAD_CONST_RAM 0x80 diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 987b958368ac..23a85750edd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -165,6 +165,9 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) unsigned i; int r; + if (amdgpu_sriov_vf(adev)) + return 0; + r = amdgpu_ring_alloc(ring, 16); if (r) { DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n", @@ -432,13 +435,19 @@ static int uvd_v7_0_sw_init(void *handle) return r; } - for (i = 0; i < adev->uvd.num_enc_rings; ++i) { ring = &adev->uvd.ring_enc[i]; sprintf(ring->name, "uvd_enc%d", i); if (amdgpu_sriov_vf(adev)) { ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; + + /* currently only use the first enconding ring for + * sriov, so set unused location for other unused rings. + */ + if (i == 0) + ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2; + else + ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1; } r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); if (r) @@ -685,6 +694,11 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, /* 4, set resp to zero */ WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); + WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0); + adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0; + adev->uvd.ring_enc[0].wptr = 0; + adev->uvd.ring_enc[0].wptr_old = 0; + /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); @@ -702,7 +716,6 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); return -EBUSY; } - WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0); return 0; } @@ -736,11 +749,9 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) init_table += header->uvd_table_offset; ring = &adev->uvd.ring; + ring->wptr = 0; size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); - /* disable clock gating */ - MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), - ~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0); MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0xFFFFFFFF, 0x00000004); /* mc resume*/ @@ -777,12 +788,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_ADDR_CONFIG), - adev->gfx.config.gb_addr_config); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG), - adev->gfx.config.gb_addr_config); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG), - adev->gfx.config.gb_addr_config); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); /* mc resume end*/ @@ -819,17 +824,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) UVD_LMI_CTRL__REQ_MODE_MASK | 0x00100000L)); - /* disable byte swapping */ - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_SWAP_CNTL), 0); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MP_SWAP_CNTL), 0); - - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA0), 0x40c2040); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXA1), 0x0); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB0), 0x40c2040); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUXB1), 0x0); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_ALU), 0); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MPC_SET_MUX), 0x88); - /* take all subblocks out of reset, except VCPU */ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); @@ -838,15 +832,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), UVD_VCPU_CNTL__CLK_EN_MASK); - /* enable UMC */ - MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), - ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); - - /* boot up the VCPU */ - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0); - - MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02); - /* enable master interrupt */ MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), @@ -859,40 +844,31 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) /* force RBC into idle state */ size = order_base_2(ring->ring_size); tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); - tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp); - /* set the write pointer delay */ - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL), 0); - - /* set the wb address */ - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR), - (upper_32_bits(ring->gpu_addr) >> 2)); - - /* programm the RB_BASE for ring buffer */ - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), - lower_32_bits(ring->gpu_addr)); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), - upper_32_bits(ring->gpu_addr)); - - ring->wptr = 0; ring = &adev->uvd.ring_enc[0]; + ring->wptr = 0; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4); + /* boot up the VCPU */ + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0); + + /* enable UMC */ + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); + + MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02); + /* add end packet */ memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; header->uvd_table_size = table_size; - return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); } - return -EINVAL; /* already initializaed ? */ + return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 1ecd6bb90c1f..11134d5f7443 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -173,6 +173,11 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev, /* 4, set resp to zero */ WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0); + WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); + adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; + adev->vce.ring[0].wptr = 0; + adev->vce.ring[0].wptr_old = 0; + /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001); @@ -190,7 +195,6 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev, dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); return -EBUSY; } - WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); return 0; } @@ -274,7 +278,8 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), - 0xffffffff, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK, + VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); /* end of MC_RESUME */ MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), @@ -296,11 +301,9 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; header->vce_table_size = table_size; - - return vce_v4_0_mmsch_start(adev, &adev->virt.mm_table); } - return -EINVAL; /* already initializaed ? */ + return vce_v4_0_mmsch_start(adev, &adev->virt.mm_table); } /** @@ -443,12 +446,14 @@ static int vce_v4_0_sw_init(void *handle) if (amdgpu_sriov_vf(adev)) { /* DOORBELL only works under SRIOV */ ring->use_doorbell = true; + + /* currently only use the first encoding ring for sriov, + * so set unused location for other unused rings. + */ if (i == 0) - ring->doorbell_index = AMDGPU_DOORBELL64_RING0_1 * 2; - else if (i == 1) - ring->doorbell_index = AMDGPU_DOORBELL64_RING2_3 * 2; + ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING0_1 * 2; else - ring->doorbell_index = AMDGPU_DOORBELL64_RING2_3 * 2 + 1; + ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1; } r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); if (r) @@ -990,11 +995,13 @@ static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev, { uint32_t val = 0; - if (state == AMDGPU_IRQ_STATE_ENABLE) - val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; + if (!amdgpu_sriov_vf(adev)) { + if (state == AMDGPU_IRQ_STATE_ENABLE) + val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; - WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val, - ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val, + ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 6cac291c96da..9ff69b90df36 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1028,8 +1028,7 @@ static int vi_common_early_init(void *handle) /* rev0 hardware requires workarounds to support PG */ adev->pg_flags = 0; if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { - adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | - AMD_PG_SUPPORT_GFX_SMG | + adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | AMD_PG_SUPPORT_GFX_PIPELINE | AMD_PG_SUPPORT_CP | AMD_PG_SUPPORT_UVD | diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6316aad43a73..e4a8c2e52cb2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -142,12 +142,12 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, struct kfd_ioctl_create_queue_args *args) { if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { - pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); + pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; } if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { - pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); + pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); return -EINVAL; } @@ -155,26 +155,26 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, (!access_ok(VERIFY_WRITE, (const void __user *) args->ring_base_address, sizeof(uint64_t)))) { - pr_err("kfd: can't access ring base address\n"); + pr_err("Can't access ring base address\n"); return -EFAULT; } if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { - pr_err("kfd: ring size must be a power of 2 or 0\n"); + pr_err("Ring size must be a power of 2 or 0\n"); return -EINVAL; } if (!access_ok(VERIFY_WRITE, (const void __user *) args->read_pointer_address, sizeof(uint32_t))) { - pr_err("kfd: can't access read pointer\n"); + pr_err("Can't access read pointer\n"); return -EFAULT; } if (!access_ok(VERIFY_WRITE, (const void __user *) args->write_pointer_address, sizeof(uint32_t))) { - pr_err("kfd: can't access write pointer\n"); + pr_err("Can't access write pointer\n"); return -EFAULT; } @@ -182,7 +182,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, !access_ok(VERIFY_WRITE, (const void __user *) args->eop_buffer_address, sizeof(uint32_t))) { - pr_debug("kfd: can't access eop buffer"); + pr_debug("Can't access eop buffer"); return -EFAULT; } @@ -190,7 +190,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, !access_ok(VERIFY_WRITE, (const void __user *) args->ctx_save_restore_address, sizeof(uint32_t))) { - pr_debug("kfd: can't access ctx save restore buffer"); + pr_debug("Can't access ctx save restore buffer"); return -EFAULT; } @@ -219,27 +219,27 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, else q_properties->format = KFD_QUEUE_FORMAT_PM4; - pr_debug("Queue Percentage (%d, %d)\n", + pr_debug("Queue Percentage: %d, %d\n", q_properties->queue_percent, args->queue_percentage); - pr_debug("Queue Priority (%d, %d)\n", + pr_debug("Queue Priority: %d, %d\n", q_properties->priority, args->queue_priority); - pr_debug("Queue Address (0x%llX, 0x%llX)\n", + pr_debug("Queue Address: 0x%llX, 0x%llX\n", q_properties->queue_address, args->ring_base_address); - pr_debug("Queue Size (0x%llX, %u)\n", + pr_debug("Queue Size: 0x%llX, %u\n", q_properties->queue_size, args->ring_size); - pr_debug("Queue r/w Pointers (0x%llX, 0x%llX)\n", - (uint64_t) q_properties->read_ptr, - (uint64_t) q_properties->write_ptr); + pr_debug("Queue r/w Pointers: %p, %p\n", + q_properties->read_ptr, + q_properties->write_ptr); - pr_debug("Queue Format (%d)\n", q_properties->format); + pr_debug("Queue Format: %d\n", q_properties->format); - pr_debug("Queue EOP (0x%llX)\n", q_properties->eop_ring_buffer_address); + pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); - pr_debug("Queue CTX save arex (0x%llX)\n", + pr_debug("Queue CTX save area: 0x%llX\n", q_properties->ctx_save_restore_area_address); return 0; @@ -257,16 +257,16 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, memset(&q_properties, 0, sizeof(struct queue_properties)); - pr_debug("kfd: creating queue ioctl\n"); + pr_debug("Creating queue ioctl\n"); err = set_queue_properties_from_user(&q_properties, args); if (err) return err; - pr_debug("kfd: looking for gpu id 0x%x\n", args->gpu_id); + pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) { - pr_debug("kfd: gpu id 0x%x was not found\n", args->gpu_id); + if (!dev) { + pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); return -EINVAL; } @@ -278,7 +278,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, goto err_bind_process; } - pr_debug("kfd: creating queue for PASID %d on GPU 0x%x\n", + pr_debug("Creating queue for PASID %d on gpu 0x%x\n", p->pasid, dev->id); @@ -296,15 +296,15 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, mutex_unlock(&p->mutex); - pr_debug("kfd: queue id %d was created successfully\n", args->queue_id); + pr_debug("Queue id %d was created successfully\n", args->queue_id); - pr_debug("ring buffer address == 0x%016llX\n", + pr_debug("Ring buffer address == 0x%016llX\n", args->ring_base_address); - pr_debug("read ptr address == 0x%016llX\n", + pr_debug("Read ptr address == 0x%016llX\n", args->read_pointer_address); - pr_debug("write ptr address == 0x%016llX\n", + pr_debug("Write ptr address == 0x%016llX\n", args->write_pointer_address); return 0; @@ -321,7 +321,7 @@ static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, int retval; struct kfd_ioctl_destroy_queue_args *args = data; - pr_debug("kfd: destroying queue id %d for PASID %d\n", + pr_debug("Destroying queue id %d for pasid %d\n", args->queue_id, p->pasid); @@ -341,12 +341,12 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, struct queue_properties properties; if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { - pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); + pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); return -EINVAL; } if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { - pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); + pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); return -EINVAL; } @@ -354,12 +354,12 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, (!access_ok(VERIFY_WRITE, (const void __user *) args->ring_base_address, sizeof(uint64_t)))) { - pr_err("kfd: can't access ring base address\n"); + pr_err("Can't access ring base address\n"); return -EFAULT; } if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { - pr_err("kfd: ring size must be a power of 2 or 0\n"); + pr_err("Ring size must be a power of 2 or 0\n"); return -EINVAL; } @@ -368,7 +368,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, properties.queue_percent = args->queue_percentage; properties.priority = args->queue_priority; - pr_debug("kfd: updating queue id %d for PASID %d\n", + pr_debug("Updating queue id %d for pasid %d\n", args->queue_id, p->pasid); mutex_lock(&p->mutex); @@ -400,7 +400,7 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, } dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; mutex_lock(&p->mutex); @@ -443,7 +443,7 @@ static int kfd_ioctl_dbg_register(struct file *filep, long status = 0; dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -460,12 +460,11 @@ static int kfd_ioctl_dbg_register(struct file *filep, */ pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - mutex_unlock(&p->mutex); - mutex_unlock(kfd_get_dbgmgr_mutex()); - return PTR_ERR(pdd); + status = PTR_ERR(pdd); + goto out; } - if (dev->dbgmgr == NULL) { + if (!dev->dbgmgr) { /* In case of a legal call, we have no dbgmgr yet */ create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev); if (create_ok) { @@ -480,6 +479,7 @@ static int kfd_ioctl_dbg_register(struct file *filep, status = -EINVAL; } +out: mutex_unlock(&p->mutex); mutex_unlock(kfd_get_dbgmgr_mutex()); @@ -494,7 +494,7 @@ static int kfd_ioctl_dbg_unregister(struct file *filep, long status; dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -505,7 +505,7 @@ static int kfd_ioctl_dbg_unregister(struct file *filep, mutex_lock(kfd_get_dbgmgr_mutex()); status = kfd_dbgmgr_unregister(dev->dbgmgr, p); - if (status == 0) { + if (!status) { kfd_dbgmgr_destroy(dev->dbgmgr); dev->dbgmgr = NULL; } @@ -539,7 +539,7 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info)); dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -580,8 +580,8 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points; if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) { - kfree(args_buff); - return -EINVAL; + status = -EINVAL; + goto out; } watch_mask_value = (uint64_t) args_buff[args_idx]; @@ -604,8 +604,8 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, } if (args_idx >= args->buf_size_in_bytes - sizeof(args)) { - kfree(args_buff); - return -EINVAL; + status = -EINVAL; + goto out; } /* Currently HSA Event is not supported for DBG */ @@ -617,6 +617,7 @@ static int kfd_ioctl_dbg_address_watch(struct file *filep, mutex_unlock(kfd_get_dbgmgr_mutex()); +out: kfree(args_buff); return status; @@ -646,7 +647,7 @@ static int kfd_ioctl_dbg_wave_control(struct file *filep, sizeof(wac_info.trapId); dev = kfd_device_by_id(args->gpu_id); - if (dev == NULL) + if (!dev) return -EINVAL; if (dev->device_info->asic_family == CHIP_CARRIZO) { @@ -782,8 +783,9 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, "scratch_limit %llX\n", pdd->scratch_limit); args->num_of_nodes++; - } while ((pdd = kfd_get_next_process_device_data(p, pdd)) != NULL && - (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS)); + + pdd = kfd_get_next_process_device_data(p, pdd); + } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS)); } mutex_unlock(&p->mutex); @@ -846,9 +848,84 @@ static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, return err; } +static int kfd_ioctl_set_scratch_backing_va(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_set_scratch_backing_va_args *args = data; + struct kfd_process_device *pdd; + struct kfd_dev *dev; + long err; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + mutex_lock(&p->mutex); + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + err = PTR_ERR(pdd); + goto bind_process_to_device_fail; + } + + pdd->qpd.sh_hidden_private_base = args->va_addr; + + mutex_unlock(&p->mutex); + + if (sched_policy == KFD_SCHED_POLICY_NO_HWS && pdd->qpd.vmid != 0) + dev->kfd2kgd->set_scratch_backing_va( + dev->kgd, args->va_addr, pdd->qpd.vmid); + + return 0; + +bind_process_to_device_fail: + mutex_unlock(&p->mutex); + return err; +} + +static int kfd_ioctl_get_tile_config(struct file *filep, + struct kfd_process *p, void *data) +{ + struct kfd_ioctl_get_tile_config_args *args = data; + struct kfd_dev *dev; + struct tile_config config; + int err = 0; + + dev = kfd_device_by_id(args->gpu_id); + + dev->kfd2kgd->get_tile_config(dev->kgd, &config); + + args->gb_addr_config = config.gb_addr_config; + args->num_banks = config.num_banks; + args->num_ranks = config.num_ranks; + + if (args->num_tile_configs > config.num_tile_configs) + args->num_tile_configs = config.num_tile_configs; + err = copy_to_user((void __user *)args->tile_config_ptr, + config.tile_config_ptr, + args->num_tile_configs * sizeof(uint32_t)); + if (err) { + args->num_tile_configs = 0; + return -EFAULT; + } + + if (args->num_macro_tile_configs > config.num_macro_tile_configs) + args->num_macro_tile_configs = + config.num_macro_tile_configs; + err = copy_to_user((void __user *)args->macro_tile_config_ptr, + config.macro_tile_config_ptr, + args->num_macro_tile_configs * sizeof(uint32_t)); + if (err) { + args->num_macro_tile_configs = 0; + return -EFAULT; + } + + return 0; +} #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ - [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl} + [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ + .cmd_drv = 0, .name = #ioctl} /** Ioctl table */ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { @@ -899,6 +976,12 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL, kfd_ioctl_dbg_wave_control, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, + kfd_ioctl_set_scratch_backing_va, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, + kfd_ioctl_get_tile_config, 0) }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index d5e19b5fbbfb..0aa021aa0aa1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -42,8 +42,6 @@ static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev) { - BUG_ON(!dev || !dev->kfd2kgd); - dev->kfd2kgd->address_watch_disable(dev->kgd); } @@ -62,7 +60,8 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, unsigned int *ib_packet_buff; int status; - BUG_ON(!dbgdev || !dbgdev->kq || !packet_buff || !size_in_bytes); + if (WARN_ON(!size_in_bytes)) + return -EINVAL; kq = dbgdev->kq; @@ -77,8 +76,8 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, status = kq->ops.acquire_packet_buffer(kq, pq_packets_size_in_bytes / sizeof(uint32_t), &ib_packet_buff); - if (status != 0) { - pr_err("amdkfd: acquire_packet_buffer failed\n"); + if (status) { + pr_err("acquire_packet_buffer failed\n"); return status; } @@ -115,8 +114,8 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, status = kfd_gtt_sa_allocate(dbgdev->dev, sizeof(uint64_t), &mem_obj); - if (status != 0) { - pr_err("amdkfd: Failed to allocate GART memory\n"); + if (status) { + pr_err("Failed to allocate GART memory\n"); kq->ops.rollback_packet(kq); return status; } @@ -168,8 +167,6 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev) { - BUG_ON(!dbgdev); - /* * no action is needed in this case, * just make sure diq will not be used @@ -187,14 +184,12 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) struct kernel_queue *kq = NULL; int status; - BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->dev); - status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL, &properties, 0, KFD_QUEUE_TYPE_DIQ, &qid); if (status) { - pr_err("amdkfd: Failed to create DIQ\n"); + pr_err("Failed to create DIQ\n"); return status; } @@ -202,8 +197,8 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) kq = pqm_get_kernel_queue(dbgdev->pqm, qid); - if (kq == NULL) { - pr_err("amdkfd: Error getting DIQ\n"); + if (!kq) { + pr_err("Error getting DIQ\n"); pqm_destroy_queue(dbgdev->pqm, qid); return -EFAULT; } @@ -215,8 +210,6 @@ static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev) static int dbgdev_unregister_nodiq(struct kfd_dbgdev *dbgdev) { - BUG_ON(!dbgdev || !dbgdev->dev); - /* disable watch address */ dbgdev_address_watch_disable_nodiq(dbgdev->dev); return 0; @@ -227,8 +220,6 @@ static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev) /* todo - disable address watch */ int status; - BUG_ON(!dbgdev || !dbgdev->pqm || !dbgdev->kq); - status = pqm_destroy_queue(dbgdev->pqm, dbgdev->kq->queue->properties.queue_id); dbgdev->kq = NULL; @@ -245,14 +236,12 @@ static void dbgdev_address_watch_set_registers( { union ULARGE_INTEGER addr; - BUG_ON(!adw_info || !addrHi || !addrLo || !cntl); - addr.quad_part = 0; addrHi->u32All = 0; addrLo->u32All = 0; cntl->u32All = 0; - if (adw_info->watch_mask != NULL) + if (adw_info->watch_mask) cntl->bitfields.mask = (uint32_t) (adw_info->watch_mask[index] & ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK); @@ -279,7 +268,7 @@ static void dbgdev_address_watch_set_registers( } static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, - struct dbg_address_watch_info *adw_info) + struct dbg_address_watch_info *adw_info) { union TCP_WATCH_ADDR_H_BITS addrHi; union TCP_WATCH_ADDR_L_BITS addrLo; @@ -287,13 +276,11 @@ static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, struct kfd_process_device *pdd; unsigned int i; - BUG_ON(!dbgdev || !dbgdev->dev || !adw_info); - /* taking the vmid for that process on the safe way using pdd */ pdd = kfd_get_process_device_data(dbgdev->dev, adw_info->process); if (!pdd) { - pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n"); + pr_err("Failed to get pdd for wave control no DIQ\n"); return -EFAULT; } @@ -303,17 +290,16 @@ static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) || (adw_info->num_watch_points == 0)) { - pr_err("amdkfd: num_watch_points is invalid\n"); + pr_err("num_watch_points is invalid\n"); return -EINVAL; } - if ((adw_info->watch_mode == NULL) || - (adw_info->watch_address == NULL)) { - pr_err("amdkfd: adw_info fields are not valid\n"); + if (!adw_info->watch_mode || !adw_info->watch_address) { + pr_err("adw_info fields are not valid\n"); return -EINVAL; } - for (i = 0 ; i < adw_info->num_watch_points ; i++) { + for (i = 0; i < adw_info->num_watch_points; i++) { dbgdev_address_watch_set_registers(adw_info, &addrHi, &addrLo, &cntl, i, pdd->qpd.vmid); @@ -348,7 +334,7 @@ static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev, } static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, - struct dbg_address_watch_info *adw_info) + struct dbg_address_watch_info *adw_info) { struct pm4__set_config_reg *packets_vec; union TCP_WATCH_ADDR_H_BITS addrHi; @@ -363,28 +349,25 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, /* we do not control the vmid in DIQ mode, just a place holder */ unsigned int vmid = 0; - BUG_ON(!dbgdev || !dbgdev->dev || !adw_info); - addrHi.u32All = 0; addrLo.u32All = 0; cntl.u32All = 0; if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) || (adw_info->num_watch_points == 0)) { - pr_err("amdkfd: num_watch_points is invalid\n"); + pr_err("num_watch_points is invalid\n"); return -EINVAL; } - if ((NULL == adw_info->watch_mode) || - (NULL == adw_info->watch_address)) { - pr_err("amdkfd: adw_info fields are not valid\n"); + if (!adw_info->watch_mode || !adw_info->watch_address) { + pr_err("adw_info fields are not valid\n"); return -EINVAL; } status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj); - if (status != 0) { - pr_err("amdkfd: Failed to allocate GART memory\n"); + if (status) { + pr_err("Failed to allocate GART memory\n"); return status; } @@ -442,8 +425,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_CNTL); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[0].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; @@ -455,8 +436,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_ADDR_HI); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[1].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[1].reg_data[0] = addrHi.u32All; @@ -467,8 +446,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_ADDR_LO); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[2].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[2].reg_data[0] = addrLo.u32All; @@ -485,8 +462,6 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, i, ADDRESS_WATCH_REG_CNTL); - aw_reg_add_dword /= sizeof(uint32_t); - packets_vec[3].bitfields2.reg_offset = aw_reg_add_dword - AMD_CONFIG_REG_BASE; packets_vec[3].reg_data[0] = cntl.u32All; @@ -498,8 +473,8 @@ static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev, packet_buff_uint, ib_size); - if (status != 0) { - pr_err("amdkfd: Failed to submit IB to DIQ\n"); + if (status) { + pr_err("Failed to submit IB to DIQ\n"); break; } } @@ -518,8 +493,6 @@ static int dbgdev_wave_control_set_registers( union GRBM_GFX_INDEX_BITS reg_gfx_index; struct HsaDbgWaveMsgAMDGen2 *pMsg; - BUG_ON(!wac_info || !in_reg_sq_cmd || !in_reg_gfx_index); - reg_sq_cmd.u32All = 0; reg_gfx_index.u32All = 0; pMsg = &wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2; @@ -620,18 +593,16 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, struct pm4__set_config_reg *packets_vec; size_t ib_size = sizeof(struct pm4__set_config_reg) * 3; - BUG_ON(!dbgdev || !wac_info); - reg_sq_cmd.u32All = 0; status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd, ®_gfx_index); if (status) { - pr_err("amdkfd: Failed to set wave control registers\n"); + pr_err("Failed to set wave control registers\n"); return status; } - /* we do not control the VMID in DIQ,so reset it to a known value */ + /* we do not control the VMID in DIQ, so reset it to a known value */ reg_sq_cmd.bits.vm_id = 0; pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); @@ -667,7 +638,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj); if (status != 0) { - pr_err("amdkfd: Failed to allocate GART memory\n"); + pr_err("Failed to allocate GART memory\n"); return status; } @@ -719,8 +690,8 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev, packet_buff_uint, ib_size); - if (status != 0) - pr_err("amdkfd: Failed to submit IB to DIQ\n"); + if (status) + pr_err("Failed to submit IB to DIQ\n"); kfd_gtt_sa_free(dbgdev->dev, mem_obj); @@ -735,21 +706,19 @@ static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev, union GRBM_GFX_INDEX_BITS reg_gfx_index; struct kfd_process_device *pdd; - BUG_ON(!dbgdev || !dbgdev->dev || !wac_info); - reg_sq_cmd.u32All = 0; /* taking the VMID for that process on the safe way using PDD */ pdd = kfd_get_process_device_data(dbgdev->dev, wac_info->process); if (!pdd) { - pr_err("amdkfd: Failed to get pdd for wave control no DIQ\n"); + pr_err("Failed to get pdd for wave control no DIQ\n"); return -EFAULT; } status = dbgdev_wave_control_set_registers(wac_info, ®_sq_cmd, ®_gfx_index); if (status) { - pr_err("amdkfd: Failed to set wave control registers\n"); + pr_err("Failed to set wave control registers\n"); return status; } @@ -818,12 +787,13 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) /* Scan all registers in the range ATC_VMID8_PASID_MAPPING .. * ATC_VMID15_PASID_MAPPING - * to check which VMID the current process is mapped to. */ + * to check which VMID the current process is mapped to. + */ for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) { if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid (dev->kgd, vmid)) { - if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid + if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid (dev->kgd, vmid) == p->pasid) { pr_debug("Killing wave fronts of vmid %d and pasid %d\n", vmid, p->pasid); @@ -833,7 +803,7 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) } if (vmid > last_vmid_to_scan) { - pr_err("amdkfd: didn't found vmid for pasid (%d)\n", p->pasid); + pr_err("Didn't find vmid for pasid %d\n", p->pasid); return -EFAULT; } @@ -860,8 +830,6 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, enum DBGDEV_TYPE type) { - BUG_ON(!pdbgdev || !pdev); - pdbgdev->dev = pdev; pdbgdev->kq = NULL; pdbgdev->type = type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c index 56d676396342..3da25f7bda6b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c @@ -44,8 +44,6 @@ struct mutex *kfd_get_dbgmgr_mutex(void) static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr) { - BUG_ON(!pmgr); - kfree(pmgr->dbgdev); pmgr->dbgdev = NULL; @@ -55,7 +53,7 @@ static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr) void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr) { - if (pmgr != NULL) { + if (pmgr) { kfd_dbgmgr_uninitialize(pmgr); kfree(pmgr); } @@ -66,12 +64,12 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) enum DBGDEV_TYPE type = DBGDEV_TYPE_DIQ; struct kfd_dbgmgr *new_buff; - BUG_ON(pdev == NULL); - BUG_ON(!pdev->init_complete); + if (WARN_ON(!pdev->init_complete)) + return false; new_buff = kfd_alloc_struct(new_buff); if (!new_buff) { - pr_err("amdkfd: Failed to allocate dbgmgr instance\n"); + pr_err("Failed to allocate dbgmgr instance\n"); return false; } @@ -79,7 +77,7 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) new_buff->dev = pdev; new_buff->dbgdev = kfd_alloc_struct(new_buff->dbgdev); if (!new_buff->dbgdev) { - pr_err("amdkfd: Failed to allocate dbgdev instance\n"); + pr_err("Failed to allocate dbgdev instance\n"); kfree(new_buff); return false; } @@ -96,8 +94,6 @@ bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev) long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p) { - BUG_ON(!p || !pmgr || !pmgr->dbgdev); - if (pmgr->pasid != 0) { pr_debug("H/W debugger is already active using pasid %d\n", pmgr->pasid); @@ -118,8 +114,6 @@ long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p) long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p) { - BUG_ON(!p || !pmgr || !pmgr->dbgdev); - /* Is the requests coming from the already registered process? */ if (pmgr->pasid != p->pasid) { pr_debug("H/W debugger is not registered by calling pasid %d\n", @@ -137,8 +131,6 @@ long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p) long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, struct dbg_wave_control_info *wac_info) { - BUG_ON(!pmgr || !pmgr->dbgdev || !wac_info); - /* Is the requests coming from the already registered process? */ if (pmgr->pasid != wac_info->process->pasid) { pr_debug("H/W debugger support was not registered for requester pasid %d\n", @@ -152,9 +144,6 @@ long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr, struct dbg_address_watch_info *adw_info) { - BUG_ON(!pmgr || !pmgr->dbgdev || !adw_info); - - /* Is the requests coming from the already registered process? */ if (pmgr->pasid != adw_info->process->pasid) { pr_debug("H/W debugger support was not registered for requester pasid %d\n", diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h index 257a745ad0b5..a04a1fe1d0d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h @@ -30,13 +30,11 @@ #pragma pack(push, 4) enum HSA_DBG_WAVEOP { - HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ - HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ - HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ - HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter - debug mode */ - HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take - a trap */ + HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ + HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ + HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ + HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter dbg mode */ + HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take a trap */ HSA_DBG_NUM_WAVEOP = 5, HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF }; @@ -81,15 +79,13 @@ struct HsaDbgWaveMsgAMDGen2 { uint32_t UserData:8; /* user data */ uint32_t ShaderArray:1; /* Shader array */ uint32_t Priv:1; /* Privileged */ - uint32_t Reserved0:4; /* This field is reserved, - should be 0 */ + uint32_t Reserved0:4; /* Reserved, should be 0 */ uint32_t WaveId:4; /* wave id */ uint32_t SIMD:2; /* SIMD id */ uint32_t HSACU:4; /* Compute unit */ uint32_t ShaderEngine:2;/* Shader engine */ uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */ - uint32_t Reserved1:4; /* This field is reserved, - should be 0 */ + uint32_t Reserved1:4; /* Reserved, should be 0 */ } ui32; uint32_t Value; }; @@ -121,20 +117,23 @@ struct HsaDbgWaveMessage { * in the user mode instruction stream. The OS scheduler event is typically * associated and signaled by an interrupt issued by the GPU, but other HSA * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced - * by the KFD by this mechanism, too. */ + * by the KFD by this mechanism, too. + */ /* these are the new definitions for events */ enum HSA_EVENTTYPE { HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */ HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */ HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change - (start/stop) */ + * (start/stop) + */ HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */ HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */ HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */ HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */ HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state - (EOP pm4) */ + * (EOP pm4) + */ /* ... */ HSA_EVENTTYPE_MAXID, HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 3f95f7cb4019..61fff25b4ce7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -26,7 +26,7 @@ #include <linux/slab.h> #include "kfd_priv.h" #include "kfd_device_queue_manager.h" -#include "kfd_pm4_headers.h" +#include "kfd_pm4_headers_vi.h" #define MQD_SIZE_ALIGNED 768 @@ -98,11 +98,14 @@ static const struct kfd_device_info *lookup_device_info(unsigned short did) for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { if (supported_devices[i].did == did) { - BUG_ON(supported_devices[i].device_info == NULL); + WARN_ON(!supported_devices[i].device_info); return supported_devices[i].device_info; } } + dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", + did); + return NULL; } @@ -114,8 +117,10 @@ struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, const struct kfd_device_info *device_info = lookup_device_info(pdev->device); - if (!device_info) + if (!device_info) { + dev_err(kfd_device, "kgd2kfd_probe failed\n"); return NULL; + } kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); if (!kfd) @@ -152,15 +157,16 @@ static bool device_iommu_pasid_init(struct kfd_dev *kfd) } if ((iommu_info.flags & required_iommu_flags) != required_iommu_flags) { - dev_err(kfd_device, "error required iommu flags ats(%i), pri(%i), pasid(%i)\n", + dev_err(kfd_device, "error required iommu flags ats %i, pri %i, pasid %i\n", (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP) != 0, (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) != 0, - (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) != 0); + (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) + != 0); return false; } pasid_limit = min_t(unsigned int, - (unsigned int)1 << kfd->device_info->max_pasid_bits, + (unsigned int)(1 << kfd->device_info->max_pasid_bits), iommu_info.max_pasids); /* * last pasid is used for kernel queues doorbells @@ -211,9 +217,8 @@ static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid, flags); dev = kfd_device_by_pci_dev(pdev); - BUG_ON(dev == NULL); - - kfd_signal_iommu_event(dev, pasid, address, + if (!WARN_ON(!dev)) + kfd_signal_iommu_event(dev, pasid, address, flags & PPR_FAULT_WRITE, flags & PPR_FAULT_EXEC); return AMD_IOMMU_INV_PRI_RSP_INVALID; @@ -234,9 +239,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, * calculate max size of runlist packet. * There can be only 2 packets at once */ - size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_map_process) + - max_num_of_queues_per_device * - sizeof(struct pm4_map_queues) + sizeof(struct pm4_runlist)) * 2; + size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + + max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) + + sizeof(struct pm4_mes_runlist)) * 2; /* Add size of HIQ & DIQ */ size += KFD_KERNEL_QUEUE_SIZE * 2; @@ -247,42 +252,37 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, if (kfd->kfd2kgd->init_gtt_mem_allocation( kfd->kgd, size, &kfd->gtt_mem, &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){ - dev_err(kfd_device, - "Could not allocate %d bytes for device (%x:%x)\n", - size, kfd->pdev->vendor, kfd->pdev->device); + dev_err(kfd_device, "Could not allocate %d bytes\n", size); goto out; } - dev_info(kfd_device, - "Allocated %d bytes on gart for device(%x:%x)\n", - size, kfd->pdev->vendor, kfd->pdev->device); + dev_info(kfd_device, "Allocated %d bytes on gart\n", size); /* Initialize GTT sa with 512 byte chunk size */ if (kfd_gtt_sa_init(kfd, size, 512) != 0) { - dev_err(kfd_device, - "Error initializing gtt sub-allocator\n"); + dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); goto kfd_gtt_sa_init_error; } - kfd_doorbell_init(kfd); - - if (kfd_topology_add_device(kfd) != 0) { + if (kfd_doorbell_init(kfd)) { dev_err(kfd_device, - "Error adding device (%x:%x) to topology\n", - kfd->pdev->vendor, kfd->pdev->device); + "Error initializing doorbell aperture\n"); + goto kfd_doorbell_error; + } + + if (kfd_topology_add_device(kfd)) { + dev_err(kfd_device, "Error adding device to topology\n"); goto kfd_topology_add_device_error; } if (kfd_interrupt_init(kfd)) { - dev_err(kfd_device, - "Error initializing interrupts for device (%x:%x)\n", - kfd->pdev->vendor, kfd->pdev->device); + dev_err(kfd_device, "Error initializing interrupts\n"); goto kfd_interrupt_error; } if (!device_iommu_pasid_init(kfd)) { dev_err(kfd_device, - "Error initializing iommuv2 for device (%x:%x)\n", + "Error initializing iommuv2 for device %x:%x\n", kfd->pdev->vendor, kfd->pdev->device); goto device_iommu_pasid_error; } @@ -292,15 +292,13 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->dqm = device_queue_manager_init(kfd); if (!kfd->dqm) { - dev_err(kfd_device, - "Error initializing queue manager for device (%x:%x)\n", - kfd->pdev->vendor, kfd->pdev->device); + dev_err(kfd_device, "Error initializing queue manager\n"); goto device_queue_manager_error; } - if (kfd->dqm->ops.start(kfd->dqm) != 0) { + if (kfd->dqm->ops.start(kfd->dqm)) { dev_err(kfd_device, - "Error starting queuen manager for device (%x:%x)\n", + "Error starting queue manager for device %x:%x\n", kfd->pdev->vendor, kfd->pdev->device); goto dqm_start_error; } @@ -308,10 +306,10 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, kfd->dbgmgr = NULL; kfd->init_complete = true; - dev_info(kfd_device, "added device (%x:%x)\n", kfd->pdev->vendor, + dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, kfd->pdev->device); - pr_debug("kfd: Starting kfd with the following scheduling policy %d\n", + pr_debug("Starting kfd with the following scheduling policy %d\n", sched_policy); goto out; @@ -325,11 +323,13 @@ device_iommu_pasid_error: kfd_interrupt_error: kfd_topology_remove_device(kfd); kfd_topology_add_device_error: + kfd_doorbell_fini(kfd); +kfd_doorbell_error: kfd_gtt_sa_fini(kfd); kfd_gtt_sa_init_error: kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); dev_err(kfd_device, - "device (%x:%x) NOT added due to errors\n", + "device %x:%x NOT added due to errors\n", kfd->pdev->vendor, kfd->pdev->device); out: return kfd->init_complete; @@ -342,6 +342,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) amd_iommu_free_device(kfd->pdev); kfd_interrupt_exit(kfd); kfd_topology_remove_device(kfd); + kfd_doorbell_fini(kfd); kfd_gtt_sa_fini(kfd); kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); } @@ -351,8 +352,6 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) void kgd2kfd_suspend(struct kfd_dev *kfd) { - BUG_ON(kfd == NULL); - if (kfd->init_complete) { kfd->dqm->ops.stop(kfd->dqm); amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL); @@ -366,14 +365,15 @@ int kgd2kfd_resume(struct kfd_dev *kfd) unsigned int pasid_limit; int err; - BUG_ON(kfd == NULL); - pasid_limit = kfd_get_pasid_limit(); if (kfd->init_complete) { err = amd_iommu_init_device(kfd->pdev, pasid_limit); - if (err < 0) + if (err < 0) { + dev_err(kfd_device, "failed to initialize iommu\n"); return -ENXIO; + } + amd_iommu_set_invalidate_ctx_cb(kfd->pdev, iommu_pasid_shutdown_callback); amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb); @@ -402,26 +402,27 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, unsigned int chunk_size) { - unsigned int num_of_bits; + unsigned int num_of_longs; - BUG_ON(!kfd); - BUG_ON(!kfd->gtt_mem); - BUG_ON(buf_size < chunk_size); - BUG_ON(buf_size == 0); - BUG_ON(chunk_size == 0); + if (WARN_ON(buf_size < chunk_size)) + return -EINVAL; + if (WARN_ON(buf_size == 0)) + return -EINVAL; + if (WARN_ON(chunk_size == 0)) + return -EINVAL; kfd->gtt_sa_chunk_size = chunk_size; kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; - num_of_bits = kfd->gtt_sa_num_of_chunks / BITS_PER_BYTE; - BUG_ON(num_of_bits == 0); + num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / + BITS_PER_LONG; - kfd->gtt_sa_bitmap = kzalloc(num_of_bits, GFP_KERNEL); + kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); if (!kfd->gtt_sa_bitmap) return -ENOMEM; - pr_debug("kfd: gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", + pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); mutex_init(&kfd->gtt_sa_lock); @@ -455,8 +456,6 @@ int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, { unsigned int found, start_search, cur_size; - BUG_ON(!kfd); - if (size == 0) return -EINVAL; @@ -467,7 +466,7 @@ int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, if ((*mem_obj) == NULL) return -ENOMEM; - pr_debug("kfd: allocated mem_obj = %p for size = %d\n", *mem_obj, size); + pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); start_search = 0; @@ -479,7 +478,7 @@ kfd_gtt_restart_search: kfd->gtt_sa_num_of_chunks, start_search); - pr_debug("kfd: found = %d\n", found); + pr_debug("Found = %d\n", found); /* If there wasn't any free chunk, bail out */ if (found == kfd->gtt_sa_num_of_chunks) @@ -497,12 +496,12 @@ kfd_gtt_restart_search: found, kfd->gtt_sa_chunk_size); - pr_debug("kfd: gpu_addr = %p, cpu_addr = %p\n", + pr_debug("gpu_addr = %p, cpu_addr = %p\n", (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); /* If we need only one chunk, mark it as allocated and get out */ if (size <= kfd->gtt_sa_chunk_size) { - pr_debug("kfd: single bit\n"); + pr_debug("Single bit\n"); set_bit(found, kfd->gtt_sa_bitmap); goto kfd_gtt_out; } @@ -537,7 +536,7 @@ kfd_gtt_restart_search: } while (cur_size > 0); - pr_debug("kfd: range_start = %d, range_end = %d\n", + pr_debug("range_start = %d, range_end = %d\n", (*mem_obj)->range_start, (*mem_obj)->range_end); /* Mark the chunks as allocated */ @@ -551,7 +550,7 @@ kfd_gtt_out: return 0; kfd_gtt_no_free_chunk: - pr_debug("kfd: allocation failed with mem_obj = %p\n", mem_obj); + pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); mutex_unlock(&kfd->gtt_sa_lock); kfree(mem_obj); return -ENOMEM; @@ -561,13 +560,11 @@ int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) { unsigned int bit; - BUG_ON(!kfd); - /* Act like kfree when trying to free a NULL object */ if (!mem_obj) return 0; - pr_debug("kfd: free mem_obj = %p, range_start = %d, range_end = %d\n", + pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", mem_obj, mem_obj->range_start, mem_obj->range_end); mutex_lock(&kfd->gtt_sa_lock); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 42de22bbe14c..53a66e821624 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -79,20 +79,17 @@ static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) unsigned int get_queues_num(struct device_queue_manager *dqm) { - BUG_ON(!dqm || !dqm->dev); return bitmap_weight(dqm->dev->shared_resources.queue_bitmap, KGD_MAX_QUEUES); } unsigned int get_queues_per_pipe(struct device_queue_manager *dqm) { - BUG_ON(!dqm || !dqm->dev); return dqm->dev->shared_resources.num_queue_per_pipe; } unsigned int get_pipes_per_mec(struct device_queue_manager *dqm) { - BUG_ON(!dqm || !dqm->dev); return dqm->dev->shared_resources.num_pipe_per_mec; } @@ -121,7 +118,7 @@ static int allocate_vmid(struct device_queue_manager *dqm, /* Kaveri kfd vmid's starts from vmid 8 */ allocated_vmid = bit + KFD_VMID_START_OFFSET; - pr_debug("kfd: vmid allocation %d\n", allocated_vmid); + pr_debug("vmid allocation %d\n", allocated_vmid); qpd->vmid = allocated_vmid; q->properties.vmid = allocated_vmid; @@ -152,42 +149,38 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, { int retval; - BUG_ON(!dqm || !q || !qpd || !allocated_vmid); - - pr_debug("kfd: In func %s\n", __func__); print_queue(q); mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { - pr_warn("amdkfd: Can't create new usermode queue because %d queues were already created\n", + pr_warn("Can't create new usermode queue because %d queues were already created\n", dqm->total_queue_count); - mutex_unlock(&dqm->lock); - return -EPERM; + retval = -EPERM; + goto out_unlock; } if (list_empty(&qpd->queues_list)) { retval = allocate_vmid(dqm, qpd, q); - if (retval != 0) { - mutex_unlock(&dqm->lock); - return retval; - } + if (retval) + goto out_unlock; } *allocated_vmid = qpd->vmid; q->properties.vmid = qpd->vmid; if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) retval = create_compute_queue_nocpsch(dqm, q, qpd); - if (q->properties.type == KFD_QUEUE_TYPE_SDMA) + else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) retval = create_sdma_queue_nocpsch(dqm, q, qpd); + else + retval = -EINVAL; - if (retval != 0) { + if (retval) { if (list_empty(&qpd->queues_list)) { deallocate_vmid(dqm, qpd, q); *allocated_vmid = 0; } - mutex_unlock(&dqm->lock); - return retval; + goto out_unlock; } list_add(&q->list, &qpd->queues_list); @@ -205,8 +198,9 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, pr_debug("Total of %d queues are accountable so far\n", dqm->total_queue_count); +out_unlock: mutex_unlock(&dqm->lock); - return 0; + return retval; } static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) @@ -216,7 +210,8 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) set = false; - for (pipe = dqm->next_pipe_to_allocate, i = 0; i < get_pipes_per_mec(dqm); + for (pipe = dqm->next_pipe_to_allocate, i = 0; + i < get_pipes_per_mec(dqm); pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) { if (!is_pipe_enabled(dqm, 0, pipe)) @@ -239,8 +234,7 @@ static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q) if (!set) return -EBUSY; - pr_debug("kfd: DQM %s hqd slot - pipe (%d) queue(%d)\n", - __func__, q->pipe, q->queue); + pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue); /* horizontal hqd allocation */ dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm); @@ -260,36 +254,38 @@ static int create_compute_queue_nocpsch(struct device_queue_manager *dqm, int retval; struct mqd_manager *mqd; - BUG_ON(!dqm || !q || !qpd); - mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE); - if (mqd == NULL) + if (!mqd) return -ENOMEM; retval = allocate_hqd(dqm, q); - if (retval != 0) + if (retval) return retval; retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - if (retval != 0) { - deallocate_hqd(dqm, q); - return retval; - } + if (retval) + goto out_deallocate_hqd; - pr_debug("kfd: loading mqd to hqd on pipe (%d) queue (%d)\n", - q->pipe, - q->queue); + pr_debug("Loading mqd to hqd on pipe %d, queue %d\n", + q->pipe, q->queue); - retval = mqd->load_mqd(mqd, q->mqd, q->pipe, - q->queue, (uint32_t __user *) q->properties.write_ptr); - if (retval != 0) { - deallocate_hqd(dqm, q); - mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); - return retval; - } + dqm->dev->kfd2kgd->set_scratch_backing_va( + dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid); + + retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties, + q->process->mm); + if (retval) + goto out_uninit_mqd; return 0; + +out_uninit_mqd: + mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); +out_deallocate_hqd: + deallocate_hqd(dqm, q); + + return retval; } static int destroy_queue_nocpsch(struct device_queue_manager *dqm, @@ -299,12 +295,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, int retval; struct mqd_manager *mqd; - BUG_ON(!dqm || !q || !q->mqd || !qpd); - retval = 0; - pr_debug("kfd: In Func %s\n", __func__); - mutex_lock(&dqm->lock); if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) { @@ -323,7 +315,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, dqm->sdma_queue_count--; deallocate_sdma_queue(dqm, q->sdma_id); } else { - pr_debug("q->properties.type is invalid (%d)\n", + pr_debug("q->properties.type %d is invalid\n", q->properties.type); retval = -EINVAL; goto out; @@ -334,7 +326,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS, q->pipe, q->queue); - if (retval != 0) + if (retval) goto out; mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); @@ -364,14 +356,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) struct mqd_manager *mqd; bool prev_active = false; - BUG_ON(!dqm || !q || !q->mqd); - mutex_lock(&dqm->lock); mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); - if (mqd == NULL) { - mutex_unlock(&dqm->lock); - return -ENOMEM; + if (!mqd) { + retval = -ENOMEM; + goto out_unlock; } if (q->properties.is_active) @@ -385,12 +375,13 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q) retval = mqd->update_mqd(mqd, q->mqd, &q->properties); if ((q->properties.is_active) && (!prev_active)) dqm->queue_count++; - else if ((!q->properties.is_active) && (prev_active)) + else if (!q->properties.is_active && prev_active) dqm->queue_count--; if (sched_policy != KFD_SCHED_POLICY_NO_HWS) retval = execute_queues_cpsch(dqm, false); +out_unlock: mutex_unlock(&dqm->lock); return retval; } @@ -400,15 +391,16 @@ static struct mqd_manager *get_mqd_manager_nocpsch( { struct mqd_manager *mqd; - BUG_ON(!dqm || type >= KFD_MQD_TYPE_MAX); + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; - pr_debug("kfd: In func %s mqd type %d\n", __func__, type); + pr_debug("mqd type %d\n", type); mqd = dqm->mqds[type]; if (!mqd) { mqd = mqd_manager_init(type, dqm->dev); - if (mqd == NULL) - pr_err("kfd: mqd manager is NULL"); + if (!mqd) + pr_err("mqd manager is NULL"); dqm->mqds[type] = mqd; } @@ -421,11 +413,7 @@ static int register_process_nocpsch(struct device_queue_manager *dqm, struct device_process_node *n; int retval; - BUG_ON(!dqm || !qpd); - - pr_debug("kfd: In func %s\n", __func__); - - n = kzalloc(sizeof(struct device_process_node), GFP_KERNEL); + n = kzalloc(sizeof(*n), GFP_KERNEL); if (!n) return -ENOMEM; @@ -449,10 +437,6 @@ static int unregister_process_nocpsch(struct device_queue_manager *dqm, int retval; struct device_process_node *cur, *next; - BUG_ON(!dqm || !qpd); - - pr_debug("In func %s\n", __func__); - pr_debug("qpd->queues_list is %s\n", list_empty(&qpd->queues_list) ? "empty" : "not empty"); @@ -493,51 +477,39 @@ static void init_interrupts(struct device_queue_manager *dqm) { unsigned int i; - BUG_ON(dqm == NULL); - for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) if (is_pipe_enabled(dqm, 0, i)) dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i); } -static int init_scheduler(struct device_queue_manager *dqm) -{ - int retval = 0; - - BUG_ON(!dqm); - - pr_debug("kfd: In %s\n", __func__); - - return retval; -} - static int initialize_nocpsch(struct device_queue_manager *dqm) { - int i; + int pipe, queue; - BUG_ON(!dqm); + pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); - pr_debug("kfd: In func %s num of pipes: %d\n", - __func__, get_pipes_per_mec(dqm)); + dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), + sizeof(unsigned int), GFP_KERNEL); + if (!dqm->allocated_queues) + return -ENOMEM; mutex_init(&dqm->lock); INIT_LIST_HEAD(&dqm->queues); dqm->queue_count = dqm->next_pipe_to_allocate = 0; dqm->sdma_queue_count = 0; - dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm), - sizeof(unsigned int), GFP_KERNEL); - if (!dqm->allocated_queues) { - mutex_destroy(&dqm->lock); - return -ENOMEM; - } - for (i = 0; i < get_pipes_per_mec(dqm); i++) - dqm->allocated_queues[i] = (1 << get_queues_per_pipe(dqm)) - 1; + for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) { + int pipe_offset = pipe * get_queues_per_pipe(dqm); + + for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) + if (test_bit(pipe_offset + queue, + dqm->dev->shared_resources.queue_bitmap)) + dqm->allocated_queues[pipe] |= 1 << queue; + } dqm->vmid_bitmap = (1 << VMID_PER_DEVICE) - 1; dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1; - init_scheduler(dqm); return 0; } @@ -545,9 +517,7 @@ static void uninitialize_nocpsch(struct device_queue_manager *dqm) { int i; - BUG_ON(!dqm); - - BUG_ON(dqm->queue_count > 0 || dqm->processes_count > 0); + WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0); kfree(dqm->allocated_queues); for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++) @@ -604,33 +574,34 @@ static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm, return -ENOMEM; retval = allocate_sdma_queue(dqm, &q->sdma_id); - if (retval != 0) + if (retval) return retval; q->properties.sdma_queue_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE; q->properties.sdma_engine_id = q->sdma_id / CIK_SDMA_ENGINE_NUM; - pr_debug("kfd: sdma id is: %d\n", q->sdma_id); - pr_debug(" sdma queue id: %d\n", q->properties.sdma_queue_id); - pr_debug(" sdma engine id: %d\n", q->properties.sdma_engine_id); + pr_debug("SDMA id is: %d\n", q->sdma_id); + pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id); + pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id); dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd); retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - if (retval != 0) { - deallocate_sdma_queue(dqm, q->sdma_id); - return retval; - } + if (retval) + goto out_deallocate_sdma_queue; - retval = mqd->load_mqd(mqd, q->mqd, 0, - 0, NULL); - if (retval != 0) { - deallocate_sdma_queue(dqm, q->sdma_id); - mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); - return retval; - } + retval = mqd->load_mqd(mqd, q->mqd, 0, 0, &q->properties, NULL); + if (retval) + goto out_uninit_mqd; return 0; + +out_uninit_mqd: + mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj); +out_deallocate_sdma_queue: + deallocate_sdma_queue(dqm, q->sdma_id); + + return retval; } /* @@ -642,10 +613,6 @@ static int set_sched_resources(struct device_queue_manager *dqm) int i, mec; struct scheduling_resources res; - BUG_ON(!dqm); - - pr_debug("kfd: In func %s\n", __func__); - res.vmid_mask = (1 << VMID_PER_DEVICE) - 1; res.vmid_mask <<= KFD_VMID_START_OFFSET; @@ -663,7 +630,8 @@ static int set_sched_resources(struct device_queue_manager *dqm) /* This situation may be hit in the future if a new HW * generation exposes more than 64 queues. If so, the - * definition of res.queue_mask needs updating */ + * definition of res.queue_mask needs updating + */ if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) { pr_err("Invalid queue enabled by amdgpu: %d\n", i); break; @@ -674,9 +642,9 @@ static int set_sched_resources(struct device_queue_manager *dqm) res.gws_mask = res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0; - pr_debug("kfd: scheduling resources:\n" - " vmid mask: 0x%8X\n" - " queue mask: 0x%8llX\n", + pr_debug("Scheduling resources:\n" + "vmid mask: 0x%8X\n" + "queue mask: 0x%8llX\n", res.vmid_mask, res.queue_mask); return pm_send_set_resources(&dqm->packets, &res); @@ -686,10 +654,7 @@ static int initialize_cpsch(struct device_queue_manager *dqm) { int retval; - BUG_ON(!dqm); - - pr_debug("kfd: In func %s num of pipes: %d\n", - __func__, get_pipes_per_mec(dqm)); + pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm)); mutex_init(&dqm->lock); INIT_LIST_HEAD(&dqm->queues); @@ -697,13 +662,9 @@ static int initialize_cpsch(struct device_queue_manager *dqm) dqm->sdma_queue_count = 0; dqm->active_runlist = false; retval = dqm->ops_asic_specific.initialize(dqm); - if (retval != 0) - goto fail_init_pipelines; - - return 0; + if (retval) + mutex_destroy(&dqm->lock); -fail_init_pipelines: - mutex_destroy(&dqm->lock); return retval; } @@ -712,25 +673,23 @@ static int start_cpsch(struct device_queue_manager *dqm) struct device_process_node *node; int retval; - BUG_ON(!dqm); - retval = 0; retval = pm_init(&dqm->packets, dqm); - if (retval != 0) + if (retval) goto fail_packet_manager_init; retval = set_sched_resources(dqm); - if (retval != 0) + if (retval) goto fail_set_sched_resources; - pr_debug("kfd: allocating fence memory\n"); + pr_debug("Allocating fence memory\n"); /* allocate fence memory on the gart */ retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr), &dqm->fence_mem); - if (retval != 0) + if (retval) goto fail_allocate_vidmem; dqm->fence_addr = dqm->fence_mem->cpu_ptr; @@ -758,8 +717,6 @@ static int stop_cpsch(struct device_queue_manager *dqm) struct device_process_node *node; struct kfd_process_device *pdd; - BUG_ON(!dqm); - destroy_queues_cpsch(dqm, true, true); list_for_each_entry(node, &dqm->queues, list) { @@ -776,13 +733,9 @@ static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd) { - BUG_ON(!dqm || !kq || !qpd); - - pr_debug("kfd: In func %s\n", __func__); - mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { - pr_warn("amdkfd: Can't create new kernel queue because %d queues were already created\n", + pr_warn("Can't create new kernel queue because %d queues were already created\n", dqm->total_queue_count); mutex_unlock(&dqm->lock); return -EPERM; @@ -809,10 +762,6 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd) { - BUG_ON(!dqm || !kq); - - pr_debug("kfd: In %s\n", __func__); - mutex_lock(&dqm->lock); /* here we actually preempt the DIQ */ destroy_queues_cpsch(dqm, true, false); @@ -844,8 +793,6 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, int retval; struct mqd_manager *mqd; - BUG_ON(!dqm || !q || !qpd); - retval = 0; if (allocate_vmid) @@ -854,7 +801,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, mutex_lock(&dqm->lock); if (dqm->total_queue_count >= max_num_of_queues_per_device) { - pr_warn("amdkfd: Can't create new usermode queue because %d queues were already created\n", + pr_warn("Can't create new usermode queue because %d queues were already created\n", dqm->total_queue_count); retval = -EPERM; goto out; @@ -866,15 +813,15 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, mqd = dqm->ops.get_mqd_manager(dqm, get_mqd_type_from_queue_type(q->properties.type)); - if (mqd == NULL) { - mutex_unlock(&dqm->lock); - return -ENOMEM; + if (!mqd) { + retval = -ENOMEM; + goto out; } dqm->ops_asic_specific.init_sdma_vm(dqm, q, qpd); retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj, &q->gart_mqd_addr, &q->properties); - if (retval != 0) + if (retval) goto out; list_add(&q->list, &qpd->queues_list); @@ -884,7 +831,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, } if (q->properties.type == KFD_QUEUE_TYPE_SDMA) - dqm->sdma_queue_count++; + dqm->sdma_queue_count++; /* * Unconditionally increment this counter, regardless of the queue's * type or whether the queue is active. @@ -903,12 +850,11 @@ int amdkfd_fence_wait_timeout(unsigned int *fence_addr, unsigned int fence_value, unsigned long timeout) { - BUG_ON(!fence_addr); timeout += jiffies; while (*fence_addr != fence_value) { if (time_after(jiffies, timeout)) { - pr_err("kfd: qcm fence wait loop timeout expired\n"); + pr_err("qcm fence wait loop timeout expired\n"); return -ETIME; } schedule(); @@ -932,8 +878,6 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, enum kfd_preempt_type_filter preempt_type; struct kfd_process_device *pdd; - BUG_ON(!dqm); - retval = 0; if (lock) @@ -941,7 +885,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, if (!dqm->active_runlist) goto out; - pr_debug("kfd: Before destroying queues, sdma queue count is : %u\n", + pr_debug("Before destroying queues, sdma queue count is : %u\n", dqm->sdma_queue_count); if (dqm->sdma_queue_count > 0) { @@ -955,7 +899,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE, preempt_type, 0, false, 0); - if (retval != 0) + if (retval) goto out; *dqm->fence_addr = KFD_FENCE_INIT; @@ -964,7 +908,7 @@ static int destroy_queues_cpsch(struct device_queue_manager *dqm, /* should be timed out */ retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED, QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS); - if (retval != 0) { + if (retval) { pdd = kfd_get_process_device_data(dqm->dev, kfd_get_process(current)); pdd->reset_wavefronts = true; @@ -983,14 +927,12 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock) { int retval; - BUG_ON(!dqm); - if (lock) mutex_lock(&dqm->lock); retval = destroy_queues_cpsch(dqm, false, false); - if (retval != 0) { - pr_err("kfd: the cp might be in an unrecoverable state due to an unsuccessful queues preemption"); + if (retval) { + pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption"); goto out; } @@ -1005,8 +947,8 @@ static int execute_queues_cpsch(struct device_queue_manager *dqm, bool lock) } retval = pm_send_runlist(&dqm->packets, &dqm->queues); - if (retval != 0) { - pr_err("kfd: failed to execute runlist"); + if (retval) { + pr_err("failed to execute runlist"); goto out; } dqm->active_runlist = true; @@ -1025,8 +967,6 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, struct mqd_manager *mqd; bool preempt_all_queues; - BUG_ON(!dqm || !qpd || !q); - preempt_all_queues = false; retval = 0; @@ -1098,8 +1038,6 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, { bool retval; - pr_debug("kfd: In func %s\n", __func__); - mutex_lock(&dqm->lock); if (alternate_aperture_size == 0) { @@ -1120,14 +1058,11 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, uint64_t base = (uintptr_t)alternate_aperture_base; uint64_t limit = base + alternate_aperture_size - 1; - if (limit <= base) - goto out; - - if ((base & APE1_FIXED_BITS_MASK) != 0) - goto out; - - if ((limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) + if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || + (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { + retval = false; goto out; + } qpd->sh_mem_ape1_base = base >> 16; qpd->sh_mem_ape1_limit = limit >> 16; @@ -1144,27 +1079,22 @@ static bool set_cache_memory_policy(struct device_queue_manager *dqm, if ((sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0)) program_sh_mem_settings(dqm, qpd); - pr_debug("kfd: sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", + pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n", qpd->sh_mem_config, qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit); - mutex_unlock(&dqm->lock); - return retval; - out: mutex_unlock(&dqm->lock); - return false; + return retval; } struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) { struct device_queue_manager *dqm; - BUG_ON(!dev); + pr_debug("Loading device queue manager\n"); - pr_debug("kfd: loading device queue manager\n"); - - dqm = kzalloc(sizeof(struct device_queue_manager), GFP_KERNEL); + dqm = kzalloc(sizeof(*dqm), GFP_KERNEL); if (!dqm) return NULL; @@ -1202,8 +1132,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) dqm->ops.set_cache_memory_policy = set_cache_memory_policy; break; default: - BUG(); - break; + pr_err("Invalid scheduling policy %d\n", sched_policy); + goto out_free; } switch (dev->device_info->asic_family) { @@ -1216,18 +1146,16 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev) break; } - if (dqm->ops.initialize(dqm) != 0) { - kfree(dqm); - return NULL; - } + if (!dqm->ops.initialize(dqm)) + return dqm; - return dqm; +out_free: + kfree(dqm); + return NULL; } void device_queue_manager_uninit(struct device_queue_manager *dqm) { - BUG_ON(!dqm); - dqm->ops.uninitialize(dqm); kfree(dqm); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c index 48dc0561b402..72c3cbabc0a7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c @@ -24,6 +24,7 @@ #include "kfd_device_queue_manager.h" #include "cik_regs.h" #include "oss/oss_2_4_sh_mask.h" +#include "gca/gfx_7_2_sh_mask.h" static bool set_cache_memory_policy_cik(struct device_queue_manager *dqm, struct qcm_process_device *qpd, @@ -65,7 +66,7 @@ static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) * for LDS/Scratch and GPUVM. */ - BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || + WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || top_address_nybble == 0); return PRIVATE_BASE(top_address_nybble << 12) | @@ -104,8 +105,6 @@ static int register_process_cik(struct device_queue_manager *dqm, struct kfd_process_device *pdd; unsigned int temp; - BUG_ON(!dqm || !qpd); - pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ @@ -125,9 +124,10 @@ static int register_process_cik(struct device_queue_manager *dqm, } else { temp = get_sh_mem_bases_nybble_64(pdd); qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); + qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__PRIVATE_ATC__SHIFT; } - pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", + pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c index 7e9cae9d349b..40e9ddd096cd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c @@ -67,7 +67,7 @@ static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) * for LDS/Scratch and GPUVM. */ - BUG_ON((top_address_nybble & 1) || top_address_nybble > 0xE || + WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || top_address_nybble == 0); return top_address_nybble << 12 | @@ -110,8 +110,6 @@ static int register_process_vi(struct device_queue_manager *dqm, struct kfd_process_device *pdd; unsigned int temp; - BUG_ON(!dqm || !qpd); - pdd = qpd_to_pdd(qpd); /* check if sh_mem_config register already configured */ @@ -137,9 +135,11 @@ static int register_process_vi(struct device_queue_manager *dqm, qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); qpd->sh_mem_config |= SH_MEM_ADDRESS_MODE_HSA64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT; + qpd->sh_mem_config |= 1 << + SH_MEM_CONFIG__PRIVATE_ATC__SHIFT; } - pr_debug("kfd: is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", + pr_debug("is32bit process: %d sh_mem_bases nybble: 0x%X and register 0x%X\n", qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 453c5d66e5c3..acf4d2a977ad 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -59,7 +59,7 @@ static inline size_t doorbell_process_allocation(void) } /* Doorbell calculations for device init. */ -void kfd_doorbell_init(struct kfd_dev *kfd) +int kfd_doorbell_init(struct kfd_dev *kfd) { size_t doorbell_start_offset; size_t doorbell_aperture_size; @@ -95,26 +95,35 @@ void kfd_doorbell_init(struct kfd_dev *kfd) kfd->doorbell_kernel_ptr = ioremap(kfd->doorbell_base, doorbell_process_allocation()); - BUG_ON(!kfd->doorbell_kernel_ptr); + if (!kfd->doorbell_kernel_ptr) + return -ENOMEM; - pr_debug("kfd: doorbell initialization:\n"); - pr_debug("kfd: doorbell base == 0x%08lX\n", + pr_debug("Doorbell initialization:\n"); + pr_debug("doorbell base == 0x%08lX\n", (uintptr_t)kfd->doorbell_base); - pr_debug("kfd: doorbell_id_offset == 0x%08lX\n", + pr_debug("doorbell_id_offset == 0x%08lX\n", kfd->doorbell_id_offset); - pr_debug("kfd: doorbell_process_limit == 0x%08lX\n", + pr_debug("doorbell_process_limit == 0x%08lX\n", doorbell_process_limit); - pr_debug("kfd: doorbell_kernel_offset == 0x%08lX\n", + pr_debug("doorbell_kernel_offset == 0x%08lX\n", (uintptr_t)kfd->doorbell_base); - pr_debug("kfd: doorbell aperture size == 0x%08lX\n", + pr_debug("doorbell aperture size == 0x%08lX\n", kfd->shared_resources.doorbell_aperture_size); - pr_debug("kfd: doorbell kernel address == 0x%08lX\n", + pr_debug("doorbell kernel address == 0x%08lX\n", (uintptr_t)kfd->doorbell_kernel_ptr); + + return 0; +} + +void kfd_doorbell_fini(struct kfd_dev *kfd) +{ + if (kfd->doorbell_kernel_ptr) + iounmap(kfd->doorbell_kernel_ptr); } int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) @@ -131,7 +140,7 @@ int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) /* Find kfd device according to gpu id */ dev = kfd_device_by_id(vma->vm_pgoff); - if (dev == NULL) + if (!dev) return -EINVAL; /* Calculate physical address of doorbell */ @@ -142,12 +151,11 @@ int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("kfd: mapping doorbell page in %s\n" + pr_debug("Mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - __func__, (unsigned long long) vma->vm_start, address, vma->vm_flags, doorbell_process_allocation()); @@ -166,8 +174,6 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, { u32 inx; - BUG_ON(!kfd || !doorbell_off); - mutex_lock(&kfd->doorbell_mutex); inx = find_first_zero_bit(kfd->doorbell_available_index, KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); @@ -185,7 +191,7 @@ u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, *doorbell_off = KERNEL_DOORBELL_PASID * (doorbell_process_allocation() / sizeof(u32)) + inx; - pr_debug("kfd: get kernel queue doorbell\n" + pr_debug("Get kernel queue doorbell\n" " doorbell offset == 0x%08X\n" " kernel address == 0x%08lX\n", *doorbell_off, (uintptr_t)(kfd->doorbell_kernel_ptr + inx)); @@ -197,8 +203,6 @@ void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr) { unsigned int inx; - BUG_ON(!kfd || !db_addr); - inx = (unsigned int)(db_addr - kfd->doorbell_kernel_ptr); mutex_lock(&kfd->doorbell_mutex); @@ -210,7 +214,7 @@ inline void write_kernel_doorbell(u32 __iomem *db, u32 value) { if (db) { writel(value, db); - pr_debug("writing %d to doorbell address 0x%p\n", value, db); + pr_debug("Writing %d to doorbell address 0x%p\n", value, db); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index d1ce83d73a87..5979158c3f7b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -110,7 +110,7 @@ static bool allocate_free_slot(struct kfd_process *process, *out_page = page; *out_slot_index = slot; - pr_debug("allocated event signal slot in page %p, slot %d\n", + pr_debug("Allocated event signal slot in page %p, slot %d\n", page, slot); return true; @@ -155,9 +155,9 @@ static bool allocate_signal_page(struct file *devkfd, struct kfd_process *p) struct signal_page, event_pages)->page_index + 1; - pr_debug("allocated new event signal page at %p, for process %p\n", + pr_debug("Allocated new event signal page at %p, for process %p\n", page, p); - pr_debug("page index is %d\n", page->page_index); + pr_debug("Page index is %d\n", page->page_index); list_add(&page->event_pages, &p->signal_event_pages); @@ -194,7 +194,8 @@ static void release_event_notification_slot(struct signal_page *page, page->free_slots++; /* We don't free signal pages, they are retained by the process - * and reused until it exits. */ + * and reused until it exits. + */ } static struct signal_page *lookup_signal_page_by_index(struct kfd_process *p, @@ -246,7 +247,7 @@ static u32 make_nonsignal_event_id(struct kfd_process *p) for (id = p->next_nonsignal_event_id; id < KFD_LAST_NONSIGNAL_EVENT_ID && - lookup_event_by_id(p, id) != NULL; + lookup_event_by_id(p, id); id++) ; @@ -265,7 +266,7 @@ static u32 make_nonsignal_event_id(struct kfd_process *p) for (id = KFD_FIRST_NONSIGNAL_EVENT_ID; id < KFD_LAST_NONSIGNAL_EVENT_ID && - lookup_event_by_id(p, id) != NULL; + lookup_event_by_id(p, id); id++) ; @@ -291,13 +292,13 @@ static int create_signal_event(struct file *devkfd, struct kfd_event *ev) { if (p->signal_event_count == KFD_SIGNAL_EVENT_LIMIT) { - pr_warn("amdkfd: Signal event wasn't created because limit was reached\n"); + pr_warn("Signal event wasn't created because limit was reached\n"); return -ENOMEM; } if (!allocate_event_notification_slot(devkfd, p, &ev->signal_page, &ev->signal_slot_index)) { - pr_warn("amdkfd: Signal event wasn't created because out of kernel memory\n"); + pr_warn("Signal event wasn't created because out of kernel memory\n"); return -ENOMEM; } @@ -309,11 +310,7 @@ static int create_signal_event(struct file *devkfd, ev->event_id = make_signal_event_id(ev->signal_page, ev->signal_slot_index); - pr_debug("signal event number %zu created with id %d, address %p\n", - p->signal_event_count, ev->event_id, - ev->user_signal_address); - - pr_debug("signal event number %zu created with id %d, address %p\n", + pr_debug("Signal event number %zu created with id %d, address %p\n", p->signal_event_count, ev->event_id, ev->user_signal_address); @@ -345,7 +342,7 @@ void kfd_event_init_process(struct kfd_process *p) static void destroy_event(struct kfd_process *p, struct kfd_event *ev) { - if (ev->signal_page != NULL) { + if (ev->signal_page) { release_event_notification_slot(ev->signal_page, ev->signal_slot_index); p->signal_event_count--; @@ -584,7 +581,7 @@ void kfd_signal_event_interrupt(unsigned int pasid, uint32_t partial_id, * search faster. */ struct signal_page *page; - unsigned i; + unsigned int i; list_for_each_entry(page, &p->signal_event_pages, event_pages) for (i = 0; i < SLOTS_PER_PAGE; i++) @@ -816,7 +813,7 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) /* check required size is logical */ if (get_order(KFD_SIGNAL_EVENT_LIMIT * 8) != get_order(vma->vm_end - vma->vm_start)) { - pr_err("amdkfd: event page mmap requested illegal size\n"); + pr_err("Event page mmap requested illegal size\n"); return -EINVAL; } @@ -825,7 +822,7 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) page = lookup_signal_page_by_index(p, page_index); if (!page) { /* Probably KFD bug, but mmap is user-accessible. */ - pr_debug("signal page could not be found for page_index %u\n", + pr_debug("Signal page could not be found for page_index %u\n", page_index); return -EINVAL; } @@ -836,7 +833,7 @@ int kfd_event_mmap(struct kfd_process *p, struct vm_area_struct *vma) vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | VM_DONTDUMP | VM_PFNMAP; - pr_debug("mapping signal page\n"); + pr_debug("Mapping signal page\n"); pr_debug(" start user address == 0x%08lx\n", vma->vm_start); pr_debug(" end user address == 0x%08lx\n", vma->vm_end); pr_debug(" pfn == 0x%016lX\n", pfn); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index 2b655103ba79..c59384bbbc5f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -304,7 +304,7 @@ int kfd_init_apertures(struct kfd_process *process) id < NUM_OF_SUPPORTED_GPUS) { pdd = kfd_create_process_device_data(dev, process); - if (pdd == NULL) { + if (!pdd) { pr_err("Failed to create process device data\n"); return -1; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c index 7f134aa9bfd3..70b3a99cffc2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c @@ -179,7 +179,7 @@ static void interrupt_wq(struct work_struct *work) bool interrupt_is_wanted(struct kfd_dev *dev, const uint32_t *ih_ring_entry) { /* integer and bitwise OR so there is no boolean short-circuiting */ - unsigned wanted = 0; + unsigned int wanted = 0; wanted |= dev->device_info->event_interrupt_class->interrupt_isr(dev, ih_ring_entry); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index d135cd002a95..681b639f5133 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -41,11 +41,11 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, int retval; union PM4_MES_TYPE_3_HEADER nop; - BUG_ON(!kq || !dev); - BUG_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ); + if (WARN_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ)) + return false; - pr_debug("amdkfd: In func %s initializing queue type %d size %d\n", - __func__, KFD_QUEUE_TYPE_HIQ, queue_size); + pr_debug("Initializing queue type %d size %d\n", KFD_QUEUE_TYPE_HIQ, + queue_size); memset(&prop, 0, sizeof(prop)); memset(&nop, 0, sizeof(nop)); @@ -63,23 +63,23 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, KFD_MQD_TYPE_HIQ); break; default: - BUG(); - break; + pr_err("Invalid queue type %d\n", type); + return false; } - if (kq->mqd == NULL) + if (!kq->mqd) return false; prop.doorbell_ptr = kfd_get_kernel_doorbell(dev, &prop.doorbell_off); - if (prop.doorbell_ptr == NULL) { - pr_err("amdkfd: error init doorbell"); + if (!prop.doorbell_ptr) { + pr_err("Failed to initialize doorbell"); goto err_get_kernel_doorbell; } retval = kfd_gtt_sa_allocate(dev, queue_size, &kq->pq); if (retval != 0) { - pr_err("amdkfd: error init pq queues size (%d)\n", queue_size); + pr_err("Failed to init pq queues size %d\n", queue_size); goto err_pq_allocate_vidmem; } @@ -87,7 +87,7 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, kq->pq_gpu_addr = kq->pq->gpu_addr; retval = kq->ops_asic_specific.initialize(kq, dev, type, queue_size); - if (retval == false) + if (!retval) goto err_eop_allocate_vidmem; retval = kfd_gtt_sa_allocate(dev, sizeof(*kq->rptr_kernel), @@ -139,11 +139,12 @@ static bool initialize(struct kernel_queue *kq, struct kfd_dev *dev, /* assign HIQ to HQD */ if (type == KFD_QUEUE_TYPE_HIQ) { - pr_debug("assigning hiq to hqd\n"); + pr_debug("Assigning hiq to hqd\n"); kq->queue->pipe = KFD_CIK_HIQ_PIPE; kq->queue->queue = KFD_CIK_HIQ_QUEUE; kq->mqd->load_mqd(kq->mqd, kq->queue->mqd, kq->queue->pipe, - kq->queue->queue, NULL); + kq->queue->queue, &kq->queue->properties, + NULL); } else { /* allocate fence for DIQ */ @@ -180,8 +181,6 @@ err_get_kernel_doorbell: static void uninitialize(struct kernel_queue *kq) { - BUG_ON(!kq); - if (kq->queue->properties.type == KFD_QUEUE_TYPE_HIQ) kq->mqd->destroy_mqd(kq->mqd, NULL, @@ -211,8 +210,6 @@ static int acquire_packet_buffer(struct kernel_queue *kq, uint32_t wptr, rptr; unsigned int *queue_address; - BUG_ON(!kq || !buffer_ptr); - rptr = *kq->rptr_kernel; wptr = *kq->wptr_kernel; queue_address = (unsigned int *)kq->pq_kernel_addr; @@ -252,11 +249,7 @@ static void submit_packet(struct kernel_queue *kq) { #ifdef DEBUG int i; -#endif - - BUG_ON(!kq); -#ifdef DEBUG for (i = *kq->wptr_kernel; i < kq->pending_wptr; i++) { pr_debug("0x%2X ", kq->pq_kernel_addr[i]); if (i % 15 == 0) @@ -272,7 +265,6 @@ static void submit_packet(struct kernel_queue *kq) static void rollback_packet(struct kernel_queue *kq) { - BUG_ON(!kq); kq->pending_wptr = *kq->queue->properties.write_ptr; } @@ -281,9 +273,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, { struct kernel_queue *kq; - BUG_ON(!dev); - - kq = kzalloc(sizeof(struct kernel_queue), GFP_KERNEL); + kq = kzalloc(sizeof(*kq), GFP_KERNEL); if (!kq) return NULL; @@ -304,7 +294,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, } if (!kq->ops.initialize(kq, dev, type, KFD_KERNEL_QUEUE_SIZE)) { - pr_err("amdkfd: failed to init kernel queue\n"); + pr_err("Failed to init kernel queue\n"); kfree(kq); return NULL; } @@ -313,32 +303,37 @@ struct kernel_queue *kernel_queue_init(struct kfd_dev *dev, void kernel_queue_uninit(struct kernel_queue *kq) { - BUG_ON(!kq); - kq->ops.uninitialize(kq); kfree(kq); } +/* FIXME: Can this test be removed? */ static __attribute__((unused)) void test_kq(struct kfd_dev *dev) { struct kernel_queue *kq; uint32_t *buffer, i; int retval; - BUG_ON(!dev); - - pr_err("amdkfd: starting kernel queue test\n"); + pr_err("Starting kernel queue test\n"); kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); - BUG_ON(!kq); + if (unlikely(!kq)) { + pr_err(" Failed to initialize HIQ\n"); + pr_err("Kernel queue test failed\n"); + return; + } retval = kq->ops.acquire_packet_buffer(kq, 5, &buffer); - BUG_ON(retval != 0); + if (unlikely(retval != 0)) { + pr_err(" Failed to acquire packet buffer\n"); + pr_err("Kernel queue test failed\n"); + return; + } for (i = 0; i < 5; i++) buffer[i] = kq->nop_packet; kq->ops.submit_packet(kq); - pr_err("amdkfd: ending kernel queue test\n"); + pr_err("Ending kernel queue test\n"); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 850a5623661f..0d73bea22c45 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -61,7 +61,8 @@ MODULE_PARM_DESC(send_sigterm, static int amdkfd_init_completed; -int kgd2kfd_init(unsigned interface_version, const struct kgd2kfd_calls **g2f) +int kgd2kfd_init(unsigned int interface_version, + const struct kgd2kfd_calls **g2f) { if (!amdkfd_init_completed) return -EPROBE_DEFER; @@ -90,7 +91,7 @@ static int __init kfd_module_init(void) /* Verify module parameters */ if ((sched_policy < KFD_SCHED_POLICY_HWS) || (sched_policy > KFD_SCHED_POLICY_NO_HWS)) { - pr_err("kfd: sched_policy has invalid value\n"); + pr_err("sched_policy has invalid value\n"); return -1; } @@ -98,13 +99,13 @@ static int __init kfd_module_init(void) if ((max_num_of_queues_per_device < 1) || (max_num_of_queues_per_device > KFD_MAX_NUM_OF_QUEUES_PER_DEVICE)) { - pr_err("kfd: max_num_of_queues_per_device must be between 1 to KFD_MAX_NUM_OF_QUEUES_PER_DEVICE\n"); + pr_err("max_num_of_queues_per_device must be between 1 to KFD_MAX_NUM_OF_QUEUES_PER_DEVICE\n"); return -1; } err = kfd_pasid_init(); if (err < 0) - goto err_pasid; + return err; err = kfd_chardev_init(); if (err < 0) @@ -126,7 +127,6 @@ err_topology: kfd_chardev_exit(); err_ioctl: kfd_pasid_exit(); -err_pasid: return err; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 213a71e0b6c7..1f3a6ba7eed2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -67,7 +67,8 @@ struct mqd_manager { int (*load_mqd)(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr); + struct queue_properties *p, + struct mm_struct *mms); int (*update_mqd)(struct mqd_manager *mm, void *mqd, struct queue_properties *q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 6acc4313363e..44ffd23348fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -44,10 +44,6 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, struct cik_mqd *m; int retval; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), mqd_mem_obj); @@ -101,7 +97,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_iq_rptr = AQL_ENABLE; *mqd = m; - if (gart_addr != NULL) + if (gart_addr) *gart_addr = addr; retval = mm->update_mqd(mm, m, q); @@ -115,8 +111,6 @@ static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, int retval; struct cik_sdma_rlc_registers *m; - BUG_ON(!mm || !mqd || !mqd_mem_obj); - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_sdma_rlc_registers), mqd_mem_obj); @@ -129,7 +123,7 @@ static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); *mqd = m; - if (gart_addr != NULL) + if (gart_addr) *gart_addr = (*mqd_mem_obj)->gpu_addr; retval = mm->update_mqd(mm, m, q); @@ -140,27 +134,31 @@ static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, static void uninit_mqd(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - BUG_ON(!mm || !mqd); kfd_gtt_sa_free(mm->dev, mqd_mem_obj); } static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - BUG_ON(!mm || !mqd); kfd_gtt_sa_free(mm->dev, mqd_mem_obj); } static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, struct queue_properties *p, + struct mm_struct *mms) { - return mm->dev->kfd2kgd->hqd_load - (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); + /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ + uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); + uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); + + return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, + (uint32_t __user *)p->write_ptr, + wptr_shift, wptr_mask, mms); } static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, - uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr) + uint32_t pipe_id, uint32_t queue_id, + struct queue_properties *p, struct mm_struct *mms) { return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd); } @@ -170,10 +168,6 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, { struct cik_mqd *m; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - m = get_mqd(mqd); m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | DEFAULT_MIN_AVAIL_SIZE | PQ_ATC_EN; @@ -188,21 +182,17 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); - m->cp_hqd_pq_doorbell_control = DOORBELL_EN | - DOORBELL_OFFSET(q->doorbell_off); + m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); m->cp_hqd_vmid = q->vmid; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_pq_control |= NO_UPDATE_RPTR; - } - m->cp_hqd_active = 0; q->is_active = false; if (q->queue_size > 0 && q->queue_address != 0 && q->queue_percent > 0) { - m->cp_hqd_active = 1; q->is_active = true; } @@ -214,8 +204,6 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, { struct cik_sdma_rlc_registers *m; - BUG_ON(!mm || !mqd || !q); - m = get_sdma_mqd(mqd); m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | @@ -254,7 +242,7 @@ static int destroy_mqd(struct mqd_manager *mm, void *mqd, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id) { - return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, type, timeout, + return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout, pipe_id, queue_id); } @@ -301,10 +289,6 @@ static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, struct cik_mqd *m; int retval; - BUG_ON(!mm || !q || !mqd || !mqd_mem_obj); - - pr_debug("kfd: In func %s\n", __func__); - retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct cik_mqd), mqd_mem_obj); @@ -359,10 +343,6 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, { struct cik_mqd *m; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - m = get_mqd(mqd); m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | DEFAULT_MIN_AVAIL_SIZE | @@ -400,8 +380,6 @@ struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) { struct cik_sdma_rlc_registers *m; - BUG_ON(!mqd); - m = (struct cik_sdma_rlc_registers *)mqd; return m; @@ -412,12 +390,10 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, { struct mqd_manager *mqd; - BUG_ON(!dev); - BUG_ON(type >= KFD_MQD_TYPE_MAX); - - pr_debug("kfd: In func %s\n", __func__); + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; - mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL); + mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); if (!mqd) return NULL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index a9b9882a9a77..73cbfe186dd2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -85,7 +85,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_iq_rptr = 1; *mqd = m; - if (gart_addr != NULL) + if (gart_addr) *gart_addr = addr; retval = mm->update_mqd(mm, m, q); @@ -94,10 +94,15 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, - uint32_t __user *wptr) + struct queue_properties *p, struct mm_struct *mms) { - return mm->dev->kfd2kgd->hqd_load - (mm->dev->kgd, mqd, pipe_id, queue_id, wptr); + /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ + uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); + uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1); + + return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, + (uint32_t __user *)p->write_ptr, + wptr_shift, wptr_mask, mms); } static int __update_mqd(struct mqd_manager *mm, void *mqd, @@ -106,10 +111,6 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, { struct vi_mqd *m; - BUG_ON(!mm || !q || !mqd); - - pr_debug("kfd: In func %s\n", __func__); - m = get_mqd(mqd); m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | @@ -117,7 +118,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; - pr_debug("kfd: cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); + pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); @@ -126,10 +127,9 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); m->cp_hqd_pq_doorbell_control = - 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT | q->doorbell_off << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; - pr_debug("kfd: cp_hqd_pq_doorbell_control 0x%x\n", + pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", m->cp_hqd_pq_doorbell_control); m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT | @@ -139,8 +139,15 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT; - m->cp_hqd_eop_control |= - ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1; + /* + * HW does not clamp this field correctly. Maximum EOP queue size + * is constrained by per-SE EOP done signal count, which is 8-bit. + * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit + * more than (EOP entry count - 1) so a queue size of 0x800 dwords + * is safe, giving a maximum field value of 0xA. + */ + m->cp_hqd_eop_control |= min(0xA, + ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); m->cp_hqd_eop_base_addr_lo = lower_32_bits(q->eop_ring_buffer_address >> 8); m->cp_hqd_eop_base_addr_hi = @@ -156,12 +163,10 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } - m->cp_hqd_active = 0; q->is_active = false; if (q->queue_size > 0 && q->queue_address != 0 && q->queue_percent > 0) { - m->cp_hqd_active = 1; q->is_active = true; } @@ -181,14 +186,13 @@ static int destroy_mqd(struct mqd_manager *mm, void *mqd, uint32_t queue_id) { return mm->dev->kfd2kgd->hqd_destroy - (mm->dev->kgd, type, timeout, + (mm->dev->kgd, mqd, type, timeout, pipe_id, queue_id); } static void uninit_mqd(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - BUG_ON(!mm || !mqd); kfd_gtt_sa_free(mm->dev, mqd_mem_obj); } @@ -238,12 +242,10 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, { struct mqd_manager *mqd; - BUG_ON(!dev); - BUG_ON(type >= KFD_MQD_TYPE_MAX); - - pr_debug("kfd: In func %s\n", __func__); + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; - mqd = kzalloc(sizeof(struct mqd_manager), GFP_KERNEL); + mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); if (!mqd) return NULL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 7131998848d7..1d312603de9f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -26,7 +26,6 @@ #include "kfd_device_queue_manager.h" #include "kfd_kernel_queue.h" #include "kfd_priv.h" -#include "kfd_pm4_headers.h" #include "kfd_pm4_headers_vi.h" #include "kfd_pm4_opcodes.h" @@ -35,7 +34,8 @@ static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes, { unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); - BUG_ON((temp * sizeof(uint32_t)) > buffer_size_bytes); + WARN((temp * sizeof(uint32_t)) > buffer_size_bytes, + "Runlist IB overflow"); *wptr = temp; } @@ -43,12 +43,12 @@ static unsigned int build_pm4_header(unsigned int opcode, size_t packet_size) { union PM4_MES_TYPE_3_HEADER header; - header.u32all = 0; + header.u32All = 0; header.opcode = opcode; header.count = packet_size/sizeof(uint32_t) - 2; header.type = PM4_TYPE_3; - return header.u32all; + return header.u32All; } static void pm_calc_rlib_size(struct packet_manager *pm, @@ -58,8 +58,6 @@ static void pm_calc_rlib_size(struct packet_manager *pm, unsigned int process_count, queue_count; unsigned int map_queue_size; - BUG_ON(!pm || !rlib_size || !over_subscription); - process_count = pm->dqm->processes_count; queue_count = pm->dqm->queue_count; @@ -67,15 +65,12 @@ static void pm_calc_rlib_size(struct packet_manager *pm, *over_subscription = false; if ((process_count > 1) || queue_count > get_queues_num(pm->dqm)) { *over_subscription = true; - pr_debug("kfd: over subscribed runlist\n"); + pr_debug("Over subscribed runlist\n"); } - map_queue_size = - (pm->dqm->dev->device_info->asic_family == CHIP_CARRIZO) ? - sizeof(struct pm4_mes_map_queues) : - sizeof(struct pm4_map_queues); + map_queue_size = sizeof(struct pm4_mes_map_queues); /* calculate run list ib allocation size */ - *rlib_size = process_count * sizeof(struct pm4_map_process) + + *rlib_size = process_count * sizeof(struct pm4_mes_map_process) + queue_count * map_queue_size; /* @@ -83,9 +78,9 @@ static void pm_calc_rlib_size(struct packet_manager *pm, * when over subscription */ if (*over_subscription) - *rlib_size += sizeof(struct pm4_runlist); + *rlib_size += sizeof(struct pm4_mes_runlist); - pr_debug("kfd: runlist ib size %d\n", *rlib_size); + pr_debug("runlist ib size %d\n", *rlib_size); } static int pm_allocate_runlist_ib(struct packet_manager *pm, @@ -96,17 +91,16 @@ static int pm_allocate_runlist_ib(struct packet_manager *pm, { int retval; - BUG_ON(!pm); - BUG_ON(pm->allocated); - BUG_ON(is_over_subscription == NULL); + if (WARN_ON(pm->allocated)) + return -EINVAL; pm_calc_rlib_size(pm, rl_buffer_size, is_over_subscription); retval = kfd_gtt_sa_allocate(pm->dqm->dev, *rl_buffer_size, &pm->ib_buffer_obj); - if (retval != 0) { - pr_err("kfd: failed to allocate runlist IB\n"); + if (retval) { + pr_err("Failed to allocate runlist IB\n"); return retval; } @@ -121,15 +115,16 @@ static int pm_allocate_runlist_ib(struct packet_manager *pm, static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, uint64_t ib, size_t ib_size_in_dwords, bool chain) { - struct pm4_runlist *packet; + struct pm4_mes_runlist *packet; - BUG_ON(!pm || !buffer || !ib); + if (WARN_ON(!ib)) + return -EFAULT; - packet = (struct pm4_runlist *)buffer; + packet = (struct pm4_mes_runlist *)buffer; - memset(buffer, 0, sizeof(struct pm4_runlist)); - packet->header.u32all = build_pm4_header(IT_RUN_LIST, - sizeof(struct pm4_runlist)); + memset(buffer, 0, sizeof(struct pm4_mes_runlist)); + packet->header.u32All = build_pm4_header(IT_RUN_LIST, + sizeof(struct pm4_mes_runlist)); packet->bitfields4.ib_size = ib_size_in_dwords; packet->bitfields4.chain = chain ? 1 : 0; @@ -144,20 +139,16 @@ static int pm_create_runlist(struct packet_manager *pm, uint32_t *buffer, static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, struct qcm_process_device *qpd) { - struct pm4_map_process *packet; + struct pm4_mes_map_process *packet; struct queue *cur; uint32_t num_queues; - BUG_ON(!pm || !buffer || !qpd); - - packet = (struct pm4_map_process *)buffer; - - pr_debug("kfd: In func %s\n", __func__); + packet = (struct pm4_mes_map_process *)buffer; - memset(buffer, 0, sizeof(struct pm4_map_process)); + memset(buffer, 0, sizeof(struct pm4_mes_map_process)); - packet->header.u32all = build_pm4_header(IT_MAP_PROCESS, - sizeof(struct pm4_map_process)); + packet->header.u32All = build_pm4_header(IT_MAP_PROCESS, + sizeof(struct pm4_mes_map_process)); packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; packet->bitfields2.process_quantum = 1; packet->bitfields2.pasid = qpd->pqm->process->pasid; @@ -175,27 +166,26 @@ static int pm_create_map_process(struct packet_manager *pm, uint32_t *buffer, packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base; packet->sh_mem_ape1_limit = qpd->sh_mem_ape1_limit; + /* TODO: scratch support */ + packet->sh_hidden_private_base_vmid = 0; + packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); return 0; } -static int pm_create_map_queue_vi(struct packet_manager *pm, uint32_t *buffer, +static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, struct queue *q, bool is_static) { struct pm4_mes_map_queues *packet; bool use_static = is_static; - BUG_ON(!pm || !buffer || !q); - - pr_debug("kfd: In func %s\n", __func__); - packet = (struct pm4_mes_map_queues *)buffer; - memset(buffer, 0, sizeof(struct pm4_map_queues)); + memset(buffer, 0, sizeof(struct pm4_mes_map_queues)); - packet->header.u32all = build_pm4_header(IT_MAP_QUEUES, - sizeof(struct pm4_map_queues)); + packet->header.u32All = build_pm4_header(IT_MAP_QUEUES, + sizeof(struct pm4_mes_map_queues)); packet->bitfields2.alloc_format = alloc_format__mes_map_queues__one_per_pipe_vi; packet->bitfields2.num_queues = 1; @@ -223,10 +213,8 @@ static int pm_create_map_queue_vi(struct packet_manager *pm, uint32_t *buffer, use_static = false; /* no static queues under SDMA */ break; default: - pr_err("kfd: in %s queue type %d\n", __func__, - q->properties.type); - BUG(); - break; + WARN(1, "queue type %d", q->properties.type); + return -EINVAL; } packet->bitfields3.doorbell_offset = q->properties.doorbell_off; @@ -246,68 +234,6 @@ static int pm_create_map_queue_vi(struct packet_manager *pm, uint32_t *buffer, return 0; } -static int pm_create_map_queue(struct packet_manager *pm, uint32_t *buffer, - struct queue *q, bool is_static) -{ - struct pm4_map_queues *packet; - bool use_static = is_static; - - BUG_ON(!pm || !buffer || !q); - - pr_debug("kfd: In func %s\n", __func__); - - packet = (struct pm4_map_queues *)buffer; - memset(buffer, 0, sizeof(struct pm4_map_queues)); - - packet->header.u32all = build_pm4_header(IT_MAP_QUEUES, - sizeof(struct pm4_map_queues)); - packet->bitfields2.alloc_format = - alloc_format__mes_map_queues__one_per_pipe; - packet->bitfields2.num_queues = 1; - packet->bitfields2.queue_sel = - queue_sel__mes_map_queues__map_to_hws_determined_queue_slots; - - packet->bitfields2.vidmem = (q->properties.is_interop) ? - vidmem__mes_map_queues__uses_video_memory : - vidmem__mes_map_queues__uses_no_video_memory; - - switch (q->properties.type) { - case KFD_QUEUE_TYPE_COMPUTE: - case KFD_QUEUE_TYPE_DIQ: - packet->bitfields2.engine_sel = - engine_sel__mes_map_queues__compute; - break; - case KFD_QUEUE_TYPE_SDMA: - packet->bitfields2.engine_sel = - engine_sel__mes_map_queues__sdma0; - use_static = false; /* no static queues under SDMA */ - break; - default: - BUG(); - break; - } - - packet->mes_map_queues_ordinals[0].bitfields3.doorbell_offset = - q->properties.doorbell_off; - - packet->mes_map_queues_ordinals[0].bitfields3.is_static = - (use_static) ? 1 : 0; - - packet->mes_map_queues_ordinals[0].mqd_addr_lo = - lower_32_bits(q->gart_mqd_addr); - - packet->mes_map_queues_ordinals[0].mqd_addr_hi = - upper_32_bits(q->gart_mqd_addr); - - packet->mes_map_queues_ordinals[0].wptr_addr_lo = - lower_32_bits((uint64_t)q->properties.write_ptr); - - packet->mes_map_queues_ordinals[0].wptr_addr_hi = - upper_32_bits((uint64_t)q->properties.write_ptr); - - return 0; -} - static int pm_create_runlist_ib(struct packet_manager *pm, struct list_head *queues, uint64_t *rl_gpu_addr, @@ -322,19 +248,16 @@ static int pm_create_runlist_ib(struct packet_manager *pm, struct kernel_queue *kq; bool is_over_subscription; - BUG_ON(!pm || !queues || !rl_size_bytes || !rl_gpu_addr); - rl_wptr = retval = proccesses_mapped = 0; retval = pm_allocate_runlist_ib(pm, &rl_buffer, rl_gpu_addr, &alloc_size_bytes, &is_over_subscription); - if (retval != 0) + if (retval) return retval; *rl_size_bytes = alloc_size_bytes; - pr_debug("kfd: In func %s\n", __func__); - pr_debug("kfd: building runlist ib process count: %d queues count %d\n", + pr_debug("Building runlist ib process count: %d queues count %d\n", pm->dqm->processes_count, pm->dqm->queue_count); /* build the run list ib packet */ @@ -342,42 +265,35 @@ static int pm_create_runlist_ib(struct packet_manager *pm, qpd = cur->qpd; /* build map process packet */ if (proccesses_mapped >= pm->dqm->processes_count) { - pr_debug("kfd: not enough space left in runlist IB\n"); + pr_debug("Not enough space left in runlist IB\n"); pm_release_ib(pm); return -ENOMEM; } retval = pm_create_map_process(pm, &rl_buffer[rl_wptr], qpd); - if (retval != 0) + if (retval) return retval; proccesses_mapped++; - inc_wptr(&rl_wptr, sizeof(struct pm4_map_process), + inc_wptr(&rl_wptr, sizeof(struct pm4_mes_map_process), alloc_size_bytes); list_for_each_entry(kq, &qpd->priv_queue_list, list) { if (!kq->queue->properties.is_active) continue; - pr_debug("kfd: static_queue, mapping kernel q %d, is debug status %d\n", + pr_debug("static_queue, mapping kernel q %d, is debug status %d\n", kq->queue->queue, qpd->is_debug); - if (pm->dqm->dev->device_info->asic_family == - CHIP_CARRIZO) - retval = pm_create_map_queue_vi(pm, - &rl_buffer[rl_wptr], - kq->queue, - qpd->is_debug); - else - retval = pm_create_map_queue(pm, + retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], kq->queue, qpd->is_debug); - if (retval != 0) + if (retval) return retval; inc_wptr(&rl_wptr, - sizeof(struct pm4_map_queues), + sizeof(struct pm4_mes_map_queues), alloc_size_bytes); } @@ -385,51 +301,44 @@ static int pm_create_runlist_ib(struct packet_manager *pm, if (!q->properties.is_active) continue; - pr_debug("kfd: static_queue, mapping user queue %d, is debug status %d\n", + pr_debug("static_queue, mapping user queue %d, is debug status %d\n", q->queue, qpd->is_debug); - if (pm->dqm->dev->device_info->asic_family == - CHIP_CARRIZO) - retval = pm_create_map_queue_vi(pm, - &rl_buffer[rl_wptr], - q, - qpd->is_debug); - else - retval = pm_create_map_queue(pm, + retval = pm_create_map_queue(pm, &rl_buffer[rl_wptr], q, qpd->is_debug); - if (retval != 0) + if (retval) return retval; inc_wptr(&rl_wptr, - sizeof(struct pm4_map_queues), + sizeof(struct pm4_mes_map_queues), alloc_size_bytes); } } - pr_debug("kfd: finished map process and queues to runlist\n"); + pr_debug("Finished map process and queues to runlist\n"); if (is_over_subscription) - pm_create_runlist(pm, &rl_buffer[rl_wptr], *rl_gpu_addr, - alloc_size_bytes / sizeof(uint32_t), true); + retval = pm_create_runlist(pm, &rl_buffer[rl_wptr], + *rl_gpu_addr, + alloc_size_bytes / sizeof(uint32_t), + true); for (i = 0; i < alloc_size_bytes / sizeof(uint32_t); i++) pr_debug("0x%2X ", rl_buffer[i]); pr_debug("\n"); - return 0; + return retval; } int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) { - BUG_ON(!dqm); - pm->dqm = dqm; mutex_init(&pm->lock); pm->priv_queue = kernel_queue_init(dqm->dev, KFD_QUEUE_TYPE_HIQ); - if (pm->priv_queue == NULL) { + if (!pm->priv_queue) { mutex_destroy(&pm->lock); return -ENOMEM; } @@ -440,8 +349,6 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm) void pm_uninit(struct packet_manager *pm) { - BUG_ON(!pm); - mutex_destroy(&pm->lock); kernel_queue_uninit(pm->priv_queue); } @@ -449,25 +356,22 @@ void pm_uninit(struct packet_manager *pm) int pm_send_set_resources(struct packet_manager *pm, struct scheduling_resources *res) { - struct pm4_set_resources *packet; - - BUG_ON(!pm || !res); - - pr_debug("kfd: In func %s\n", __func__); + struct pm4_mes_set_resources *packet; + int retval = 0; mutex_lock(&pm->lock); pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, sizeof(*packet) / sizeof(uint32_t), - (unsigned int **)&packet); - if (packet == NULL) { - mutex_unlock(&pm->lock); - pr_err("kfd: failed to allocate buffer on kernel queue\n"); - return -ENOMEM; + (unsigned int **)&packet); + if (!packet) { + pr_err("Failed to allocate buffer on kernel queue\n"); + retval = -ENOMEM; + goto out; } - memset(packet, 0, sizeof(struct pm4_set_resources)); - packet->header.u32all = build_pm4_header(IT_SET_RESOURCES, - sizeof(struct pm4_set_resources)); + memset(packet, 0, sizeof(struct pm4_mes_set_resources)); + packet->header.u32All = build_pm4_header(IT_SET_RESOURCES, + sizeof(struct pm4_mes_set_resources)); packet->bitfields2.queue_type = queue_type__mes_set_resources__hsa_interface_queue_hiq; @@ -485,9 +389,10 @@ int pm_send_set_resources(struct packet_manager *pm, pm->priv_queue->ops.submit_packet(pm->priv_queue); +out: mutex_unlock(&pm->lock); - return 0; + return retval; } int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) @@ -497,26 +402,24 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) size_t rl_ib_size, packet_size_dwords; int retval; - BUG_ON(!pm || !dqm_queues); - retval = pm_create_runlist_ib(pm, dqm_queues, &rl_gpu_ib_addr, &rl_ib_size); - if (retval != 0) + if (retval) goto fail_create_runlist_ib; - pr_debug("kfd: runlist IB address: 0x%llX\n", rl_gpu_ib_addr); + pr_debug("runlist IB address: 0x%llX\n", rl_gpu_ib_addr); - packet_size_dwords = sizeof(struct pm4_runlist) / sizeof(uint32_t); + packet_size_dwords = sizeof(struct pm4_mes_runlist) / sizeof(uint32_t); mutex_lock(&pm->lock); retval = pm->priv_queue->ops.acquire_packet_buffer(pm->priv_queue, packet_size_dwords, &rl_buffer); - if (retval != 0) + if (retval) goto fail_acquire_packet_buffer; retval = pm_create_runlist(pm, rl_buffer, rl_gpu_ib_addr, rl_ib_size / sizeof(uint32_t), false); - if (retval != 0) + if (retval) goto fail_create_runlist; pm->priv_queue->ops.submit_packet(pm->priv_queue); @@ -530,8 +433,7 @@ fail_create_runlist: fail_acquire_packet_buffer: mutex_unlock(&pm->lock); fail_create_runlist_ib: - if (pm->allocated) - pm_release_ib(pm); + pm_release_ib(pm); return retval; } @@ -539,20 +441,21 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, uint32_t fence_value) { int retval; - struct pm4_query_status *packet; + struct pm4_mes_query_status *packet; - BUG_ON(!pm || !fence_address); + if (WARN_ON(!fence_address)) + return -EFAULT; mutex_lock(&pm->lock); retval = pm->priv_queue->ops.acquire_packet_buffer( pm->priv_queue, - sizeof(struct pm4_query_status) / sizeof(uint32_t), + sizeof(struct pm4_mes_query_status) / sizeof(uint32_t), (unsigned int **)&packet); - if (retval != 0) + if (retval) goto fail_acquire_packet_buffer; - packet->header.u32all = build_pm4_header(IT_QUERY_STATUS, - sizeof(struct pm4_query_status)); + packet->header.u32All = build_pm4_header(IT_QUERY_STATUS, + sizeof(struct pm4_mes_query_status)); packet->bitfields2.context_id = 0; packet->bitfields2.interrupt_sel = @@ -566,9 +469,6 @@ int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, packet->data_lo = lower_32_bits((uint64_t)fence_value); pm->priv_queue->ops.submit_packet(pm->priv_queue); - mutex_unlock(&pm->lock); - - return 0; fail_acquire_packet_buffer: mutex_unlock(&pm->lock); @@ -582,24 +482,22 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, { int retval; uint32_t *buffer; - struct pm4_unmap_queues *packet; - - BUG_ON(!pm); + struct pm4_mes_unmap_queues *packet; mutex_lock(&pm->lock); retval = pm->priv_queue->ops.acquire_packet_buffer( pm->priv_queue, - sizeof(struct pm4_unmap_queues) / sizeof(uint32_t), + sizeof(struct pm4_mes_unmap_queues) / sizeof(uint32_t), &buffer); - if (retval != 0) + if (retval) goto err_acquire_packet_buffer; - packet = (struct pm4_unmap_queues *)buffer; - memset(buffer, 0, sizeof(struct pm4_unmap_queues)); - pr_debug("kfd: static_queue: unmapping queues: mode is %d , reset is %d , type is %d\n", + packet = (struct pm4_mes_unmap_queues *)buffer; + memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues)); + pr_debug("static_queue: unmapping queues: mode is %d , reset is %d , type is %d\n", mode, reset, type); - packet->header.u32all = build_pm4_header(IT_UNMAP_QUEUES, - sizeof(struct pm4_unmap_queues)); + packet->header.u32All = build_pm4_header(IT_UNMAP_QUEUES, + sizeof(struct pm4_mes_unmap_queues)); switch (type) { case KFD_QUEUE_TYPE_COMPUTE: case KFD_QUEUE_TYPE_DIQ: @@ -611,8 +509,9 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, engine_sel__mes_unmap_queues__sdma0 + sdma_engine; break; default: - BUG(); - break; + WARN(1, "queue type %d", type); + retval = -EINVAL; + goto err_invalid; } if (reset) @@ -636,16 +535,17 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, break; case KFD_PREEMPT_TYPE_FILTER_ALL_QUEUES: packet->bitfields2.queue_sel = - queue_sel__mes_unmap_queues__perform_request_on_all_active_queues; + queue_sel__mes_unmap_queues__unmap_all_queues; break; case KFD_PREEMPT_TYPE_FILTER_DYNAMIC_QUEUES: /* in this case, we do not preempt static queues */ packet->bitfields2.queue_sel = - queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only; + queue_sel__mes_unmap_queues__unmap_all_non_static_queues; break; default: - BUG(); - break; + WARN(1, "filter %d", mode); + retval = -EINVAL; + goto err_invalid; } pm->priv_queue->ops.submit_packet(pm->priv_queue); @@ -653,6 +553,8 @@ int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, mutex_unlock(&pm->lock); return 0; +err_invalid: + pm->priv_queue->ops.rollback_packet(pm->priv_queue); err_acquire_packet_buffer: mutex_unlock(&pm->lock); return retval; @@ -660,8 +562,6 @@ err_acquire_packet_buffer: void pm_release_ib(struct packet_manager *pm) { - BUG_ON(!pm); - mutex_lock(&pm->lock); if (pm->allocated) { kfd_gtt_sa_free(pm->dqm->dev, pm->ib_buffer_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c index 6cfe7f1f18cf..1e06de0bc673 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pasid.c @@ -32,7 +32,8 @@ int kfd_pasid_init(void) { pasid_limit = KFD_MAX_NUM_OF_PROCESSES; - pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long), GFP_KERNEL); + pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long), + GFP_KERNEL); if (!pasid_bitmap) return -ENOMEM; @@ -91,6 +92,6 @@ unsigned int kfd_pasid_alloc(void) void kfd_pasid_free(unsigned int pasid) { - BUG_ON(pasid == 0 || pasid >= pasid_limit); - clear_bit(pasid, pasid_bitmap); + if (!WARN_ON(pasid == 0 || pasid >= pasid_limit)) + clear_bit(pasid, pasid_bitmap); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h index 5b393f3e34a9..e50f73d25de6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h @@ -28,112 +28,19 @@ #define PM4_MES_HEADER_DEFINED union PM4_MES_TYPE_3_HEADER { struct { - uint32_t reserved1:8; /* < reserved */ - uint32_t opcode:8; /* < IT opcode */ - uint32_t count:14; /* < number of DWORDs - 1 - * in the information body. - */ - uint32_t type:2; /* < packet identifier. - * It should be 3 for type 3 packets - */ + /* reserved */ + uint32_t reserved1:8; + /* IT opcode */ + uint32_t opcode:8; + /* number of DWORDs - 1 in the information body */ + uint32_t count:14; + /* packet identifier. It should be 3 for type 3 packets */ + uint32_t type:2; }; uint32_t u32all; }; #endif /* PM4_MES_HEADER_DEFINED */ -/* --------------------MES_SET_RESOURCES-------------------- */ - -#ifndef PM4_MES_SET_RESOURCES_DEFINED -#define PM4_MES_SET_RESOURCES_DEFINED -enum set_resources_queue_type_enum { - queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, - queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, - queue_type__mes_set_resources__hsa_debug_interface_queue = 4 -}; - -struct pm4_set_resources { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t vmid_mask:16; - uint32_t unmap_latency:8; - uint32_t reserved1:5; - enum set_resources_queue_type_enum queue_type:3; - } bitfields2; - uint32_t ordinal2; - }; - - uint32_t queue_mask_lo; - uint32_t queue_mask_hi; - uint32_t gws_mask_lo; - uint32_t gws_mask_hi; - - union { - struct { - uint32_t oac_mask:16; - uint32_t reserved2:16; - } bitfields7; - uint32_t ordinal7; - }; - - union { - struct { - uint32_t gds_heap_base:6; - uint32_t reserved3:5; - uint32_t gds_heap_size:6; - uint32_t reserved4:15; - } bitfields8; - uint32_t ordinal8; - }; - -}; -#endif - -/*--------------------MES_RUN_LIST-------------------- */ - -#ifndef PM4_MES_RUN_LIST_DEFINED -#define PM4_MES_RUN_LIST_DEFINED - -struct pm4_runlist { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t reserved1:2; - uint32_t ib_base_lo:30; - } bitfields2; - uint32_t ordinal2; - }; - - union { - struct { - uint32_t ib_base_hi:16; - uint32_t reserved2:16; - } bitfields3; - uint32_t ordinal3; - }; - - union { - struct { - uint32_t ib_size:20; - uint32_t chain:1; - uint32_t offload_polling:1; - uint32_t reserved3:1; - uint32_t valid:1; - uint32_t reserved4:8; - } bitfields4; - uint32_t ordinal4; - }; - -}; -#endif /*--------------------MES_MAP_PROCESS-------------------- */ @@ -186,217 +93,58 @@ struct pm4_map_process { }; #endif -/*--------------------MES_MAP_QUEUES--------------------*/ - -#ifndef PM4_MES_MAP_QUEUES_DEFINED -#define PM4_MES_MAP_QUEUES_DEFINED -enum map_queues_queue_sel_enum { - queue_sel__mes_map_queues__map_to_specified_queue_slots = 0, - queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1, - queue_sel__mes_map_queues__enable_process_queues = 2 -}; +#ifndef PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH +#define PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH -enum map_queues_vidmem_enum { - vidmem__mes_map_queues__uses_no_video_memory = 0, - vidmem__mes_map_queues__uses_video_memory = 1 -}; - -enum map_queues_alloc_format_enum { - alloc_format__mes_map_queues__one_per_pipe = 0, - alloc_format__mes_map_queues__all_on_one_pipe = 1 -}; - -enum map_queues_engine_sel_enum { - engine_sel__mes_map_queues__compute = 0, - engine_sel__mes_map_queues__sdma0 = 2, - engine_sel__mes_map_queues__sdma1 = 3 -}; - -struct pm4_map_queues { +struct pm4_map_process_scratch_kv { union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t reserved1:4; - enum map_queues_queue_sel_enum queue_sel:2; - uint32_t reserved2:2; - uint32_t vmid:4; - uint32_t reserved3:4; - enum map_queues_vidmem_enum vidmem:2; - uint32_t reserved4:6; - enum map_queues_alloc_format_enum alloc_format:2; - enum map_queues_engine_sel_enum engine_sel:3; - uint32_t num_queues:3; - } bitfields2; - uint32_t ordinal2; - }; - - struct { - union { - struct { - uint32_t is_static:1; - uint32_t reserved5:1; - uint32_t doorbell_offset:21; - uint32_t reserved6:3; - uint32_t queue:6; - } bitfields3; - uint32_t ordinal3; - }; - - uint32_t mqd_addr_lo; - uint32_t mqd_addr_hi; - uint32_t wptr_addr_lo; - uint32_t wptr_addr_hi; - - } mes_map_queues_ordinals[1]; /* 1..N of these ordinal groups */ - -}; -#endif - -/*--------------------MES_QUERY_STATUS--------------------*/ - -#ifndef PM4_MES_QUERY_STATUS_DEFINED -#define PM4_MES_QUERY_STATUS_DEFINED -enum query_status_interrupt_sel_enum { - interrupt_sel__mes_query_status__completion_status = 0, - interrupt_sel__mes_query_status__process_status = 1, - interrupt_sel__mes_query_status__queue_status = 2 -}; - -enum query_status_command_enum { - command__mes_query_status__interrupt_only = 0, - command__mes_query_status__fence_only_immediate = 1, - command__mes_query_status__fence_only_after_write_ack = 2, - command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 -}; - -enum query_status_engine_sel_enum { - engine_sel__mes_query_status__compute = 0, - engine_sel__mes_query_status__sdma0_queue = 2, - engine_sel__mes_query_status__sdma1_queue = 3 -}; - -struct pm4_query_status { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - uint32_t context_id:28; - enum query_status_interrupt_sel_enum interrupt_sel:2; - enum query_status_command_enum command:2; - } bitfields2; - uint32_t ordinal2; + union PM4_MES_TYPE_3_HEADER header; /* header */ + uint32_t ordinal1; }; union { struct { uint32_t pasid:16; - uint32_t reserved1:16; - } bitfields3a; - struct { - uint32_t reserved2:2; - uint32_t doorbell_offset:21; - uint32_t reserved3:3; - enum query_status_engine_sel_enum engine_sel:3; - uint32_t reserved4:3; - } bitfields3b; - uint32_t ordinal3; - }; - - uint32_t addr_lo; - uint32_t addr_hi; - uint32_t data_lo; - uint32_t data_hi; -}; -#endif - -/*--------------------MES_UNMAP_QUEUES--------------------*/ - -#ifndef PM4_MES_UNMAP_QUEUES_DEFINED -#define PM4_MES_UNMAP_QUEUES_DEFINED -enum unmap_queues_action_enum { - action__mes_unmap_queues__preempt_queues = 0, - action__mes_unmap_queues__reset_queues = 1, - action__mes_unmap_queues__disable_process_queues = 2 -}; - -enum unmap_queues_queue_sel_enum { - queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, - queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, - queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2, - queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only = 3 -}; - -enum unmap_queues_engine_sel_enum { - engine_sel__mes_unmap_queues__compute = 0, - engine_sel__mes_unmap_queues__sdma0 = 2, - engine_sel__mes_unmap_queues__sdma1 = 3 -}; - -struct pm4_unmap_queues { - union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; - }; - - union { - struct { - enum unmap_queues_action_enum action:2; - uint32_t reserved1:2; - enum unmap_queues_queue_sel_enum queue_sel:2; - uint32_t reserved2:20; - enum unmap_queues_engine_sel_enum engine_sel:3; - uint32_t num_queues:3; + uint32_t reserved1:8; + uint32_t diq_enable:1; + uint32_t process_quantum:7; } bitfields2; uint32_t ordinal2; }; union { struct { - uint32_t pasid:16; - uint32_t reserved3:16; - } bitfields3a; - struct { - uint32_t reserved4:2; - uint32_t doorbell_offset0:21; - uint32_t reserved5:9; - } bitfields3b; + uint32_t page_table_base:28; + uint32_t reserved2:4; + } bitfields3; uint32_t ordinal3; }; - union { - struct { - uint32_t reserved6:2; - uint32_t doorbell_offset1:21; - uint32_t reserved7:9; - } bitfields4; - uint32_t ordinal4; - }; - - union { - struct { - uint32_t reserved8:2; - uint32_t doorbell_offset2:21; - uint32_t reserved9:9; - } bitfields5; - uint32_t ordinal5; - }; + uint32_t reserved3; + uint32_t sh_mem_bases; + uint32_t sh_mem_config; + uint32_t sh_mem_ape1_base; + uint32_t sh_mem_ape1_limit; + uint32_t sh_hidden_private_base_vmid; + uint32_t reserved4; + uint32_t reserved5; + uint32_t gds_addr_lo; + uint32_t gds_addr_hi; union { struct { - uint32_t reserved10:2; - uint32_t doorbell_offset3:21; - uint32_t reserved11:9; - } bitfields6; - uint32_t ordinal6; + uint32_t num_gws:6; + uint32_t reserved6:2; + uint32_t num_oac:4; + uint32_t reserved7:4; + uint32_t gds_size:6; + uint32_t num_queues:10; + } bitfields14; + uint32_t ordinal14; }; + uint32_t completion_signal_lo32; +uint32_t completion_signal_hi32; }; #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h index 08c721922812..7c8d9b357749 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h @@ -30,10 +30,12 @@ union PM4_MES_TYPE_3_HEADER { struct { uint32_t reserved1 : 8; /* < reserved */ uint32_t opcode : 8; /* < IT opcode */ - uint32_t count : 14;/* < number of DWORDs - 1 in the - information body. */ - uint32_t type : 2; /* < packet identifier. - It should be 3 for type 3 packets */ + uint32_t count : 14;/* < Number of DWORDS - 1 in the + * information body + */ + uint32_t type : 2; /* < packet identifier + * It should be 3 for type 3 packets + */ }; uint32_t u32All; }; @@ -124,9 +126,10 @@ struct pm4_mes_runlist { uint32_t ib_size:20; uint32_t chain:1; uint32_t offload_polling:1; - uint32_t reserved3:1; + uint32_t reserved2:1; uint32_t valid:1; - uint32_t reserved4:8; + uint32_t process_cnt:4; + uint32_t reserved3:4; } bitfields4; uint32_t ordinal4; }; @@ -141,8 +144,8 @@ struct pm4_mes_runlist { struct pm4_mes_map_process { union { - union PM4_MES_TYPE_3_HEADER header; /* header */ - uint32_t ordinal1; + union PM4_MES_TYPE_3_HEADER header; /* header */ + uint32_t ordinal1; }; union { @@ -153,36 +156,48 @@ struct pm4_mes_map_process { uint32_t process_quantum:7; } bitfields2; uint32_t ordinal2; -}; + }; union { struct { uint32_t page_table_base:28; - uint32_t reserved2:4; + uint32_t reserved3:4; } bitfields3; uint32_t ordinal3; }; + uint32_t reserved; + uint32_t sh_mem_bases; + uint32_t sh_mem_config; uint32_t sh_mem_ape1_base; uint32_t sh_mem_ape1_limit; - uint32_t sh_mem_config; + + uint32_t sh_hidden_private_base_vmid; + + uint32_t reserved2; + uint32_t reserved3; + uint32_t gds_addr_lo; uint32_t gds_addr_hi; union { struct { uint32_t num_gws:6; - uint32_t reserved3:2; + uint32_t reserved4:2; uint32_t num_oac:4; - uint32_t reserved4:4; + uint32_t reserved5:4; uint32_t gds_size:6; uint32_t num_queues:10; } bitfields10; uint32_t ordinal10; }; + uint32_t completion_signal_lo; + uint32_t completion_signal_hi; + }; + #endif /*--------------------MES_MAP_QUEUES--------------------*/ @@ -335,7 +350,7 @@ enum mes_unmap_queues_engine_sel_enum { engine_sel__mes_unmap_queues__sdmal = 3 }; -struct PM4_MES_UNMAP_QUEUES { +struct pm4_mes_unmap_queues { union { union PM4_MES_TYPE_3_HEADER header; /* header */ uint32_t ordinal1; @@ -395,4 +410,101 @@ struct PM4_MES_UNMAP_QUEUES { }; #endif +#ifndef PM4_MEC_RELEASE_MEM_DEFINED +#define PM4_MEC_RELEASE_MEM_DEFINED +enum RELEASE_MEM_event_index_enum { + event_index___release_mem__end_of_pipe = 5, + event_index___release_mem__shader_done = 6 +}; + +enum RELEASE_MEM_cache_policy_enum { + cache_policy___release_mem__lru = 0, + cache_policy___release_mem__stream = 1, + cache_policy___release_mem__bypass = 2 +}; + +enum RELEASE_MEM_dst_sel_enum { + dst_sel___release_mem__memory_controller = 0, + dst_sel___release_mem__tc_l2 = 1, + dst_sel___release_mem__queue_write_pointer_register = 2, + dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 +}; + +enum RELEASE_MEM_int_sel_enum { + int_sel___release_mem__none = 0, + int_sel___release_mem__send_interrupt_only = 1, + int_sel___release_mem__send_interrupt_after_write_confirm = 2, + int_sel___release_mem__send_data_after_write_confirm = 3 +}; + +enum RELEASE_MEM_data_sel_enum { + data_sel___release_mem__none = 0, + data_sel___release_mem__send_32_bit_low = 1, + data_sel___release_mem__send_64_bit_data = 2, + data_sel___release_mem__send_gpu_clock_counter = 3, + data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, + data_sel___release_mem__store_gds_data_to_memory = 5 +}; + +struct pm4_mec_release_mem { + union { + union PM4_MES_TYPE_3_HEADER header; /*header */ + unsigned int ordinal1; + }; + + union { + struct { + unsigned int event_type:6; + unsigned int reserved1:2; + enum RELEASE_MEM_event_index_enum event_index:4; + unsigned int tcl1_vol_action_ena:1; + unsigned int tc_vol_action_ena:1; + unsigned int reserved2:1; + unsigned int tc_wb_action_ena:1; + unsigned int tcl1_action_ena:1; + unsigned int tc_action_ena:1; + unsigned int reserved3:6; + unsigned int atc:1; + enum RELEASE_MEM_cache_policy_enum cache_policy:2; + unsigned int reserved4:5; + } bitfields2; + unsigned int ordinal2; + }; + + union { + struct { + unsigned int reserved5:16; + enum RELEASE_MEM_dst_sel_enum dst_sel:2; + unsigned int reserved6:6; + enum RELEASE_MEM_int_sel_enum int_sel:3; + unsigned int reserved7:2; + enum RELEASE_MEM_data_sel_enum data_sel:3; + } bitfields3; + unsigned int ordinal3; + }; + + union { + struct { + unsigned int reserved8:2; + unsigned int address_lo_32b:30; + } bitfields4; + struct { + unsigned int reserved9:3; + unsigned int address_lo_64b:29; + } bitfields5; + unsigned int ordinal4; + }; + + unsigned int address_hi; + + unsigned int data_lo; + + unsigned int data_hi; +}; +#endif + +enum { + CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 +}; + #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4750cabe4252..b397ec726400 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -239,11 +239,6 @@ enum kfd_preempt_type_filter { KFD_PREEMPT_TYPE_FILTER_BY_PASID }; -enum kfd_preempt_type { - KFD_PREEMPT_TYPE_WAVEFRONT, - KFD_PREEMPT_TYPE_WAVEFRONT_RESET -}; - /** * enum kfd_queue_type * @@ -294,13 +289,13 @@ enum kfd_queue_format { * @write_ptr: Defines the number of dwords written to the ring buffer. * * @doorbell_ptr: This field aim is to notify the H/W of new packet written to - * the queue ring buffer. This field should be similar to write_ptr and the user - * should update this field after he updated the write_ptr. + * the queue ring buffer. This field should be similar to write_ptr and the + * user should update this field after he updated the write_ptr. * * @doorbell_off: The doorbell offset in the doorbell pci-bar. * - * @is_interop: Defines if this is a interop queue. Interop queue means that the - * queue can access both graphics and compute resources. + * @is_interop: Defines if this is a interop queue. Interop queue means that + * the queue can access both graphics and compute resources. * * @is_active: Defines if the queue is active or not. * @@ -352,9 +347,10 @@ struct queue_properties { * @properties: The queue properties. * * @mec: Used only in no cp scheduling mode and identifies to micro engine id - * that the queue should be execute on. + * that the queue should be execute on. * - * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe id. + * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe + * id. * * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. * @@ -436,6 +432,7 @@ struct qcm_process_device { uint32_t gds_size; uint32_t num_gws; uint32_t num_oac; + uint32_t sh_hidden_private_base; }; /* Data that is per-process-per device. */ @@ -520,8 +517,8 @@ struct kfd_process { struct mutex event_mutex; /* All events in process hashed by ID, linked on kfd_event.events. */ DECLARE_HASHTABLE(events, 4); - struct list_head signal_event_pages; /* struct slot_page_header. - event_pages */ + /* struct slot_page_header.event_pages */ + struct list_head signal_event_pages; u32 next_nonsignal_event_id; size_t signal_event_count; }; @@ -559,8 +556,10 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_dev *dev, struct kfd_process *p); /* Process device data iterator */ -struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p); -struct kfd_process_device *kfd_get_next_process_device_data(struct kfd_process *p, +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p); +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, struct kfd_process_device *pdd); bool kfd_has_process_device_data(struct kfd_process *p); @@ -573,7 +572,8 @@ unsigned int kfd_pasid_alloc(void); void kfd_pasid_free(unsigned int pasid); /* Doorbells */ -void kfd_doorbell_init(struct kfd_dev *kfd); +int kfd_doorbell_init(struct kfd_dev *kfd); +void kfd_doorbell_fini(struct kfd_dev *kfd); int kfd_doorbell_mmap(struct kfd_process *process, struct vm_area_struct *vma); u32 __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, unsigned int *doorbell_off); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 035bbc98a63d..c74cf22a1ed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -79,9 +79,7 @@ struct kfd_process *kfd_create_process(const struct task_struct *thread) { struct kfd_process *process; - BUG_ON(!kfd_process_wq); - - if (thread->mm == NULL) + if (!thread->mm) return ERR_PTR(-EINVAL); /* Only the pthreads threading model is supported. */ @@ -101,7 +99,7 @@ struct kfd_process *kfd_create_process(const struct task_struct *thread) /* A prior open of /dev/kfd could have already created the process. */ process = find_process(thread); if (process) - pr_debug("kfd: process already found\n"); + pr_debug("Process already found\n"); if (!process) process = create_process(thread); @@ -117,7 +115,7 @@ struct kfd_process *kfd_get_process(const struct task_struct *thread) { struct kfd_process *process; - if (thread->mm == NULL) + if (!thread->mm) return ERR_PTR(-EINVAL); /* Only the pthreads threading model is supported. */ @@ -202,10 +200,8 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) struct kfd_process_release_work *work; struct kfd_process *p; - BUG_ON(!kfd_process_wq); - p = container_of(rcu, struct kfd_process, rcu); - BUG_ON(atomic_read(&p->mm->mm_count) <= 0); + WARN_ON(atomic_read(&p->mm->mm_count) <= 0); mmdrop(p->mm); @@ -229,7 +225,8 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, * mmu_notifier srcu is read locked */ p = container_of(mn, struct kfd_process, mmu_notifier); - BUG_ON(p->mm != mm); + if (WARN_ON(p->mm != mm)) + return; mutex_lock(&kfd_processes_mutex); hash_del_rcu(&p->kfd_processes); @@ -250,7 +247,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, kfd_dbgmgr_destroy(pdd->dev->dbgmgr); if (pdd->reset_wavefronts) { - pr_warn("amdkfd: Resetting all wave fronts\n"); + pr_warn("Resetting all wave fronts\n"); dbgdev_wave_reset_wavefronts(pdd->dev, p); pdd->reset_wavefronts = false; } @@ -407,8 +404,6 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid) struct kfd_process *p; struct kfd_process_device *pdd; - BUG_ON(dev == NULL); - /* * Look for the process that matches the pasid. If there is no such * process, we either released it in amdkfd's own notifier, or there @@ -449,14 +444,16 @@ void kfd_unbind_process_from_device(struct kfd_dev *dev, unsigned int pasid) mutex_unlock(&p->mutex); } -struct kfd_process_device *kfd_get_first_process_device_data(struct kfd_process *p) +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p) { return list_first_entry(&p->per_device_data, struct kfd_process_device, per_device_list); } -struct kfd_process_device *kfd_get_next_process_device_data(struct kfd_process *p, +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, struct kfd_process_device *pdd) { if (list_is_last(&pdd->per_device_list, &p->per_device_data)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 32cdf2b483db..1cae95e2b13a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -32,12 +32,9 @@ static inline struct process_queue_node *get_queue_by_qid( { struct process_queue_node *pqn; - BUG_ON(!pqm); - list_for_each_entry(pqn, &pqm->queues, process_queue_list) { - if (pqn->q && pqn->q->properties.queue_id == qid) - return pqn; - if (pqn->kq && pqn->kq->queue->properties.queue_id == qid) + if ((pqn->q && pqn->q->properties.queue_id == qid) || + (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) return pqn; } @@ -49,17 +46,13 @@ static int find_available_queue_slot(struct process_queue_manager *pqm, { unsigned long found; - BUG_ON(!pqm || !qid); - - pr_debug("kfd: in %s\n", __func__); - found = find_first_zero_bit(pqm->queue_slot_bitmap, KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); - pr_debug("kfd: the new slot id %lu\n", found); + pr_debug("The new slot id %lu\n", found); if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { - pr_info("amdkfd: Can not open more queues for process with pasid %d\n", + pr_info("Cannot open more queues for process with pasid %d\n", pqm->process->pasid); return -ENOMEM; } @@ -72,13 +65,11 @@ static int find_available_queue_slot(struct process_queue_manager *pqm, int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { - BUG_ON(!pqm); - INIT_LIST_HEAD(&pqm->queues); pqm->queue_slot_bitmap = kzalloc(DIV_ROUND_UP(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, BITS_PER_BYTE), GFP_KERNEL); - if (pqm->queue_slot_bitmap == NULL) + if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; @@ -90,10 +81,6 @@ void pqm_uninit(struct process_queue_manager *pqm) int retval; struct process_queue_node *pqn, *next; - BUG_ON(!pqm); - - pr_debug("In func %s\n", __func__); - list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { retval = pqm_destroy_queue( pqm, @@ -102,7 +89,7 @@ void pqm_uninit(struct process_queue_manager *pqm) pqn->kq->queue->properties.queue_id); if (retval != 0) { - pr_err("kfd: failed to destroy queue\n"); + pr_err("failed to destroy queue\n"); return; } } @@ -117,8 +104,6 @@ static int create_cp_queue(struct process_queue_manager *pqm, { int retval; - retval = 0; - /* Doorbell initialized in user space*/ q_properties->doorbell_ptr = NULL; @@ -131,16 +116,13 @@ static int create_cp_queue(struct process_queue_manager *pqm, retval = init_queue(q, q_properties); if (retval != 0) - goto err_init_queue; + return retval; (*q)->device = dev; (*q)->process = pqm->process; - pr_debug("kfd: PQM After init queue"); - - return retval; + pr_debug("PQM After init queue"); -err_init_queue: return retval; } @@ -161,8 +143,6 @@ int pqm_create_queue(struct process_queue_manager *pqm, int num_queues = 0; struct queue *cur; - BUG_ON(!pqm || !dev || !properties || !qid); - memset(&q_properties, 0, sizeof(struct queue_properties)); memcpy(&q_properties, properties, sizeof(struct queue_properties)); q = NULL; @@ -185,7 +165,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, list_for_each_entry(cur, &pdd->qpd.queues_list, list) num_queues++; if (num_queues >= dev->device_info->max_no_of_hqd/2) - return (-ENOSPC); + return -ENOSPC; } retval = find_available_queue_slot(pqm, qid); @@ -197,7 +177,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); } - pqn = kzalloc(sizeof(struct process_queue_node), GFP_KERNEL); + pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); if (!pqn) { retval = -ENOMEM; goto err_allocate_pqn; @@ -210,7 +190,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && ((dev->dqm->processes_count >= VMID_PER_DEVICE) || (dev->dqm->queue_count >= get_queues_num(dev->dqm)))) { - pr_err("kfd: over-subscription is not allowed in radeon_kfd.sched_policy == 1\n"); + pr_err("Over-subscription is not allowed in radeon_kfd.sched_policy == 1\n"); retval = -EPERM; goto err_create_queue; } @@ -227,7 +207,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, break; case KFD_QUEUE_TYPE_DIQ: kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ); - if (kq == NULL) { + if (!kq) { retval = -ENOMEM; goto err_create_queue; } @@ -238,22 +218,22 @@ int pqm_create_queue(struct process_queue_manager *pqm, kq, &pdd->qpd); break; default: - BUG(); - break; + WARN(1, "Invalid queue type %d", type); + retval = -EINVAL; } if (retval != 0) { - pr_debug("Error dqm create queue\n"); + pr_err("DQM create queue failed\n"); goto err_create_queue; } - pr_debug("kfd: PQM After DQM create queue\n"); + pr_debug("PQM After DQM create queue\n"); list_add(&pqn->process_queue_list, &pqm->queues); if (q) { *properties = q->properties; - pr_debug("kfd: PQM done creating queue\n"); + pr_debug("PQM done creating queue\n"); print_queue_properties(properties); } @@ -279,14 +259,11 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dqm = NULL; - BUG_ON(!pqm); retval = 0; - pr_debug("kfd: In Func %s\n", __func__); - pqn = get_queue_by_qid(pqm, qid); - if (pqn == NULL) { - pr_err("kfd: queue id does not match any known queue\n"); + if (!pqn) { + pr_err("Queue id does not match any known queue\n"); return -EINVAL; } @@ -295,7 +272,8 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dev = pqn->kq->dev; if (pqn->q) dev = pqn->q->device; - BUG_ON(!dev); + if (WARN_ON(!dev)) + return -ENODEV; pdd = kfd_get_process_device_data(dev, pqm->process); if (!pdd) { @@ -335,12 +313,9 @@ int pqm_update_queue(struct process_queue_manager *pqm, unsigned int qid, int retval; struct process_queue_node *pqn; - BUG_ON(!pqm); - pqn = get_queue_by_qid(pqm, qid); if (!pqn) { - pr_debug("amdkfd: No queue %d exists for update operation\n", - qid); + pr_debug("No queue %d exists for update operation\n", qid); return -EFAULT; } @@ -363,8 +338,6 @@ struct kernel_queue *pqm_get_kernel_queue( { struct process_queue_node *pqn; - BUG_ON(!pqm); - pqn = get_queue_by_qid(pqm, qid); if (pqn && pqn->kq) return pqn->kq; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c index 0ab197077f2d..a5315d4f1c95 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c @@ -65,17 +65,15 @@ void print_queue(struct queue *q) int init_queue(struct queue **q, const struct queue_properties *properties) { - struct queue *tmp; + struct queue *tmp_q; - BUG_ON(!q); - - tmp = kzalloc(sizeof(struct queue), GFP_KERNEL); - if (!tmp) + tmp_q = kzalloc(sizeof(*tmp_q), GFP_KERNEL); + if (!tmp_q) return -ENOMEM; - memcpy(&tmp->properties, properties, sizeof(struct queue_properties)); + memcpy(&tmp_q->properties, properties, sizeof(*properties)); - *q = tmp; + *q = tmp_q; return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 1e5064749959..19ce59028d6b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -108,9 +108,6 @@ static int kfd_topology_get_crat_acpi(void *crat_image, size_t *size) static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) { - BUG_ON(!dev); - BUG_ON(!cu); - dev->node_props.cpu_cores_count = cu->num_cpu_cores; dev->node_props.cpu_core_id_base = cu->processor_id_low; if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) @@ -123,9 +120,6 @@ static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, struct crat_subtype_computeunit *cu) { - BUG_ON(!dev); - BUG_ON(!cu); - dev->node_props.simd_id_base = cu->processor_id_low; dev->node_props.simd_count = cu->num_simd_cores; dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; @@ -148,8 +142,6 @@ static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu) struct kfd_topology_device *dev; int i = 0; - BUG_ON(!cu); - pr_info("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", cu->proximity_domain, cu->hsa_capability); list_for_each_entry(dev, &topology_device_list, list) { @@ -177,8 +169,6 @@ static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem) struct kfd_topology_device *dev; int i = 0; - BUG_ON(!mem); - pr_info("Found memory entry in CRAT table with proximity_domain=%d\n", mem->promixity_domain); list_for_each_entry(dev, &topology_device_list, list) { @@ -223,8 +213,6 @@ static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache) struct kfd_topology_device *dev; uint32_t id; - BUG_ON(!cache); - id = cache->processor_id_low; pr_info("Found cache entry in CRAT table with processor_id=%d\n", id); @@ -274,8 +262,6 @@ static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink) uint32_t id_from; uint32_t id_to; - BUG_ON(!iolink); - id_from = iolink->proximity_domain_from; id_to = iolink->proximity_domain_to; @@ -323,8 +309,6 @@ static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr) struct crat_subtype_iolink *iolink; int ret = 0; - BUG_ON(!sub_type_hdr); - switch (sub_type_hdr->type) { case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY: cu = (struct crat_subtype_computeunit *)sub_type_hdr; @@ -368,8 +352,6 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; - BUG_ON(!dev); - list_del(&dev->list); while (dev->mem_props.next != &dev->mem_props) { @@ -416,7 +398,7 @@ static struct kfd_topology_device *kfd_create_topology_device(void) struct kfd_topology_device *dev; dev = kfd_alloc_struct(dev); - if (dev == NULL) { + if (!dev) { pr_err("No memory to allocate a topology device"); return NULL; } @@ -666,7 +648,7 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, dev->node_props.simd_count); if (dev->mem_bank_count < dev->node_props.mem_banks_count) { - pr_info_once("kfd: mem_banks_count truncated from %d to %d\n", + pr_info_once("mem_banks_count truncated from %d to %d\n", dev->node_props.mem_banks_count, dev->mem_bank_count); sysfs_show_32bit_prop(buffer, "mem_banks_count", @@ -763,8 +745,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; - BUG_ON(!dev); - if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) if (iolink->kobj) { @@ -819,12 +799,12 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, int ret; uint32_t i; - BUG_ON(!dev); + if (WARN_ON(dev->kobj_node)) + return -EEXIST; /* * Creating the sysfs folders */ - BUG_ON(dev->kobj_node); dev->kobj_node = kfd_alloc_struct(dev->kobj_node); if (!dev->kobj_node) return -ENOMEM; @@ -957,7 +937,7 @@ static int kfd_topology_update_sysfs(void) int ret; pr_info("Creating topology SYSFS entries\n"); - if (sys_props.kobj_topology == NULL) { + if (!sys_props.kobj_topology) { sys_props.kobj_topology = kfd_alloc_struct(sys_props.kobj_topology); if (!sys_props.kobj_topology) @@ -1117,10 +1097,8 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu) struct kfd_topology_device *dev; struct kfd_topology_device *out_dev = NULL; - BUG_ON(!gpu); - list_for_each_entry(dev, &topology_device_list, list) - if (dev->gpu == NULL && dev->node_props.simd_count > 0) { + if (!dev->gpu && (dev->node_props.simd_count > 0)) { dev->gpu = gpu; out_dev = dev; break; @@ -1143,11 +1121,9 @@ int kfd_topology_add_device(struct kfd_dev *gpu) struct kfd_topology_device *dev; int res; - BUG_ON(!gpu); - gpu_id = kfd_generate_gpu_id(gpu); - pr_debug("kfd: Adding new GPU (ID: 0x%x) to topology\n", gpu_id); + pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id); down_write(&topology_lock); /* @@ -1170,8 +1146,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu) * GPU vBIOS */ - /* - * Update the SYSFS tree, since we added another topology device + /* Update the SYSFS tree, since we added another topology + * device */ if (kfd_topology_update_sysfs() < 0) kfd_topology_release_sysfs(); @@ -1190,7 +1166,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu) if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) { dev->node_props.capability |= HSA_CAP_DOORBELL_PACKET_TYPE; - pr_info("amdkfd: adding doorbell packet type capability\n"); + pr_info("Adding doorbell packet type capability\n"); } res = 0; @@ -1210,8 +1186,6 @@ int kfd_topology_remove_device(struct kfd_dev *gpu) uint32_t gpu_id; int res = -ENODEV; - BUG_ON(!gpu); - down_write(&topology_lock); list_for_each_entry(dev, &topology_device_list, list) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 36f376677a53..94277cb734d2 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -41,6 +41,11 @@ struct kgd_dev; struct kgd_mem; +enum kfd_preempt_type { + KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0, + KFD_PREEMPT_TYPE_WAVEFRONT_RESET, +}; + enum kgd_memory_pool { KGD_POOL_SYSTEM_CACHEABLE = 1, KGD_POOL_SYSTEM_WRITECOMBINE = 2, @@ -82,6 +87,17 @@ struct kgd2kfd_shared_resources { size_t doorbell_start_offset; }; +struct tile_config { + uint32_t *tile_config_ptr; + uint32_t *macro_tile_config_ptr; + uint32_t num_tile_configs; + uint32_t num_macro_tile_configs; + + uint32_t gb_addr_config; + uint32_t num_banks; + uint32_t num_ranks; +}; + /** * struct kfd2kgd_calls * @@ -123,6 +139,11 @@ struct kgd2kfd_shared_resources { * * @get_fw_version: Returns FW versions from the header * + * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID. + * Only used for no cp scheduling mode + * + * @get_tile_config: Returns GPU-specific tiling mode information + * * This structure contains function pointers to services that the kgd driver * provides to amdkfd driver. * @@ -153,14 +174,16 @@ struct kfd2kgd_calls { int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd); bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); - int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type, + int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id); @@ -192,6 +215,9 @@ struct kfd2kgd_calls { uint16_t (*get_fw_version)(struct kgd_dev *kgd, enum kgd_engine_type type); + void (*set_scratch_backing_va)(struct kgd_dev *kgd, + uint64_t va, uint32_t vmid); + int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config); }; /** diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 0b74da3dca8b..bc839ff0bdd0 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -1240,13 +1240,18 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); - if (cz_hwmgr->sclk_dpm.soft_min_clk != - cz_hwmgr->sclk_dpm.soft_max_clk) - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, - PPSMC_MSG_SetSclkSoftMin, - cz_get_sclk_level(hwmgr, - cz_hwmgr->sclk_dpm.soft_max_clk, - PPSMC_MSG_SetSclkSoftMin)); + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetSclkSoftMin, + cz_get_sclk_level(hwmgr, + cz_hwmgr->sclk_dpm.soft_max_clk, + PPSMC_MSG_SetSclkSoftMin)); + + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetSclkSoftMax, + cz_get_sclk_level(hwmgr, + cz_hwmgr->sclk_dpm.soft_max_clk, + PPSMC_MSG_SetSclkSoftMax)); + return 0; } @@ -1292,17 +1297,55 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) { struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); - if (cz_hwmgr->sclk_dpm.soft_min_clk != - cz_hwmgr->sclk_dpm.soft_max_clk) { - cz_hwmgr->sclk_dpm.soft_max_clk = - cz_hwmgr->sclk_dpm.soft_min_clk; + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetSclkSoftMax, + cz_get_sclk_level(hwmgr, + cz_hwmgr->sclk_dpm.soft_min_clk, + PPSMC_MSG_SetSclkSoftMax)); - smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetSclkSoftMin, + cz_get_sclk_level(hwmgr, + cz_hwmgr->sclk_dpm.soft_min_clk, + PPSMC_MSG_SetSclkSoftMin)); + + return 0; +} + +static int cz_phm_force_dpm_sclk(struct pp_hwmgr *hwmgr, uint32_t sclk) +{ + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetSclkSoftMin, + cz_get_sclk_level(hwmgr, + sclk, + PPSMC_MSG_SetSclkSoftMin)); + + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, - cz_hwmgr->sclk_dpm.soft_max_clk, + sclk, PPSMC_MSG_SetSclkSoftMax)); + return 0; +} + +static int cz_get_profiling_clk(struct pp_hwmgr *hwmgr, uint32_t *sclk) +{ + struct phm_clock_voltage_dependency_table *table = + hwmgr->dyn_state.vddc_dependency_on_sclk; + int32_t tmp_sclk; + int32_t count; + + tmp_sclk = table->entries[table->count-1].clk * 70 / 100; + + for (count = table->count-1; count >= 0; count--) { + if (tmp_sclk >= table->entries[count].clk) { + tmp_sclk = table->entries[count].clk; + *sclk = tmp_sclk; + break; + } } + if (count < 0) + *sclk = table->entries[0].clk; return 0; } @@ -1310,30 +1353,70 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) { + uint32_t sclk = 0; int ret = 0; + uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; + + if (level == hwmgr->dpm_level) + return ret; + + if (!(hwmgr->dpm_level & profile_mode_mask)) { + /* enter profile mode, save current level, disable gfx cg*/ + if (level & profile_mode_mask) { + hwmgr->saved_dpm_level = hwmgr->dpm_level; + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_CG_STATE_UNGATE); + } + } else { + /* exit profile mode, restore level, enable gfx cg*/ + if (!(level & profile_mode_mask)) { + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) + level = hwmgr->saved_dpm_level; + cgs_set_clockgating_state(hwmgr->device, + AMD_IP_BLOCK_TYPE_GFX, + AMD_CG_STATE_GATE); + } + } switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: ret = cz_phm_force_dpm_highest(hwmgr); if (ret) return ret; + hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_LOW: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: ret = cz_phm_force_dpm_lowest(hwmgr); if (ret) return ret; + hwmgr->dpm_level = level; break; case AMD_DPM_FORCED_LEVEL_AUTO: ret = cz_phm_unforce_dpm_levels(hwmgr); if (ret) return ret; + hwmgr->dpm_level = level; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: + ret = cz_get_profiling_clk(hwmgr, &sclk); + if (ret) + return ret; + hwmgr->dpm_level = level; + cz_phm_force_dpm_sclk(hwmgr, sclk); + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + hwmgr->dpm_level = level; break; + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: default: break; } - hwmgr->dpm_level = level; - return ret; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index d025653c7823..9547f265a8bb 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -557,9 +557,8 @@ uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, u return vddci_table->entries[i].value; } - PP_ASSERT_WITH_CODE(false, - "VDDCI is larger than max VDDCI in VDDCI Voltage Table!", - return vddci_table->entries[i-1].value); + pr_debug("vddci is larger than max value in vddci_table\n"); + return vddci_table->entries[i-1].value; } int phm_find_boot_level(void *table, @@ -583,26 +582,26 @@ int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t virtual_voltage_id, int32_t *sclk) { - uint8_t entryId; - uint8_t voltageId; + uint8_t entry_id; + uint8_t voltage_id; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL); /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ - for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) { - voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd; - if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id) + for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { + voltage_id = table_info->vdd_dep_on_sclk->entries[entry_id].vddInd; + if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) break; } - PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count, - "Can't find requested voltage id in vdd_dep_on_sclk table!", - return -EINVAL; - ); + if (entry_id >= table_info->vdd_dep_on_sclk->count) { + pr_debug("Can't find requested voltage id in vdd_dep_on_sclk table\n"); + return -EINVAL; + } - *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk; + *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk; return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c index cd33eb179db2..c062844b15f3 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c @@ -142,7 +142,7 @@ int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, } } else if (voltage_mode == VOLTAGE_OBJ_SVID2) { voltage_table->psi1_enable = - voltage_object->svid2_voltage_obj.loadline_psi1 & 0x1; + (voltage_object->svid2_voltage_obj.loadline_psi1 & 0x20) >> 5; voltage_table->psi0_enable = voltage_object->svid2_voltage_obj.psi0_enable & 0x1; voltage_table->max_vid_step = diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c index 4c7f430b36eb..edc5fb6412d9 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c @@ -265,6 +265,15 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input, } } */ + if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) || + ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) { + rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100; + rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100; + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetSoftMinVcn, + (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min); + } + if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h index afb852295a15..2472b50e54cf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h @@ -280,6 +280,8 @@ struct rv_hwmgr { uint32_t f_actual_hard_min_freq; uint32_t fabric_actual_soft_min_freq; + uint32_t vclk_soft_min; + uint32_t dclk_soft_min; uint32_t gfx_actual_soft_min_freq; bool vcn_power_gated; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index f01cda93f178..c2743233ba10 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -1962,9 +1962,6 @@ static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); break; default: - PP_ASSERT_WITH_CODE(0, - "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!", - ); break; } cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 01ff5054041b..9d71a259d97d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -2313,7 +2313,7 @@ static int vega10_acg_enable(struct pp_hwmgr *hwmgr) smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_InitializeAcg); smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_RunAcgBtc); - vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response);; + vega10_read_arg_from_smc(hwmgr->smumgr, &agc_btc_response); if (1 == agc_btc_response) { if (1 == data->acg_loop_state) @@ -2522,6 +2522,9 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) pp_table->DisplayDpmVoltageMode = (uint8_t)(table_info->uc_dcef_dpm_voltage_mode); + data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable; + data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable; + if (data->registry_data.ulv_support && table_info->us_ulv_voltage_offset) { result = vega10_populate_ulv_state(hwmgr); @@ -3701,10 +3704,22 @@ static void vega10_apply_dal_minimum_voltage_request( return; } +static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) +{ + struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk; + struct phm_ppt_v2_information *table_info = + (struct phm_ppt_v2_information *)(hwmgr->pptable); + + vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk; + + return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; +} + static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend); + uint32_t socclk_idx; vega10_apply_dal_minimum_voltage_request(hwmgr); @@ -3725,13 +3740,22 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) if (!data->registry_data.mclk_dpm_key_disabled) { if (data->smc_state_table.mem_boot_level != data->dpm_table.mem_table.dpm_state.soft_min_level) { + if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { + socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( - hwmgr->smumgr, - PPSMC_MSG_SetSoftMinUclkByIndex, - data->smc_state_table.mem_boot_level), - "Failed to set soft min mclk index!", - return -EINVAL); - + hwmgr->smumgr, + PPSMC_MSG_SetSoftMinSocclkByIndex, + socclk_idx), + "Failed to set soft min uclk index!", + return -EINVAL); + } else { + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( + hwmgr->smumgr, + PPSMC_MSG_SetSoftMinUclkByIndex, + data->smc_state_table.mem_boot_level), + "Failed to set soft min uclk index!", + return -EINVAL); + } data->dpm_table.mem_table.dpm_state.soft_min_level = data->smc_state_table.mem_boot_level; } @@ -4138,7 +4162,7 @@ static int vega10_notify_smc_display_config_after_ps_adjustment( pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); } } else { - pr_info("Cannot find requested DCEFCLK!"); + pr_debug("Cannot find requested DCEFCLK!"); } if (min_clocks.memoryClock != 0) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c index fbafc849ea71..e7fa67063cdc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c @@ -543,7 +543,7 @@ static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- */ /* SQ */ - { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, + { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, @@ -556,7 +556,7 @@ static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, /* TD */ - { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, + { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, @@ -1208,7 +1208,7 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) if (0 != result) return result; - vega10_didt_set_mask(hwmgr, true); + vega10_didt_set_mask(hwmgr, false); cgs_enter_safe_mode(hwmgr->device, false); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c index e7ab8eb8a0cf..d44243441d28 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c @@ -321,10 +321,7 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) { - result = vega10_fan_ctrl_set_static_mode(hwmgr, - FDO_PWM_MODE_STATIC); - if (!result) - result = vega10_fan_ctrl_start_smc_fan_control(hwmgr); + result = vega10_fan_ctrl_start_smc_fan_control(hwmgr); } else result = vega10_fan_ctrl_set_default_mode(hwmgr); @@ -633,7 +630,6 @@ int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) { vega10_fan_ctrl_start_smc_fan_control(hwmgr); - vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } return 0; diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 47e57bd2c36f..91b0105e8240 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -128,6 +128,8 @@ struct phm_uvd_arbiter { uint32_t dclk; uint32_t vclk_ceiling; uint32_t dclk_ceiling; + uint32_t vclk_soft_min; + uint32_t dclk_soft_min; }; struct phm_vce_arbiter { diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h index e0e106f1b23a..901c960cfe21 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h @@ -66,7 +66,12 @@ #define PPSMC_MSG_SetMinVddcrSocVoltage 0x22 #define PPSMC_MSG_SetMinVideoFclkFreq 0x23 #define PPSMC_MSG_SetMinDeepSleepDcefclk 0x24 -#define PPSMC_Message_Count 0x25 +#define PPSMC_MSG_ForcePowerDownGfx 0x25 +#define PPSMC_MSG_SetPhyclkVoltageByFreq 0x26 +#define PPSMC_MSG_SetDppclkVoltageByFreq 0x27 +#define PPSMC_MSG_SetSoftMinVcn 0x28 +#define PPSMC_Message_Count 0x29 + typedef uint16_t PPSMC_Result; typedef int PPSMC_Msg; diff --git a/drivers/gpu/drm/arc/arcpgu_drv.c b/drivers/gpu/drm/arc/arcpgu_drv.c index e3c13aa202b8..289eda54e5aa 100644 --- a/drivers/gpu/drm/arc/arcpgu_drv.c +++ b/drivers/gpu/drm/arc/arcpgu_drv.c @@ -31,7 +31,7 @@ static void arcpgu_fb_output_poll_changed(struct drm_device *dev) drm_fbdev_cma_hotplug_event(arcpgu->fbdev); } -static struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = { +static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = { .fb_create = drm_fb_cma_create, .output_poll_changed = arcpgu_fb_output_poll_changed, .atomic_check = drm_atomic_helper_check, diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c index 3022b39c00f3..69dab82a3771 100644 --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c @@ -209,7 +209,6 @@ static struct drm_driver driver = { .gem_free_object_unlocked = ast_gem_free_object, .dumb_create = ast_dumb_create, .dumb_map_offset = ast_dumb_mmap_offset, - .dumb_destroy = drm_gem_dumb_destroy, }; diff --git a/drivers/gpu/drm/ast/ast_fb.c b/drivers/gpu/drm/ast/ast_fb.c index 9052ebeae8d0..0cd827e11fa2 100644 --- a/drivers/gpu/drm/ast/ast_fb.c +++ b/drivers/gpu/drm/ast/ast_fb.c @@ -266,7 +266,7 @@ static void ast_fbdev_destroy(struct drm_device *dev, drm_fb_helper_unregister_fbi(&afbdev->helper); if (afb->obj) { - drm_gem_object_unreference_unlocked(afb->obj); + drm_gem_object_put_unlocked(afb->obj); afb->obj = NULL; } drm_fb_helper_fini(&afbdev->helper); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 9a44cdec3bca..dac355812adc 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -387,7 +387,7 @@ static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb); - drm_gem_object_unreference_unlocked(ast_fb->obj); + drm_gem_object_put_unlocked(ast_fb->obj); drm_framebuffer_cleanup(fb); kfree(ast_fb); } @@ -429,13 +429,13 @@ ast_user_framebuffer_create(struct drm_device *dev, ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL); if (!ast_fb) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(-ENOMEM); } ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj); if (ret) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); kfree(ast_fb); return ERR_PTR(ret); } @@ -628,7 +628,7 @@ int ast_dumb_create(struct drm_file *file, return ret; ret = drm_gem_handle_create(file, gobj, &handle); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (ret) return ret; @@ -676,7 +676,7 @@ ast_dumb_mmap_offset(struct drm_file *file, bo = gem_to_ast_bo(obj); *offset = ast_bo_mmap_offset(bo); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return 0; diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 43245229f437..6f3849ec0c1d 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -950,7 +950,7 @@ static void ast_cursor_fini(struct drm_device *dev) { struct ast_private *ast = dev->dev_private; ttm_bo_kunmap(&ast->cache_kmap); - drm_gem_object_unreference_unlocked(ast->cursor_cache); + drm_gem_object_put_unlocked(ast->cursor_cache); } int ast_mode_init(struct drm_device *dev) @@ -1215,10 +1215,10 @@ static int ast_cursor_set(struct drm_crtc *crtc, ast_show_cursor(crtc); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return 0; fail: - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/bochs/bochs_drv.c b/drivers/gpu/drm/bochs/bochs_drv.c index a1d28845da5f..7b20318483e4 100644 --- a/drivers/gpu/drm/bochs/bochs_drv.c +++ b/drivers/gpu/drm/bochs/bochs_drv.c @@ -93,7 +93,6 @@ static struct drm_driver bochs_driver = { .gem_free_object_unlocked = bochs_gem_free_object, .dumb_create = bochs_dumb_create, .dumb_map_offset = bochs_dumb_mmap_offset, - .dumb_destroy = drm_gem_dumb_destroy, }; /* ---------------------------------------------------------------------- */ diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 682c090fa3ed..b2431aee7887 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -785,7 +785,7 @@ adv7511_connector_detect(struct drm_connector *connector, bool force) return adv7511_detect(adv, connector); } -static struct drm_connector_funcs adv7511_connector_funcs = { +static const struct drm_connector_funcs adv7511_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .detect = adv7511_connector_detect, .destroy = drm_connector_cleanup, @@ -856,7 +856,7 @@ static int adv7511_bridge_attach(struct drm_bridge *bridge) return ret; } -static struct drm_bridge_funcs adv7511_bridge_funcs = { +static const struct drm_bridge_funcs adv7511_bridge_funcs = { .enable = adv7511_bridge_enable, .disable = adv7511_bridge_disable, .mode_set = adv7511_bridge_mode_set, diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c index 8f2d1379c880..cf3f0caf9c63 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c @@ -517,7 +517,7 @@ static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream) return bytes_to_frames(runtime, dw->buf_offset); } -static struct snd_pcm_ops snd_dw_hdmi_ops = { +static const struct snd_pcm_ops snd_dw_hdmi_ops = { .open = dw_hdmi_open, .close = dw_hdmi_close, .ioctl = snd_pcm_lib_ioctl, diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 36f5ccbd1794..63c7a01b7053 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -811,7 +811,7 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge) return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge); } -static struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { +static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { .mode_set = dw_mipi_dsi_bridge_mode_set, .enable = dw_mipi_dsi_bridge_enable, .post_disable = dw_mipi_dsi_bridge_post_disable, diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c b/drivers/gpu/drm/cirrus/cirrus_drv.c index 910c300f5c37..69c4e352dd78 100644 --- a/drivers/gpu/drm/cirrus/cirrus_drv.c +++ b/drivers/gpu/drm/cirrus/cirrus_drv.c @@ -142,7 +142,6 @@ static struct drm_driver driver = { .gem_free_object_unlocked = cirrus_gem_free_object, .dumb_create = cirrus_dumb_create, .dumb_map_offset = cirrus_dumb_mmap_offset, - .dumb_destroy = drm_gem_dumb_destroy, }; static const struct dev_pm_ops cirrus_pm_ops = { diff --git a/drivers/gpu/drm/cirrus/cirrus_fbdev.c b/drivers/gpu/drm/cirrus/cirrus_fbdev.c index 0f6815f35ad2..32fbfba2c623 100644 --- a/drivers/gpu/drm/cirrus/cirrus_fbdev.c +++ b/drivers/gpu/drm/cirrus/cirrus_fbdev.c @@ -251,7 +251,7 @@ static int cirrus_fbdev_destroy(struct drm_device *dev, drm_fb_helper_unregister_fbi(&gfbdev->helper); if (gfb->obj) { - drm_gem_object_unreference_unlocked(gfb->obj); + drm_gem_object_put_unlocked(gfb->obj); gfb->obj = NULL; } diff --git a/drivers/gpu/drm/cirrus/cirrus_main.c b/drivers/gpu/drm/cirrus/cirrus_main.c index e7fc95f63dca..b5f528543956 100644 --- a/drivers/gpu/drm/cirrus/cirrus_main.c +++ b/drivers/gpu/drm/cirrus/cirrus_main.c @@ -18,7 +18,7 @@ static void cirrus_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct cirrus_framebuffer *cirrus_fb = to_cirrus_framebuffer(fb); - drm_gem_object_unreference_unlocked(cirrus_fb->obj); + drm_gem_object_put_unlocked(cirrus_fb->obj); drm_framebuffer_cleanup(fb); kfree(fb); } @@ -67,13 +67,13 @@ cirrus_user_framebuffer_create(struct drm_device *dev, cirrus_fb = kzalloc(sizeof(*cirrus_fb), GFP_KERNEL); if (!cirrus_fb) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(-ENOMEM); } ret = cirrus_framebuffer_init(dev, cirrus_fb, mode_cmd, obj); if (ret) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); kfree(cirrus_fb); return ERR_PTR(ret); } @@ -261,7 +261,7 @@ int cirrus_dumb_create(struct drm_file *file, return ret; ret = drm_gem_handle_create(file, gobj, &handle); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (ret) return ret; @@ -310,7 +310,7 @@ cirrus_dumb_mmap_offset(struct drm_file *file, bo = gem_to_cirrus_bo(obj); *offset = cirrus_bo_mmap_offset(bo); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return 0; } diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 1bc32cd74d78..4e53aae9a1fb 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -2716,6 +2716,7 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, struct drm_plane *plane; struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; + unsigned plane_mask = 0; int ret, i; state = drm_atomic_state_alloc(dev); @@ -2758,10 +2759,14 @@ int drm_atomic_helper_disable_all(struct drm_device *dev, goto free; drm_atomic_set_fb_for_plane(plane_state, NULL); + plane_mask |= BIT(drm_plane_index(plane)); + plane->old_fb = plane->fb; } ret = drm_atomic_commit(state); free: + if (plane_mask) + drm_atomic_clean_old_fb(dev, plane_mask, ret); drm_atomic_state_put(state); return ret; } @@ -2892,11 +2897,16 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, struct drm_connector_state *new_conn_state; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; + unsigned plane_mask = 0; + struct drm_device *dev = state->dev; + int ret; state->acquire_ctx = ctx; - for_each_new_plane_in_state(state, plane, new_plane_state, i) + for_each_new_plane_in_state(state, plane, new_plane_state, i) { + plane_mask |= BIT(drm_plane_index(plane)); state->planes[i].old_state = plane->state; + } for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) state->crtcs[i].old_state = crtc->state; @@ -2904,7 +2914,11 @@ int drm_atomic_helper_commit_duplicated_state(struct drm_atomic_state *state, for_each_new_connector_in_state(state, connector, new_conn_state, i) state->connectors[i].old_state = connector->state; - return drm_atomic_commit(state); + ret = drm_atomic_commit(state); + if (plane_mask) + drm_atomic_clean_old_fb(dev, plane_mask, ret); + + return ret; } EXPORT_SYMBOL(drm_atomic_helper_commit_duplicated_state); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 2ed2d919beae..be38ac7050d4 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -291,7 +291,7 @@ struct drm_minor *drm_minor_acquire(unsigned int minor_id) if (!minor) { return ERR_PTR(-ENODEV); - } else if (drm_device_is_unplugged(minor->dev)) { + } else if (drm_dev_is_unplugged(minor->dev)) { drm_dev_unref(minor->dev); return ERR_PTR(-ENODEV); } @@ -364,26 +364,32 @@ void drm_put_dev(struct drm_device *dev) } EXPORT_SYMBOL(drm_put_dev); -void drm_unplug_dev(struct drm_device *dev) +static void drm_device_set_unplugged(struct drm_device *dev) { - /* for a USB device */ - if (drm_core_check_feature(dev, DRIVER_MODESET)) - drm_modeset_unregister_all(dev); + smp_wmb(); + atomic_set(&dev->unplugged, 1); +} - drm_minor_unregister(dev, DRM_MINOR_PRIMARY); - drm_minor_unregister(dev, DRM_MINOR_RENDER); - drm_minor_unregister(dev, DRM_MINOR_CONTROL); +/** + * drm_dev_unplug - unplug a DRM device + * @dev: DRM device + * + * This unplugs a hotpluggable DRM device, which makes it inaccessible to + * userspace operations. Entry-points can use drm_dev_is_unplugged(). This + * essentially unregisters the device like drm_dev_unregister(), but can be + * called while there are still open users of @dev. + */ +void drm_dev_unplug(struct drm_device *dev) +{ + drm_dev_unregister(dev); mutex_lock(&drm_global_mutex); - drm_device_set_unplugged(dev); - - if (dev->open_count == 0) { - drm_put_dev(dev); - } + if (dev->open_count == 0) + drm_dev_unref(dev); mutex_unlock(&drm_global_mutex); } -EXPORT_SYMBOL(drm_unplug_dev); +EXPORT_SYMBOL(drm_dev_unplug); /* * DRM internal mount @@ -835,6 +841,9 @@ EXPORT_SYMBOL(drm_dev_register); * drm_dev_register() but does not deallocate the device. The caller must call * drm_dev_unref() to drop their final reference. * + * A special form of unregistering for hotpluggable devices is drm_dev_unplug(), + * which can be called while there are still open users of @dev. + * * This should be called first in the device teardown code to make sure * userspace can't access the device instance any more. */ @@ -842,7 +851,8 @@ void drm_dev_unregister(struct drm_device *dev) { struct drm_map_list *r_list, *list_temp; - drm_lastclose(dev); + if (drm_core_check_feature(dev, DRIVER_LEGACY)) + drm_lastclose(dev); dev->registered = false; diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c index ade319d10e70..f2ee88363015 100644 --- a/drivers/gpu/drm/drm_fb_cma_helper.c +++ b/drivers/gpu/drm/drm_fb_cma_helper.c @@ -18,27 +18,17 @@ */ #include <drm/drmP.h> -#include <drm/drm_atomic.h> -#include <drm/drm_crtc.h> #include <drm/drm_fb_helper.h> -#include <drm/drm_crtc_helper.h> +#include <drm/drm_framebuffer.h> #include <drm/drm_gem_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_fb_cma_helper.h> -#include <linux/dma-buf.h> -#include <linux/dma-mapping.h> #include <linux/module.h> -#include <linux/reservation.h> #define DEFAULT_FBDEFIO_DELAY_MS 50 -struct drm_fb_cma { - struct drm_framebuffer fb; - struct drm_gem_cma_object *obj[4]; -}; - struct drm_fbdev_cma { struct drm_fb_helper fb_helper; - struct drm_fb_cma *fb; const struct drm_framebuffer_funcs *fb_funcs; }; @@ -90,69 +80,19 @@ static inline struct drm_fbdev_cma *to_fbdev_cma(struct drm_fb_helper *helper) return container_of(helper, struct drm_fbdev_cma, fb_helper); } -static inline struct drm_fb_cma *to_fb_cma(struct drm_framebuffer *fb) -{ - return container_of(fb, struct drm_fb_cma, fb); -} - void drm_fb_cma_destroy(struct drm_framebuffer *fb) { - struct drm_fb_cma *fb_cma = to_fb_cma(fb); - int i; - - for (i = 0; i < 4; i++) { - if (fb_cma->obj[i]) - drm_gem_object_put_unlocked(&fb_cma->obj[i]->base); - } - - drm_framebuffer_cleanup(fb); - kfree(fb_cma); + drm_gem_fb_destroy(fb); } EXPORT_SYMBOL(drm_fb_cma_destroy); int drm_fb_cma_create_handle(struct drm_framebuffer *fb, struct drm_file *file_priv, unsigned int *handle) { - struct drm_fb_cma *fb_cma = to_fb_cma(fb); - - return drm_gem_handle_create(file_priv, - &fb_cma->obj[0]->base, handle); + return drm_gem_fb_create_handle(fb, file_priv, handle); } EXPORT_SYMBOL(drm_fb_cma_create_handle); -static struct drm_framebuffer_funcs drm_fb_cma_funcs = { - .destroy = drm_fb_cma_destroy, - .create_handle = drm_fb_cma_create_handle, -}; - -static struct drm_fb_cma *drm_fb_cma_alloc(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd, - struct drm_gem_cma_object **obj, - unsigned int num_planes, const struct drm_framebuffer_funcs *funcs) -{ - struct drm_fb_cma *fb_cma; - int ret; - int i; - - fb_cma = kzalloc(sizeof(*fb_cma), GFP_KERNEL); - if (!fb_cma) - return ERR_PTR(-ENOMEM); - - drm_helper_mode_fill_fb_struct(dev, &fb_cma->fb, mode_cmd); - - for (i = 0; i < num_planes; i++) - fb_cma->obj[i] = obj[i]; - - ret = drm_framebuffer_init(dev, &fb_cma->fb, funcs); - if (ret) { - dev_err(dev->dev, "Failed to initialize framebuffer: %d\n", ret); - kfree(fb_cma); - return ERR_PTR(ret); - } - - return fb_cma; -} - /** * drm_fb_cma_create_with_funcs() - helper function for the * &drm_mode_config_funcs.fb_create @@ -170,53 +110,7 @@ struct drm_framebuffer *drm_fb_cma_create_with_funcs(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd, const struct drm_framebuffer_funcs *funcs) { - const struct drm_format_info *info; - struct drm_fb_cma *fb_cma; - struct drm_gem_cma_object *objs[4]; - struct drm_gem_object *obj; - int ret; - int i; - - info = drm_get_format_info(dev, mode_cmd); - if (!info) - return ERR_PTR(-EINVAL); - - for (i = 0; i < info->num_planes; i++) { - unsigned int width = mode_cmd->width / (i ? info->hsub : 1); - unsigned int height = mode_cmd->height / (i ? info->vsub : 1); - unsigned int min_size; - - obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]); - if (!obj) { - dev_err(dev->dev, "Failed to lookup GEM object\n"); - ret = -ENOENT; - goto err_gem_object_put; - } - - min_size = (height - 1) * mode_cmd->pitches[i] - + width * info->cpp[i] - + mode_cmd->offsets[i]; - - if (obj->size < min_size) { - drm_gem_object_put_unlocked(obj); - ret = -EINVAL; - goto err_gem_object_put; - } - objs[i] = to_drm_gem_cma_obj(obj); - } - - fb_cma = drm_fb_cma_alloc(dev, mode_cmd, objs, i, funcs); - if (IS_ERR(fb_cma)) { - ret = PTR_ERR(fb_cma); - goto err_gem_object_put; - } - - return &fb_cma->fb; - -err_gem_object_put: - for (i--; i >= 0; i--) - drm_gem_object_put_unlocked(&objs[i]->base); - return ERR_PTR(ret); + return drm_gem_fb_create_with_funcs(dev, file_priv, mode_cmd, funcs); } EXPORT_SYMBOL_GPL(drm_fb_cma_create_with_funcs); @@ -233,8 +127,7 @@ EXPORT_SYMBOL_GPL(drm_fb_cma_create_with_funcs); struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) { - return drm_fb_cma_create_with_funcs(dev, file_priv, mode_cmd, - &drm_fb_cma_funcs); + return drm_gem_fb_create(dev, file_priv, mode_cmd); } EXPORT_SYMBOL_GPL(drm_fb_cma_create); @@ -250,12 +143,13 @@ EXPORT_SYMBOL_GPL(drm_fb_cma_create); struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb, unsigned int plane) { - struct drm_fb_cma *fb_cma = to_fb_cma(fb); + struct drm_gem_object *gem; - if (plane >= 4) + gem = drm_gem_fb_get_obj(fb, plane); + if (!gem) return NULL; - return fb_cma->obj[plane]; + return to_drm_gem_cma_obj(gem); } EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj); @@ -272,13 +166,14 @@ dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb, struct drm_plane_state *state, unsigned int plane) { - struct drm_fb_cma *fb_cma = to_fb_cma(fb); + struct drm_gem_cma_object *obj; dma_addr_t paddr; - if (plane >= 4) + obj = drm_fb_cma_get_gem_obj(fb, plane); + if (!obj) return 0; - paddr = fb_cma->obj[plane]->paddr + fb->offsets[plane]; + paddr = obj->paddr + fb->offsets[plane]; paddr += fb->format->cpp[plane] * (state->src_x >> 16); paddr += fb->pitches[plane] * (state->src_y >> 16); @@ -302,26 +197,13 @@ EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_addr); int drm_fb_cma_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) { - struct dma_buf *dma_buf; - struct dma_fence *fence; - - if ((plane->state->fb == state->fb) || !state->fb) - return 0; - - dma_buf = drm_fb_cma_get_gem_obj(state->fb, 0)->base.dma_buf; - if (dma_buf) { - fence = reservation_object_get_excl_rcu(dma_buf->resv); - drm_atomic_set_fence_for_plane(state, fence); - } - - return 0; + return drm_gem_fb_prepare_fb(plane, state); } EXPORT_SYMBOL_GPL(drm_fb_cma_prepare_fb); #ifdef CONFIG_DEBUG_FS static void drm_fb_cma_describe(struct drm_framebuffer *fb, struct seq_file *m) { - struct drm_fb_cma *fb_cma = to_fb_cma(fb); int i; seq_printf(m, "fb: %dx%d@%4.4s\n", fb->width, fb->height, @@ -330,7 +212,7 @@ static void drm_fb_cma_describe(struct drm_framebuffer *fb, struct seq_file *m) for (i = 0; i < fb->format->num_planes; i++) { seq_printf(m, " %d: offset=%d pitch=%d, obj: ", i, fb->offsets[i], fb->pitches[i]); - drm_gem_cma_describe(fb_cma->obj[i], m); + drm_gem_cma_describe(drm_fb_cma_get_gem_obj(fb, i), m); } } @@ -431,7 +313,6 @@ drm_fbdev_cma_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { struct drm_fbdev_cma *fbdev_cma = to_fbdev_cma(helper); - struct drm_mode_fb_cmd2 mode_cmd = { 0 }; struct drm_device *dev = helper->dev; struct drm_gem_cma_object *obj; struct drm_framebuffer *fb; @@ -446,14 +327,7 @@ drm_fbdev_cma_create(struct drm_fb_helper *helper, sizes->surface_bpp); bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8); - - mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; - mode_cmd.pitches[0] = sizes->surface_width * bytes_per_pixel; - mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, - sizes->surface_depth); - - size = mode_cmd.pitches[0] * mode_cmd.height; + size = sizes->surface_width * sizes->surface_height * bytes_per_pixel; obj = drm_gem_cma_create(dev, size); if (IS_ERR(obj)) return -ENOMEM; @@ -464,15 +338,14 @@ drm_fbdev_cma_create(struct drm_fb_helper *helper, goto err_gem_free_object; } - fbdev_cma->fb = drm_fb_cma_alloc(dev, &mode_cmd, &obj, 1, - fbdev_cma->fb_funcs); - if (IS_ERR(fbdev_cma->fb)) { + fb = drm_gem_fbdev_fb_create(dev, sizes, 0, &obj->base, + fbdev_cma->fb_funcs); + if (IS_ERR(fb)) { dev_err(dev->dev, "Failed to allocate DRM framebuffer.\n"); - ret = PTR_ERR(fbdev_cma->fb); + ret = PTR_ERR(fb); goto err_fb_info_destroy; } - fb = &fbdev_cma->fb->fb; helper->fb = fb; fbi->par = helper; @@ -500,7 +373,7 @@ drm_fbdev_cma_create(struct drm_fb_helper *helper, return 0; err_cma_destroy: - drm_framebuffer_remove(&fbdev_cma->fb->fb); + drm_framebuffer_remove(fb); err_fb_info_destroy: drm_fb_helper_fini(helper); err_gem_free_object: @@ -570,6 +443,11 @@ err_free: } EXPORT_SYMBOL_GPL(drm_fbdev_cma_init_with_funcs); +static const struct drm_framebuffer_funcs drm_fb_cma_funcs = { + .destroy = drm_gem_fb_destroy, + .create_handle = drm_gem_fb_create_handle, +}; + /** * drm_fbdev_cma_init() - Allocate and initializes a drm_fbdev_cma struct * @dev: DRM device @@ -597,8 +475,8 @@ void drm_fbdev_cma_fini(struct drm_fbdev_cma *fbdev_cma) if (fbdev_cma->fb_helper.fbdev) drm_fbdev_cma_defio_fini(fbdev_cma->fb_helper.fbdev); - if (fbdev_cma->fb) - drm_framebuffer_remove(&fbdev_cma->fb->fb); + if (fbdev_cma->fb_helper.fb) + drm_framebuffer_remove(fbdev_cma->fb_helper.fb); drm_fb_helper_fini(&fbdev_cma->fb_helper); kfree(fbdev_cma); diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c index 59b75a974357..b3c6e997ccdb 100644 --- a/drivers/gpu/drm/drm_file.c +++ b/drivers/gpu/drm/drm_file.c @@ -436,7 +436,7 @@ int drm_release(struct inode *inode, struct file *filp) if (!--dev->open_count) { drm_lastclose(dev); - if (drm_device_is_unplugged(dev)) + if (drm_dev_is_unplugged(dev)) drm_put_dev(dev); } mutex_unlock(&drm_global_mutex); diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index a8d396bed6a4..ad4e9cfe48a2 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -1001,7 +1001,7 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) struct drm_vma_offset_node *node; int ret; - if (drm_device_is_unplugged(dev)) + if (drm_dev_is_unplugged(dev)) return -ENODEV; drm_vma_offset_lock_lookup(dev->vma_offset_manager); diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c index 275ab872b34f..373e33f22be4 100644 --- a/drivers/gpu/drm/drm_gem_cma_helper.c +++ b/drivers/gpu/drm/drm_gem_cma_helper.c @@ -264,41 +264,6 @@ int drm_gem_cma_dumb_create(struct drm_file *file_priv, } EXPORT_SYMBOL_GPL(drm_gem_cma_dumb_create); -/** - * drm_gem_cma_dumb_map_offset - return the fake mmap offset for a CMA GEM - * object - * @file_priv: DRM file-private structure containing the GEM object - * @drm: DRM device - * @handle: GEM object handle - * @offset: return location for the fake mmap offset - * - * This function look up an object by its handle and returns the fake mmap - * offset associated with it. Drivers using the CMA helpers should set this - * as their &drm_driver.dumb_map_offset callback. - * - * Returns: - * 0 on success or a negative error code on failure. - */ -int drm_gem_cma_dumb_map_offset(struct drm_file *file_priv, - struct drm_device *drm, u32 handle, - u64 *offset) -{ - struct drm_gem_object *gem_obj; - - gem_obj = drm_gem_object_lookup(file_priv, handle); - if (!gem_obj) { - dev_err(drm->dev, "failed to lookup GEM object\n"); - return -EINVAL; - } - - *offset = drm_vma_node_offset_addr(&gem_obj->vma_node); - - drm_gem_object_put_unlocked(gem_obj); - - return 0; -} -EXPORT_SYMBOL_GPL(drm_gem_cma_dumb_map_offset); - const struct vm_operations_struct drm_gem_cma_vm_ops = { .open = drm_gem_vm_open, .close = drm_gem_vm_close, @@ -390,7 +355,7 @@ unsigned long drm_gem_cma_get_unmapped_area(struct file *filp, struct drm_device *dev = priv->minor->dev; struct drm_vma_offset_node *node; - if (drm_device_is_unplugged(dev)) + if (drm_dev_is_unplugged(dev)) return -ENODEV; drm_vma_offset_lock_lookup(dev->vma_offset_manager); diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c new file mode 100644 index 000000000000..d54a083dc5dd --- /dev/null +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -0,0 +1,283 @@ +/* + * drm gem framebuffer helper functions + * + * Copyright (C) 2017 Noralf Trønnes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/dma-buf.h> +#include <linux/dma-fence.h> +#include <linux/reservation.h> +#include <linux/slab.h> + +#include <drm/drmP.h> +#include <drm/drm_atomic.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_framebuffer.h> +#include <drm/drm_gem.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_modeset_helper.h> + +/** + * DOC: overview + * + * This library provides helpers for drivers that don't subclass + * &drm_framebuffer and and use &drm_gem_object for their backing storage. + * + * Drivers without additional needs to validate framebuffers can simply use + * drm_gem_fb_create() and everything is wired up automatically. But all + * parts can be used individually. + */ + +/** + * drm_gem_fb_get_obj() - Get GEM object for framebuffer + * @fb: The framebuffer + * @plane: Which plane + * + * Returns the GEM object for given framebuffer. + */ +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane) +{ + if (plane >= 4) + return NULL; + + return fb->obj[plane]; +} +EXPORT_SYMBOL_GPL(drm_gem_fb_get_obj); + +static struct drm_framebuffer * +drm_gem_fb_alloc(struct drm_device *dev, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object **obj, unsigned int num_planes, + const struct drm_framebuffer_funcs *funcs) +{ + struct drm_framebuffer *fb; + int ret, i; + + fb = kzalloc(sizeof(*fb), GFP_KERNEL); + if (!fb) + return ERR_PTR(-ENOMEM); + + drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + + for (i = 0; i < num_planes; i++) + fb->obj[i] = obj[i]; + + ret = drm_framebuffer_init(dev, fb, funcs); + if (ret) { + DRM_DEV_ERROR(dev->dev, "Failed to init framebuffer: %d\n", + ret); + kfree(fb); + return ERR_PTR(ret); + } + + return fb; +} + +/** + * drm_gem_fb_destroy - Free GEM backed framebuffer + * @fb: DRM framebuffer + * + * Frees a GEM backed framebuffer with its backing buffer(s) and the structure + * itself. Drivers can use this as their &drm_framebuffer_funcs->destroy + * callback. + */ +void drm_gem_fb_destroy(struct drm_framebuffer *fb) +{ + int i; + + for (i = 0; i < 4; i++) + drm_gem_object_put_unlocked(fb->obj[i]); + + drm_framebuffer_cleanup(fb); + kfree(fb); +} +EXPORT_SYMBOL(drm_gem_fb_destroy); + +/** + * drm_gem_fb_create_handle - Create handle for GEM backed framebuffer + * @fb: DRM framebuffer + * @file: drm file + * @handle: handle created + * + * Drivers can use this as their &drm_framebuffer_funcs->create_handle + * callback. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle) +{ + return drm_gem_handle_create(file, fb->obj[0], handle); +} +EXPORT_SYMBOL(drm_gem_fb_create_handle); + +/** + * drm_gem_fb_create_with_funcs() - helper function for the + * &drm_mode_config_funcs.fb_create + * callback + * @dev: DRM device + * @file: drm file for the ioctl call + * @mode_cmd: metadata from the userspace fb creation request + * @funcs: vtable to be used for the new framebuffer object + * + * This can be used to set &drm_framebuffer_funcs for drivers that need the + * &drm_framebuffer_funcs.dirty callback. Use drm_gem_fb_create() if you don't + * need to change &drm_framebuffer_funcs. + * The function does buffer size validation. + */ +struct drm_framebuffer * +drm_gem_fb_create_with_funcs(struct drm_device *dev, struct drm_file *file, + const struct drm_mode_fb_cmd2 *mode_cmd, + const struct drm_framebuffer_funcs *funcs) +{ + const struct drm_format_info *info; + struct drm_gem_object *objs[4]; + struct drm_framebuffer *fb; + int ret, i; + + info = drm_get_format_info(dev, mode_cmd); + if (!info) + return ERR_PTR(-EINVAL); + + for (i = 0; i < info->num_planes; i++) { + unsigned int width = mode_cmd->width / (i ? info->hsub : 1); + unsigned int height = mode_cmd->height / (i ? info->vsub : 1); + unsigned int min_size; + + objs[i] = drm_gem_object_lookup(file, mode_cmd->handles[i]); + if (!objs[i]) { + DRM_DEV_ERROR(dev->dev, "Failed to lookup GEM\n"); + ret = -ENOENT; + goto err_gem_object_put; + } + + min_size = (height - 1) * mode_cmd->pitches[i] + + width * info->cpp[i] + + mode_cmd->offsets[i]; + + if (objs[i]->size < min_size) { + drm_gem_object_put_unlocked(objs[i]); + ret = -EINVAL; + goto err_gem_object_put; + } + } + + fb = drm_gem_fb_alloc(dev, mode_cmd, objs, i, funcs); + if (IS_ERR(fb)) { + ret = PTR_ERR(fb); + goto err_gem_object_put; + } + + return fb; + +err_gem_object_put: + for (i--; i >= 0; i--) + drm_gem_object_put_unlocked(objs[i]); + + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(drm_gem_fb_create_with_funcs); + +static const struct drm_framebuffer_funcs drm_gem_fb_funcs = { + .destroy = drm_gem_fb_destroy, + .create_handle = drm_gem_fb_create_handle, +}; + +/** + * drm_gem_fb_create() - &drm_mode_config_funcs.fb_create callback function + * @dev: DRM device + * @file: drm file for the ioctl call + * @mode_cmd: metadata from the userspace fb creation request + * + * If your hardware has special alignment or pitch requirements these should be + * checked before calling this function. The function does buffer size + * validation. Use drm_gem_fb_create_with_funcs() if you need to set + * &drm_framebuffer_funcs.dirty. + */ +struct drm_framebuffer * +drm_gem_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, + &drm_gem_fb_funcs); +} +EXPORT_SYMBOL_GPL(drm_gem_fb_create); + +/** + * drm_gem_fb_prepare_fb() - Prepare gem framebuffer + * @plane: Which plane + * @state: Plane state attach fence to + * + * This can be used as the &drm_plane_helper_funcs.prepare_fb hook. + * + * This function checks if the plane FB has an dma-buf attached, extracts + * the exclusive fence and attaches it to plane state for the atomic helper + * to wait on. + * + * There is no need for &drm_plane_helper_funcs.cleanup_fb hook for simple + * gem based framebuffer drivers which have their buffers always pinned in + * memory. + */ +int drm_gem_fb_prepare_fb(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct dma_buf *dma_buf; + struct dma_fence *fence; + + if ((plane->state->fb == state->fb) || !state->fb) + return 0; + + dma_buf = drm_gem_fb_get_obj(state->fb, 0)->dma_buf; + if (dma_buf) { + fence = reservation_object_get_excl_rcu(dma_buf->resv); + drm_atomic_set_fence_for_plane(state, fence); + } + + return 0; +} +EXPORT_SYMBOL_GPL(drm_gem_fb_prepare_fb); + +/** + * drm_gem_fbdev_fb_create - Create a drm_framebuffer for fbdev emulation + * @dev: DRM device + * @sizes: fbdev size description + * @pitch_align: optional pitch alignment + * @obj: GEM object backing the framebuffer + * @funcs: vtable to be used for the new framebuffer object + * + * This function creates a framebuffer for use with fbdev emulation. + * + * Returns: + * Pointer to a drm_framebuffer on success or an error pointer on failure. + */ +struct drm_framebuffer * +drm_gem_fbdev_fb_create(struct drm_device *dev, + struct drm_fb_helper_surface_size *sizes, + unsigned int pitch_align, struct drm_gem_object *obj, + const struct drm_framebuffer_funcs *funcs) +{ + struct drm_mode_fb_cmd2 mode_cmd = { 0 }; + + mode_cmd.width = sizes->surface_width; + mode_cmd.height = sizes->surface_height; + mode_cmd.pitches[0] = sizes->surface_width * + DIV_ROUND_UP(sizes->surface_bpp, 8); + if (pitch_align) + mode_cmd.pitches[0] = roundup(mode_cmd.pitches[0], + pitch_align); + mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, + sizes->surface_depth); + if (obj->size < mode_cmd.pitches[0] * mode_cmd.height) + return ERR_PTR(-EINVAL); + + return drm_gem_fb_alloc(dev, &mode_cmd, &obj, 1, funcs); +} +EXPORT_SYMBOL(drm_gem_fbdev_fb_create); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 8bfeb32f8a10..d920b2118a39 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -716,7 +716,7 @@ long drm_ioctl_kernel(struct file *file, drm_ioctl_t *func, void *kdata, struct drm_device *dev = file_priv->minor->dev; int retcode; - if (drm_device_is_unplugged(dev)) + if (drm_dev_is_unplugged(dev)) return -ENODEV; retcode = drm_ioctl_permit(flags, file_priv); @@ -765,7 +765,7 @@ long drm_ioctl(struct file *filp, dev = file_priv->minor->dev; - if (drm_device_is_unplugged(dev)) + if (drm_dev_is_unplugged(dev)) return -ENODEV; is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END; diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 5c14beee52ff..85ab1eec73e5 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -126,7 +126,7 @@ static int create_in_format_blob(struct drm_device *dev, struct drm_plane *plane plane->format_types[j], plane->modifiers[i])) { - mod->formats |= 1 << j; + mod->formats |= 1ULL << j; } } diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index 1170b3209a12..13a59ed2afbc 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -631,7 +631,7 @@ int drm_legacy_mmap(struct file *filp, struct vm_area_struct *vma) struct drm_device *dev = priv->minor->dev; int ret; - if (drm_device_is_unplugged(dev)) + if (drm_dev_is_unplugged(dev)) return -ENODEV; mutex_lock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig index 71cee4e9fefb..38b477b5fbf9 100644 --- a/drivers/gpu/drm/etnaviv/Kconfig +++ b/drivers/gpu/drm/etnaviv/Kconfig @@ -10,6 +10,8 @@ config DRM_ETNAVIV select IOMMU_API select IOMMU_SUPPORT select WANT_DEV_COREDUMP + select CMA if HAVE_DMA_CONTIGUOUS + select DMA_CMA if HAVE_DMA_CONTIGUOUS help DRM driver for Vivante GPUs. diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 91e17aeee1da..2cb4773823c2 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -316,7 +316,7 @@ static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, ret = etnaviv_gem_cpu_prep(obj, args->op, &TS(args->timeout)); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -337,7 +337,7 @@ static int etnaviv_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, ret = etnaviv_gem_cpu_fini(obj); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -357,7 +357,7 @@ static int etnaviv_ioctl_gem_info(struct drm_device *dev, void *data, return -ENOENT; ret = etnaviv_gem_mmap_offset(obj, &args->offset); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -446,7 +446,7 @@ static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data, ret = etnaviv_gem_wait_bo(gpu, obj, timeout); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c index 9a3bea738330..5a634594a6ce 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -68,7 +68,7 @@ static int etnaviv_gem_shmem_get_pages(struct etnaviv_gem_object *etnaviv_obj) struct page **p = drm_gem_get_pages(&etnaviv_obj->base); if (IS_ERR(p)) { - dev_err(dev->dev, "could not get pages: %ld\n", PTR_ERR(p)); + dev_dbg(dev->dev, "could not get pages: %ld\n", PTR_ERR(p)); return PTR_ERR(p); } @@ -265,7 +265,7 @@ void etnaviv_gem_mapping_reference(struct etnaviv_vram_mapping *mapping) { struct etnaviv_gem_object *etnaviv_obj = mapping->object; - drm_gem_object_reference(&etnaviv_obj->base); + drm_gem_object_get(&etnaviv_obj->base); mutex_lock(&etnaviv_obj->lock); WARN_ON(mapping->use == 0); @@ -282,7 +282,7 @@ void etnaviv_gem_mapping_unreference(struct etnaviv_vram_mapping *mapping) mapping->use -= 1; mutex_unlock(&etnaviv_obj->lock); - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); } struct etnaviv_vram_mapping *etnaviv_gem_mapping_get( @@ -358,7 +358,7 @@ out: return ERR_PTR(ret); /* Take a reference on the object */ - drm_gem_object_reference(obj); + drm_gem_object_get(obj); return mapping; } @@ -413,6 +413,16 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, bool write = !!(op & ETNA_PREP_WRITE); int ret; + if (!etnaviv_obj->sgt) { + void *ret; + + mutex_lock(&etnaviv_obj->lock); + ret = etnaviv_gem_get_pages(etnaviv_obj); + mutex_unlock(&etnaviv_obj->lock); + if (IS_ERR(ret)) + return PTR_ERR(ret); + } + if (op & ETNA_PREP_NOSYNC) { if (!reservation_object_test_signaled_rcu(etnaviv_obj->resv, write)) @@ -427,16 +437,6 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, } if (etnaviv_obj->flags & ETNA_BO_CACHED) { - if (!etnaviv_obj->sgt) { - void *ret; - - mutex_lock(&etnaviv_obj->lock); - ret = etnaviv_gem_get_pages(etnaviv_obj); - mutex_unlock(&etnaviv_obj->lock); - if (IS_ERR(ret)) - return PTR_ERR(ret); - } - dma_sync_sg_for_cpu(dev->dev, etnaviv_obj->sgt->sgl, etnaviv_obj->sgt->nents, etnaviv_op_to_dma_dir(op)); @@ -662,7 +662,8 @@ static struct drm_gem_object *__etnaviv_gem_new(struct drm_device *dev, * going to pin these pages. */ mapping = obj->filp->f_mapping; - mapping_set_gfp_mask(mapping, GFP_HIGHUSER); + mapping_set_gfp_mask(mapping, GFP_HIGHUSER | + __GFP_RETRY_MAYFAIL | __GFP_NOWARN); } if (ret) @@ -671,7 +672,7 @@ static struct drm_gem_object *__etnaviv_gem_new(struct drm_device *dev, return obj; fail: - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(ret); } @@ -688,14 +689,14 @@ int etnaviv_gem_new_handle(struct drm_device *dev, struct drm_file *file, ret = etnaviv_gem_obj_add(dev, obj); if (ret < 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } ret = drm_gem_handle_create(file, obj, handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -712,7 +713,7 @@ struct drm_gem_object *etnaviv_gem_new(struct drm_device *dev, ret = etnaviv_gem_obj_add(dev, obj); if (ret < 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(ret); } @@ -800,7 +801,7 @@ static void __etnaviv_gem_userptr_get_pages(struct work_struct *_work) } mutex_unlock(&etnaviv_obj->lock); - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); mmput(work->mm); put_task_struct(work->task); @@ -858,7 +859,7 @@ static int etnaviv_gem_userptr_get_pages(struct etnaviv_gem_object *etnaviv_obj) } get_task_struct(current); - drm_gem_object_reference(&etnaviv_obj->base); + drm_gem_object_get(&etnaviv_obj->base); work->mm = mm; work->task = current; @@ -924,6 +925,6 @@ int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file, ret = drm_gem_handle_create(file, &etnaviv_obj->base, handle); unreference: /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); return ret; } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index e5da4f2300ba..ae884723e9b1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -146,7 +146,7 @@ struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device *dev, return &etnaviv_obj->base; fail: - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c index 6463fc2c736f..a7ff2e4c00d2 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c @@ -88,7 +88,7 @@ static int submit_lookup_objects(struct etnaviv_gem_submit *submit, * Take a refcount on the object. The file table lock * prevents the object_idr's refcount on this being dropped. */ - drm_gem_object_reference(obj); + drm_gem_object_get(obj); submit->bos[i].obj = to_etnaviv_bo(obj); } @@ -291,7 +291,7 @@ static void submit_cleanup(struct etnaviv_gem_submit *submit) struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj; submit_unlock_object(submit, i); - drm_gem_object_unreference_unlocked(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); } ww_acquire_fini(&submit->ticket); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index ada45fdd0eae..fc9a6a83dfc7 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1622,10 +1622,12 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master, struct etnaviv_gpu *gpu = dev_get_drvdata(dev); int ret; - gpu->cooling = thermal_of_cooling_device_register(dev->of_node, + if (IS_ENABLED(CONFIG_THERMAL)) { + gpu->cooling = thermal_of_cooling_device_register(dev->of_node, (char *)dev_name(dev), gpu, &cooling_ops); - if (IS_ERR(gpu->cooling)) - return PTR_ERR(gpu->cooling); + if (IS_ERR(gpu->cooling)) + return PTR_ERR(gpu->cooling); + } #ifdef CONFIG_PM ret = pm_runtime_get_sync(gpu->dev); diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index facc8419f0cd..b1f7299600f0 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -145,8 +145,6 @@ static struct drm_driver exynos_drm_driver = { .gem_free_object_unlocked = exynos_drm_gem_free_object, .gem_vm_ops = &exynos_drm_gem_vm_ops, .dumb_create = exynos_drm_gem_dumb_create, - .dumb_map_offset = exynos_drm_gem_dumb_map_offset, - .dumb_destroy = drm_gem_dumb_destroy, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_export = drm_gem_prime_export, diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index c23479be4850..077de014d610 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -286,8 +286,8 @@ int exynos_drm_gem_map_ioctl(struct drm_device *dev, void *data, { struct drm_exynos_gem_map *args = data; - return exynos_drm_gem_dumb_map_offset(file_priv, dev, args->handle, - &args->offset); + return drm_gem_dumb_map_offset(file_priv, dev, args->handle, + &args->offset); } dma_addr_t *exynos_drm_gem_get_dma_addr(struct drm_device *dev, @@ -422,32 +422,6 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv, return 0; } -int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv, - struct drm_device *dev, uint32_t handle, - uint64_t *offset) -{ - struct drm_gem_object *obj; - int ret = 0; - - /* - * get offset of memory allocated for drm framebuffer. - * - this callback would be called by user application - * with DRM_IOCTL_MODE_MAP_DUMB command. - */ - - obj = drm_gem_object_lookup(file_priv, handle); - if (!obj) { - DRM_ERROR("failed to lookup gem object.\n"); - return -EINVAL; - } - - *offset = drm_vma_node_offset_addr(&obj->vma_node); - DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset); - - drm_gem_object_unreference_unlocked(obj); - return ret; -} - int exynos_drm_gem_fault(struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h index 85457255fcd1..e86d1a9518c3 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.h +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h @@ -110,11 +110,6 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args); -/* map memory region for drm framebuffer to user space. */ -int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv, - struct drm_device *dev, uint32_t handle, - uint64_t *offset); - /* page fault handler and mmap fault address(virtual) to physical memory. */ int exynos_drm_gem_fault(struct vm_fault *vmf); diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c index 7da061aab729..131239759a75 100644 --- a/drivers/gpu/drm/gma500/gem.c +++ b/drivers/gpu/drm/gma500/gem.c @@ -48,36 +48,6 @@ int psb_gem_get_aperture(struct drm_device *dev, void *data, } /** - * psb_gem_dumb_map_gtt - buffer mapping for dumb interface - * @file: our drm client file - * @dev: drm device - * @handle: GEM handle to the object (from dumb_create) - * - * Do the necessary setup to allow the mapping of the frame buffer - * into user memory. We don't have to do much here at the moment. - */ -int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev, - uint32_t handle, uint64_t *offset) -{ - int ret = 0; - struct drm_gem_object *obj; - - /* GEM does all our handle to object mapping */ - obj = drm_gem_object_lookup(file, handle); - if (obj == NULL) - return -ENOENT; - - /* Make it mmapable */ - ret = drm_gem_create_mmap_offset(obj); - if (ret) - goto out; - *offset = drm_vma_node_offset_addr(&obj->vma_node); -out: - drm_gem_object_unreference_unlocked(obj); - return ret; -} - -/** * psb_gem_create - create a mappable object * @file: the DRM file of the client * @dev: our device diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c index 1616af209bfc..c50534c923df 100644 --- a/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c +++ b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c @@ -520,7 +520,7 @@ static int __read_panel_data(struct mdfld_dsi_pkg_sender *sender, u8 data_type, u8 *data, u16 len, u32 *data_out, u16 len_out, bool hs) { unsigned long flags; - struct drm_device *dev = sender->dev; + struct drm_device *dev; int i; u32 gen_data_reg; int retry = MDFLD_DSI_READ_MAX_COUNT; @@ -530,6 +530,8 @@ static int __read_panel_data(struct mdfld_dsi_pkg_sender *sender, u8 data_type, return -EINVAL; } + dev = sender->dev; + /** * do reading. * 0) send out generic read request diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c index 747c06b227c5..37a3be71acd9 100644 --- a/drivers/gpu/drm/gma500/psb_drv.c +++ b/drivers/gpu/drm/gma500/psb_drv.c @@ -494,8 +494,6 @@ static struct drm_driver driver = { .gem_vm_ops = &psb_gem_vm_ops, .dumb_create = psb_gem_dumb_create, - .dumb_map_offset = psb_gem_dumb_map_gtt, - .dumb_destroy = drm_gem_dumb_destroy, .ioctls = psb_ioctls, .fops = &psb_gem_fops, .name = DRIVER_NAME, diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h index 83667087d6e5..821497dbd3fc 100644 --- a/drivers/gpu/drm/gma500/psb_drv.h +++ b/drivers/gpu/drm/gma500/psb_drv.h @@ -750,8 +750,6 @@ extern int psb_gem_get_aperture(struct drm_device *dev, void *data, struct drm_file *file); extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, struct drm_mode_create_dumb *args); -extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev, - uint32_t handle, uint64_t *offset); extern int psb_gem_fault(struct vm_fault *vmf); /* psb_device.c */ diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c index 9740eed9231a..b92595c477ef 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c @@ -157,7 +157,7 @@ out_unpin_bo: out_unreserve_ttm_bo: ttm_bo_unreserve(&bo->bo); out_unref_gem: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return ret; } @@ -172,7 +172,7 @@ static void hibmc_fbdev_destroy(struct hibmc_fbdev *fbdev) drm_fb_helper_fini(fbh); if (gfb) - drm_framebuffer_unreference(&gfb->fb); + drm_framebuffer_put(&gfb->fb); } static const struct drm_fb_helper_funcs hibmc_fbdev_helper_funcs = { diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c index ac457c779caa..3518167a7dc4 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c @@ -444,7 +444,7 @@ int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev, } ret = drm_gem_handle_create(file, gobj, &handle); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (ret) { DRM_ERROR("failed to unreference GEM object: %d\n", ret); return ret; @@ -479,7 +479,7 @@ int hibmc_dumb_mmap_offset(struct drm_file *file, struct drm_device *dev, bo = gem_to_hibmc_bo(obj); *offset = hibmc_bo_mmap_offset(bo); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return 0; } @@ -487,7 +487,7 @@ static void hibmc_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct hibmc_framebuffer *hibmc_fb = to_hibmc_framebuffer(fb); - drm_gem_object_unreference_unlocked(hibmc_fb->obj); + drm_gem_object_put_unlocked(hibmc_fb->obj); drm_framebuffer_cleanup(fb); kfree(hibmc_fb); } @@ -543,7 +543,7 @@ hibmc_user_framebuffer_create(struct drm_device *dev, hibmc_fb = hibmc_framebuffer_init(dev, mode_cmd, obj); if (IS_ERR(hibmc_fb)) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR((long)hibmc_fb); } return &hibmc_fb->fb; diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c index 79fcce76f2ad..e27352ca26c4 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -157,8 +157,6 @@ static struct drm_driver kirin_drm_driver = { .gem_free_object_unlocked = drm_gem_cma_free_object, .gem_vm_ops = &drm_gem_cma_vm_ops, .dumb_create = kirin_gem_cma_dumb_create, - .dumb_map_offset = drm_gem_cma_dumb_map_offset, - .dumb_destroy = drm_gem_dumb_destroy, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 78c5c049a347..aed7d207ea84 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -25,6 +25,7 @@ config DRM_I915_DEBUG select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks) select DRM_DEBUG_MM if DRM=y select DRM_DEBUG_MM_SELFTEST + select SW_SYNC # signaling validation framework (igt/syncobj*) select DRM_I915_SW_FENCE_DEBUG_OBJECTS select DRM_I915_SELFTEST default n diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index f8227318dcaf..892f52b53060 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -39,6 +39,7 @@ i915-y += i915_cmd_parser.o \ i915_gem_gtt.o \ i915_gem_internal.o \ i915_gem.o \ + i915_gem_object.o \ i915_gem_render_state.o \ i915_gem_request.o \ i915_gem_shrinker.o \ diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c index 325618d969fe..ca3d1925beda 100644 --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c @@ -285,8 +285,8 @@ static int alloc_resource(struct intel_vgpu *vgpu, return 0; no_enough_resource: - gvt_vgpu_err("fail to allocate resource %s\n", item); - gvt_vgpu_err("request %luMB avail %luMB max %luMB taken %luMB\n", + gvt_err("fail to allocate resource %s\n", item); + gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n", BYTES_TO_MB(request), BYTES_TO_MB(avail), BYTES_TO_MB(max), BYTES_TO_MB(taken)); return -ENOSPC; diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 713848c36349..72b97ce525e8 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1382,13 +1382,13 @@ static inline int cmd_address_audit(struct parser_exec_state *s, ret = -EINVAL; goto err; } - } else if ((!vgpu_gmadr_is_valid(s->vgpu, guest_gma)) || - (!vgpu_gmadr_is_valid(s->vgpu, - guest_gma + op_size - 1))) { + } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) { ret = -EINVAL; goto err; } + return 0; + err: gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n", s->info->name, guest_gma, op_size); @@ -2647,7 +2647,7 @@ static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload) return 0; } -int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) +int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload) { int ret; struct intel_vgpu *vgpu = workload->vgpu; diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.h b/drivers/gpu/drm/i915/gvt/cmd_parser.h index bed33514103c..286703643002 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.h +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.h @@ -42,7 +42,7 @@ void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt); int intel_gvt_init_cmd_parser(struct intel_gvt *gvt); -int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); +int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload); int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx); diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 7cb0818a13de..3c318439a659 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -178,9 +178,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTE_HOTPLUG_SPT); vgpu_vreg(vgpu, SKL_FUSE_STATUS) |= SKL_FUSE_DOWNLOAD_STATUS | - SKL_FUSE_PG0_DIST_STATUS | - SKL_FUSE_PG1_DIST_STATUS | - SKL_FUSE_PG2_DIST_STATUS; + SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | + SKL_FUSE_PG_DIST_STATUS(SKL_PG2); vgpu_vreg(vgpu, LCPLL1_CTL) |= LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index 1648887d3f55..91b4300f3b39 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -622,6 +622,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, struct list_head *q = workload_q_head(vgpu, ring_id); struct intel_vgpu_workload *last_workload = get_last_workload(q); struct intel_vgpu_workload *workload = NULL; + struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; u64 ring_context_gpa; u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; int ret; @@ -685,6 +686,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, workload->complete = complete_execlist_workload; workload->status = -EINPROGRESS; workload->emulate_schedule_in = emulate_schedule_in; + workload->shadowed = false; if (ring_id == RCS) { intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + @@ -718,6 +720,17 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, return ret; } + /* Only scan and shadow the first workload in the queue + * as there is only one pre-allocated buf-obj for shadow. + */ + if (list_empty(workload_q_head(vgpu, ring_id))) { + intel_runtime_pm_get(dev_priv); + mutex_lock(&dev_priv->drm.struct_mutex); + intel_gvt_scan_and_shadow_workload(workload); + mutex_unlock(&dev_priv->drm.struct_mutex); + intel_runtime_pm_put(dev_priv); + } + queue_workload(workload); return 0; } @@ -800,6 +813,8 @@ static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask) list_del_init(&pos->list); free_workload(pos); } + + clear_bit(engine->id, vgpu->shadow_ctx_desc_updated); } } diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 6166e34d892b..e6dfc3331f4b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -259,7 +259,7 @@ static void write_pte64(struct drm_i915_private *dev_priv, writeq(pte, addr); } -static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, +static inline int gtt_get_entry64(void *pt, struct intel_gvt_gtt_entry *e, unsigned long index, bool hypervisor_access, unsigned long gpa, struct intel_vgpu *vgpu) @@ -268,22 +268,23 @@ static inline struct intel_gvt_gtt_entry *gtt_get_entry64(void *pt, int ret; if (WARN_ON(info->gtt_entry_size != 8)) - return e; + return -EINVAL; if (hypervisor_access) { ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa + (index << info->gtt_entry_size_shift), &e->val64, 8); - WARN_ON(ret); + if (WARN_ON(ret)) + return ret; } else if (!pt) { e->val64 = read_pte64(vgpu->gvt->dev_priv, index); } else { e->val64 = *((u64 *)pt + index); } - return e; + return 0; } -static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, +static inline int gtt_set_entry64(void *pt, struct intel_gvt_gtt_entry *e, unsigned long index, bool hypervisor_access, unsigned long gpa, struct intel_vgpu *vgpu) @@ -292,19 +293,20 @@ static inline struct intel_gvt_gtt_entry *gtt_set_entry64(void *pt, int ret; if (WARN_ON(info->gtt_entry_size != 8)) - return e; + return -EINVAL; if (hypervisor_access) { ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa + (index << info->gtt_entry_size_shift), &e->val64, 8); - WARN_ON(ret); + if (WARN_ON(ret)) + return ret; } else if (!pt) { write_pte64(vgpu->gvt->dev_priv, index, e->val64); } else { *((u64 *)pt + index) = e->val64; } - return e; + return 0; } #define GTT_HAW 46 @@ -445,21 +447,25 @@ static int gtt_entry_p2m(struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *p, /* * MM helpers. */ -struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, +int intel_vgpu_mm_get_entry(struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index) { struct intel_gvt *gvt = mm->vgpu->gvt; struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; + int ret; e->type = mm->page_table_entry_type; - ops->get_entry(page_table, e, index, false, 0, mm->vgpu); + ret = ops->get_entry(page_table, e, index, false, 0, mm->vgpu); + if (ret) + return ret; + ops->test_pse(e); - return e; + return 0; } -struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, +int intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index) { @@ -472,7 +478,7 @@ struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry(struct intel_vgpu_mm *mm, /* * PPGTT shadow page table helpers. */ -static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( +static inline int ppgtt_spt_get_entry( struct intel_vgpu_ppgtt_spt *spt, void *page_table, int type, struct intel_gvt_gtt_entry *e, unsigned long index, @@ -480,20 +486,24 @@ static inline struct intel_gvt_gtt_entry *ppgtt_spt_get_entry( { struct intel_gvt *gvt = spt->vgpu->gvt; struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; + int ret; e->type = get_entry_type(type); if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) - return e; + return -EINVAL; - ops->get_entry(page_table, e, index, guest, + ret = ops->get_entry(page_table, e, index, guest, spt->guest_page.gfn << GTT_PAGE_SHIFT, spt->vgpu); + if (ret) + return ret; + ops->test_pse(e); - return e; + return 0; } -static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( +static inline int ppgtt_spt_set_entry( struct intel_vgpu_ppgtt_spt *spt, void *page_table, int type, struct intel_gvt_gtt_entry *e, unsigned long index, @@ -503,7 +513,7 @@ static inline struct intel_gvt_gtt_entry *ppgtt_spt_set_entry( struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n")) - return e; + return -EINVAL; return ops->set_entry(page_table, e, index, guest, spt->guest_page.gfn << GTT_PAGE_SHIFT, @@ -792,13 +802,13 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_find_shadow_page( #define for_each_present_guest_entry(spt, e, i) \ for (i = 0; i < pt_entries(spt); i++) \ - if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ - ppgtt_get_guest_entry(spt, e, i))) + if (!ppgtt_get_guest_entry(spt, e, i) && \ + spt->vgpu->gvt->gtt.pte_ops->test_present(e)) #define for_each_present_shadow_entry(spt, e, i) \ for (i = 0; i < pt_entries(spt); i++) \ - if (spt->vgpu->gvt->gtt.pte_ops->test_present( \ - ppgtt_get_shadow_entry(spt, e, i))) + if (!ppgtt_get_shadow_entry(spt, e, i) && \ + spt->vgpu->gvt->gtt.pte_ops->test_present(e)) static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt *spt) { @@ -979,29 +989,26 @@ fail: } static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, - unsigned long index) + struct intel_gvt_gtt_entry *se, unsigned long index) { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu_shadow_page *sp = &spt->shadow_page; struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; - struct intel_gvt_gtt_entry e; int ret; - ppgtt_get_shadow_entry(spt, &e, index); - - trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, e.val64, + trace_gpt_change(spt->vgpu->id, "remove", spt, sp->type, se->val64, index); - if (!ops->test_present(&e)) + if (!ops->test_present(se)) return 0; - if (ops->get_pfn(&e) == vgpu->gtt.scratch_pt[sp->type].page_mfn) + if (ops->get_pfn(se) == vgpu->gtt.scratch_pt[sp->type].page_mfn) return 0; - if (gtt_type_is_pt(get_next_pt_type(e.type))) { + if (gtt_type_is_pt(get_next_pt_type(se->type))) { struct intel_vgpu_ppgtt_spt *s = - ppgtt_find_shadow_page(vgpu, ops->get_pfn(&e)); + ppgtt_find_shadow_page(vgpu, ops->get_pfn(se)); if (!s) { gvt_vgpu_err("fail to find guest page\n"); ret = -ENXIO; @@ -1011,12 +1018,10 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page *gpt, if (ret) goto fail; } - ops->set_pfn(&e, vgpu->gtt.scratch_pt[sp->type].page_mfn); - ppgtt_set_shadow_entry(spt, &e, index); return 0; fail: gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n", - spt, e.val64, e.type); + spt, se->val64, se->type); return ret; } @@ -1236,22 +1241,37 @@ static int ppgtt_handle_guest_write_page_table( { struct intel_vgpu_ppgtt_spt *spt = guest_page_to_ppgtt_spt(gpt); struct intel_vgpu *vgpu = spt->vgpu; + int type = spt->shadow_page.type; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; + struct intel_gvt_gtt_entry se; int ret; int new_present; new_present = ops->test_present(we); - ret = ppgtt_handle_guest_entry_removal(gpt, index); - if (ret) - goto fail; + /* + * Adding the new entry first and then removing the old one, that can + * guarantee the ppgtt table is validated during the window between + * adding and removal. + */ + ppgtt_get_shadow_entry(spt, &se, index); if (new_present) { ret = ppgtt_handle_guest_entry_add(gpt, we, index); if (ret) goto fail; } + + ret = ppgtt_handle_guest_entry_removal(gpt, &se, index); + if (ret) + goto fail; + + if (!new_present) { + ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn); + ppgtt_set_shadow_entry(spt, &se, index); + } + return 0; fail: gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n", @@ -1323,7 +1343,7 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, struct intel_vgpu *vgpu = spt->vgpu; struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; - struct intel_gvt_gtt_entry we; + struct intel_gvt_gtt_entry we, se; unsigned long index; int ret; @@ -1339,7 +1359,8 @@ static int ppgtt_handle_guest_write_page_table_bytes(void *gp, return ret; } else { if (!test_bit(index, spt->post_shadow_bitmap)) { - ret = ppgtt_handle_guest_entry_removal(gpt, index); + ppgtt_get_shadow_entry(spt, &se, index); + ret = ppgtt_handle_guest_entry_removal(gpt, &se, index); if (ret) return ret; } @@ -1713,8 +1734,10 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) if (!vgpu_gmadr_is_valid(vgpu, gma)) goto err; - ggtt_get_guest_entry(mm, &e, - gma_ops->gma_to_ggtt_pte_index(gma)); + ret = ggtt_get_guest_entry(mm, &e, + gma_ops->gma_to_ggtt_pte_index(gma)); + if (ret) + goto err; gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) + (gma & ~GTT_PAGE_MASK); @@ -1724,7 +1747,9 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) switch (mm->page_table_level) { case 4: - ppgtt_get_shadow_root_entry(mm, &e, 0); + ret = ppgtt_get_shadow_root_entry(mm, &e, 0); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pml4_index(gma); gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma); gma_index[2] = gma_ops->gma_to_pde_index(gma); @@ -1732,15 +1757,19 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) index = 4; break; case 3: - ppgtt_get_shadow_root_entry(mm, &e, + ret = ppgtt_get_shadow_root_entry(mm, &e, gma_ops->gma_to_l3_pdp_index(gma)); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pde_index(gma); gma_index[1] = gma_ops->gma_to_pte_index(gma); index = 2; break; case 2: - ppgtt_get_shadow_root_entry(mm, &e, + ret = ppgtt_get_shadow_root_entry(mm, &e, gma_ops->gma_to_pde_index(gma)); + if (ret) + goto err; gma_index[0] = gma_ops->gma_to_pte_index(gma); index = 1; break; @@ -1755,6 +1784,11 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma) (i == index - 1)); if (ret) goto err; + + if (!pte_ops->test_present(&e)) { + gvt_dbg_core("GMA 0x%lx is not present\n", gma); + goto err; + } } gpa = (pte_ops->get_pfn(&e) << GTT_PAGE_SHIFT) @@ -2329,13 +2363,12 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu) /** * intel_vgpu_reset_gtt - reset the all GTT related status * @vgpu: a vGPU - * @dmlr: true for vGPU Device Model Level Reset, false for GT Reset * * This function is called from vfio core to reset reset all * GTT related status, including GGTT, PPGTT, scratch page. * */ -void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) +void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu) { int i; @@ -2347,9 +2380,6 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) */ intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT); - if (!dmlr) - return; - intel_vgpu_reset_ggtt(vgpu); /* clear scratch page for security */ diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index f88eb5e89bea..30a4c8d16026 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -49,14 +49,18 @@ struct intel_gvt_gtt_entry { }; struct intel_gvt_gtt_pte_ops { - struct intel_gvt_gtt_entry *(*get_entry)(void *pt, - struct intel_gvt_gtt_entry *e, - unsigned long index, bool hypervisor_access, unsigned long gpa, - struct intel_vgpu *vgpu); - struct intel_gvt_gtt_entry *(*set_entry)(void *pt, - struct intel_gvt_gtt_entry *e, - unsigned long index, bool hypervisor_access, unsigned long gpa, - struct intel_vgpu *vgpu); + int (*get_entry)(void *pt, + struct intel_gvt_gtt_entry *e, + unsigned long index, + bool hypervisor_access, + unsigned long gpa, + struct intel_vgpu *vgpu); + int (*set_entry)(void *pt, + struct intel_gvt_gtt_entry *e, + unsigned long index, + bool hypervisor_access, + unsigned long gpa, + struct intel_vgpu *vgpu); bool (*test_present)(struct intel_gvt_gtt_entry *e); void (*clear_present)(struct intel_gvt_gtt_entry *e); bool (*test_pse)(struct intel_gvt_gtt_entry *e); @@ -143,12 +147,12 @@ struct intel_vgpu_mm { struct intel_vgpu *vgpu; }; -extern struct intel_gvt_gtt_entry *intel_vgpu_mm_get_entry( +extern int intel_vgpu_mm_get_entry( struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index); -extern struct intel_gvt_gtt_entry *intel_vgpu_mm_set_entry( +extern int intel_vgpu_mm_set_entry( struct intel_vgpu_mm *mm, void *page_table, struct intel_gvt_gtt_entry *e, unsigned long index); @@ -208,7 +212,7 @@ extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu); extern int intel_gvt_init_gtt(struct intel_gvt *gvt); -extern void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr); +void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 2964a4d01a66..44b719eda8c4 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -167,6 +167,7 @@ struct intel_vgpu { atomic_t running_workload_num; DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); struct i915_gem_context *shadow_ctx; + DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) struct { @@ -482,6 +483,8 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); void populate_pvinfo_page(struct intel_vgpu *vgpu); +int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); + struct intel_gvt_ops { int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, unsigned int); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index feed9921b3b3..3502a59166ff 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -113,9 +113,17 @@ static int new_mmio_info(struct intel_gvt *gvt, info->offset = i; p = find_mmio_info(gvt, info->offset); - if (p) - gvt_err("dup mmio definition offset %x\n", + if (p) { + WARN(1, "dup mmio definition offset %x\n", info->offset); + kfree(info); + + /* We return -EEXIST here to make GVT-g load fail. + * So duplicated MMIO can be found as soon as + * possible. + */ + return -EEXIST; + } info->ro_mask = ro_mask; info->device = device; @@ -1222,10 +1230,12 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, { write_vreg(vgpu, offset, p_data, bytes); - if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST) - vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED; + if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) + vgpu_vreg(vgpu, offset) |= + HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); else - vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED; + vgpu_vreg(vgpu, offset) &= + ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); return 0; } @@ -2242,10 +2252,17 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); MMIO_D(GEN6_PMINTRMSK, D_ALL); - MMIO_DH(HSW_PWR_WELL_BIOS, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_DRIVER, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); - MMIO_DH(HSW_PWR_WELL_DEBUG, D_BDW, NULL, power_well_ctl_mmio_write); + /* + * Use an arbitrary power well controlled by the PWR_WELL_CTL + * register. + */ + MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); + MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, + power_well_ctl_mmio_write); MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); @@ -2581,7 +2598,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, force_nonpriv_write); - MMIO_D(0x22040, D_BDW_PLUS); MMIO_D(0x44484, D_BDW_PLUS); MMIO_D(0x4448c, D_BDW_PLUS); @@ -2636,9 +2652,13 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, dp_aux_ch_ctl_mmio_write); - MMIO_D(HSW_PWR_WELL_BIOS, D_SKL_PLUS); - MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL_PLUS, NULL, - skl_power_well_ctl_write); + /* + * Use an arbitrary power well controlled by the PWR_WELL_CTL + * register. + */ + MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); + MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, + skl_power_well_ctl_write); MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write); MMIO_D(0xa210, D_SKL_PLUS); @@ -2831,7 +2851,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_D(0x320f0, D_SKL | D_KBL); MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); - MMIO_DFH(_REG_VECS_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); MMIO_D(0x70034, D_SKL_PLUS); MMIO_D(0x71034, D_SKL_PLUS); MMIO_D(0x72034, D_SKL_PLUS); @@ -2849,10 +2868,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) NULL, NULL); MMIO_D(0x4ab8, D_KBL); - MMIO_D(0x940c, D_SKL_PLUS); MMIO_D(0x2248, D_SKL_PLUS | D_KBL); - MMIO_D(0x4ab0, D_SKL | D_KBL); - MMIO_D(0x20d4, D_SKL | D_KBL); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index fd0c85f9ef3c..83e88c70272a 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -1170,10 +1170,27 @@ vgpu_id_show(struct device *dev, struct device_attribute *attr, return sprintf(buf, "\n"); } +static ssize_t +hw_id_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mdev_device *mdev = mdev_from_dev(dev); + + if (mdev) { + struct intel_vgpu *vgpu = (struct intel_vgpu *) + mdev_get_drvdata(mdev); + return sprintf(buf, "%u\n", + vgpu->shadow_ctx->hw_id); + } + return sprintf(buf, "\n"); +} + static DEVICE_ATTR_RO(vgpu_id); +static DEVICE_ATTR_RO(hw_id); static struct attribute *intel_vgpu_attrs[] = { &dev_attr_vgpu_id.attr, + &dev_attr_hw_id.attr, NULL }; diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 504e57c3bc23..2ea542257f03 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -207,18 +207,16 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { - gen9_render_mocs[ring_id][i] = I915_READ(offset); + gen9_render_mocs[ring_id][i] = I915_READ_FW(offset); I915_WRITE(offset, vgpu_vreg(vgpu, offset)); - POSTING_READ(offset); offset.reg += 4; } if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - gen9_render_mocs_L3[i] = I915_READ(l3_offset); - I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset)); - POSTING_READ(l3_offset); + gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset); + I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset)); l3_offset.reg += 4; } } @@ -242,18 +240,16 @@ static void restore_mocs(struct intel_vgpu *vgpu, int ring_id) offset.reg = regs[ring_id]; for (i = 0; i < 64; i++) { - vgpu_vreg(vgpu, offset) = I915_READ(offset); - I915_WRITE(offset, gen9_render_mocs[ring_id][i]); - POSTING_READ(offset); + vgpu_vreg(vgpu, offset) = I915_READ_FW(offset); + I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]); offset.reg += 4; } if (ring_id == RCS) { l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { - vgpu_vreg(vgpu, l3_offset) = I915_READ(l3_offset); - I915_WRITE(l3_offset, gen9_render_mocs_L3[i]); - POSTING_READ(l3_offset); + vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset); + I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]); l3_offset.reg += 4; } } @@ -272,6 +268,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL]; u32 inhibit_mask = _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + i915_reg_t last_reg = _MMIO(0); if (IS_SKYLAKE(vgpu->gvt->dev_priv) || IS_KABYLAKE(vgpu->gvt->dev_priv)) { @@ -287,7 +284,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) if (mmio->ring_id != ring_id) continue; - mmio->value = I915_READ(mmio->reg); + mmio->value = I915_READ_FW(mmio->reg); /* * if it is an inhibit context, load in_context mmio @@ -304,13 +301,18 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id) else v = vgpu_vreg(vgpu, mmio->reg); - I915_WRITE(mmio->reg, v); - POSTING_READ(mmio->reg); + I915_WRITE_FW(mmio->reg, v); + last_reg = mmio->reg; trace_render_mmio(vgpu->id, "load", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } + + /* Make sure the swiched MMIOs has taken effect. */ + if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + I915_READ_FW(last_reg); + handle_tlb_pending_event(vgpu, ring_id); } @@ -319,6 +321,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; struct render_mmio *mmio; + i915_reg_t last_reg = _MMIO(0); u32 v; int i, array_size; @@ -335,7 +338,7 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) if (mmio->ring_id != ring_id) continue; - vgpu_vreg(vgpu, mmio->reg) = I915_READ(mmio->reg); + vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg); if (mmio->mask) { vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16); @@ -346,13 +349,17 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) if (mmio->in_context) continue; - I915_WRITE(mmio->reg, v); - POSTING_READ(mmio->reg); + I915_WRITE_FW(mmio->reg, v); + last_reg = mmio->reg; trace_render_mmio(vgpu->id, "restore", i915_mmio_reg_offset(mmio->reg), mmio->value, v); } + + /* Make sure the swiched MMIOs has taken effect. */ + if (likely(INTEL_GVT_MMIO_OFFSET(last_reg))) + I915_READ_FW(last_reg); } /** @@ -367,12 +374,23 @@ static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id) void intel_gvt_switch_mmio(struct intel_vgpu *pre, struct intel_vgpu *next, int ring_id) { + struct drm_i915_private *dev_priv; + if (WARN_ON(!pre && !next)) return; gvt_dbg_render("switch ring %d from %s to %s\n", ring_id, pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); + dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; + + /** + * We are using raw mmio access wrapper to improve the + * performace for batch mmio read/write, so we need + * handle forcewake mannually. + */ + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + /** * TODO: Optimize for vGPU to vGPU switch by merging * switch_mmio_to_host() and switch_mmio_to_vgpu(). @@ -382,4 +400,6 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, if (next) switch_mmio_to_vgpu(next, ring_id); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index c873136add97..391800d2067b 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -184,41 +184,52 @@ static int shadow_context_status_change(struct notifier_block *nb, return NOTIFY_OK; } -static int dispatch_workload(struct intel_vgpu_workload *workload) +static void shadow_context_descriptor_update(struct i915_gem_context *ctx, + struct intel_engine_cs *engine) +{ + struct intel_context *ce = &ctx->engine[engine->id]; + u64 desc = 0; + + desc = ce->lrc_desc; + + /* Update bits 0-11 of the context descriptor which includes flags + * like GEN8_CTX_* cached in desc_template + */ + desc &= U64_MAX << 12; + desc |= ctx->desc_template & ((1ULL << 12) - 1); + + ce->lrc_desc = desc; +} + +/** + * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and + * shadow it as well, include ringbuffer,wa_ctx and ctx. + * @workload: an abstract entity for each execlist submission. + * + * This function is called before the workload submitting to i915, to make + * sure the content of the workload is valid. + */ +int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) { int ring_id = workload->ring_id; struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; - struct intel_engine_cs *engine = dev_priv->engine[ring_id]; struct drm_i915_gem_request *rq; struct intel_vgpu *vgpu = workload->vgpu; - struct intel_ring *ring; int ret; - gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", - ring_id, workload); + lockdep_assert_held(&dev_priv->drm.struct_mutex); + + if (workload->shadowed) + return 0; shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - mutex_lock(&dev_priv->drm.struct_mutex); - - /* pin shadow context by gvt even the shadow context will be pinned - * when i915 alloc request. That is because gvt will update the guest - * context from shadow context when workload is completed, and at that - * moment, i915 may already unpined the shadow context to make the - * shadow_ctx pages invalid. So gvt need to pin itself. After update - * the guest context, gvt can unpin the shadow_ctx safely. - */ - ring = engine->context_pin(engine, shadow_ctx); - if (IS_ERR(ring)) { - ret = PTR_ERR(ring); - gvt_vgpu_err("fail to pin shadow context\n"); - workload->status = ret; - mutex_unlock(&dev_priv->drm.struct_mutex); - return ret; - } + if (!test_and_set_bit(ring_id, vgpu->shadow_ctx_desc_updated)) + shadow_context_descriptor_update(shadow_ctx, + dev_priv->engine[ring_id]); rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); if (IS_ERR(rq)) { @@ -231,7 +242,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) workload->req = i915_gem_request_get(rq); - ret = intel_gvt_scan_and_shadow_workload(workload); + ret = intel_gvt_scan_and_shadow_ringbuffer(workload); if (ret) goto out; @@ -246,25 +257,61 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) if (ret) goto out; + workload->shadowed = true; + +out: + return ret; +} + +static int dispatch_workload(struct intel_vgpu_workload *workload) +{ + int ring_id = workload->ring_id; + struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; + struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; + struct intel_engine_cs *engine = dev_priv->engine[ring_id]; + struct intel_vgpu *vgpu = workload->vgpu; + struct intel_ring *ring; + int ret = 0; + + gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", + ring_id, workload); + + mutex_lock(&dev_priv->drm.struct_mutex); + + ret = intel_gvt_scan_and_shadow_workload(workload); + if (ret) + goto out; + if (workload->prepare) { ret = workload->prepare(workload); if (ret) goto out; } - gvt_dbg_sched("ring id %d submit workload to i915 %p\n", - ring_id, workload->req); + /* pin shadow context by gvt even the shadow context will be pinned + * when i915 alloc request. That is because gvt will update the guest + * context from shadow context when workload is completed, and at that + * moment, i915 may already unpined the shadow context to make the + * shadow_ctx pages invalid. So gvt need to pin itself. After update + * the guest context, gvt can unpin the shadow_ctx safely. + */ + ring = engine->context_pin(engine, shadow_ctx); + if (IS_ERR(ring)) { + ret = PTR_ERR(ring); + gvt_vgpu_err("fail to pin shadow context\n"); + goto out; + } - ret = 0; - workload->dispatched = true; out: if (ret) workload->status = ret; - if (!IS_ERR_OR_NULL(rq)) - i915_add_request(rq); - else - engine->context_unpin(engine, shadow_ctx); + if (!IS_ERR_OR_NULL(workload->req)) { + gvt_dbg_sched("ring id %d submit workload to i915 %p\n", + ring_id, workload->req); + i915_add_request(workload->req); + workload->dispatched = true; + } mutex_unlock(&dev_priv->drm.struct_mutex); return ret; @@ -631,5 +678,7 @@ int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu) vgpu->shadow_ctx->engine[RCS].initialised = true; + bitmap_zero(vgpu->shadow_ctx_desc_updated, I915_NUM_ENGINES); + return 0; } diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h index 9b6bf51e9b9b..0d431a968a32 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.h +++ b/drivers/gpu/drm/i915/gvt/scheduler.h @@ -82,6 +82,7 @@ struct intel_vgpu_workload { struct drm_i915_gem_request *req; /* if this workload has been dispatched to i915? */ bool dispatched; + bool shadowed; int status; struct intel_vgpu_mm *shadow_mm; diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 3deadcbd5a24..02c61a1ad56a 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -43,6 +43,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; + vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT; vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = vgpu_aperture_gmadr_base(vgpu); vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = @@ -504,11 +505,11 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, /* full GPU reset or device model level reset */ if (engine_mask == ALL_ENGINES || dmlr) { - intel_vgpu_reset_gtt(vgpu, dmlr); - /*fence will not be reset during virtual reset */ - if (dmlr) + if (dmlr) { + intel_vgpu_reset_gtt(vgpu); intel_vgpu_reset_resource(vgpu); + } intel_vgpu_reset_mmio(vgpu, dmlr); populate_pvinfo_page(vgpu); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2ef75c1a6119..48572b157222 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -543,75 +543,6 @@ static int i915_gem_gtt_info(struct seq_file *m, void *data) return 0; } -static int i915_gem_pageflip_info(struct seq_file *m, void *data) -{ - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc; - int ret; - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - for_each_intel_crtc(dev, crtc) { - const char pipe = pipe_name(crtc->pipe); - const char plane = plane_name(crtc->plane); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = crtc->flip_work; - if (work == NULL) { - seq_printf(m, "No flip due on pipe %c (plane %c)\n", - pipe, plane); - } else { - u32 pending; - u32 addr; - - pending = atomic_read(&work->pending); - if (pending) { - seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", - pipe, plane); - } else { - seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", - pipe, plane); - } - if (work->flip_queued_req) { - struct intel_engine_cs *engine = work->flip_queued_req->engine; - - seq_printf(m, "Flip queued on %s at seqno %x, last submitted seqno %x [current breadcrumb %x], completed? %d\n", - engine->name, - work->flip_queued_req->global_seqno, - intel_engine_last_submit(engine), - intel_engine_get_seqno(engine), - i915_gem_request_completed(work->flip_queued_req)); - } else - seq_printf(m, "Flip not associated with any ring\n"); - seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", - work->flip_queued_vblank, - work->flip_ready_vblank, - intel_crtc_get_vblank_counter(crtc)); - seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); - - if (INTEL_GEN(dev_priv) >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); - else - addr = I915_READ(DSPADDR(crtc->plane)); - seq_printf(m, "Current scanout address 0x%08x\n", addr); - - if (work->pending_flip_obj) { - seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); - seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); - } - } - spin_unlock_irq(&dev->event_lock); - } - - mutex_unlock(&dev->struct_mutex); - - return 0; -} - static int i915_gem_batch_pool_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2023,12 +1954,6 @@ static int i915_context_status(struct seq_file *m, void *unused) seq_putc(m, '\n'); } - seq_printf(m, - "\tvma hashtable size=%u (actual %lu), count=%u\n", - ctx->vma_lut.ht_size, - BIT(ctx->vma_lut.ht_bits), - ctx->vma_lut.ht_count); - seq_putc(m, '\n'); } @@ -2852,7 +2777,7 @@ out: static int i915_energy_uJ(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - u64 power; + unsigned long long power; u32 units; if (INTEL_GEN(dev_priv) < 6) @@ -2860,15 +2785,18 @@ static int i915_energy_uJ(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); - rdmsrl(MSR_RAPL_POWER_UNIT, power); - power = (power & 0x1f00) >> 8; - units = 1000000 / (1 << power); /* convert to uJ */ + if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &power)) { + intel_runtime_pm_put(dev_priv); + return -ENODEV; + } + + units = (power & 0x1f00) >> 8; power = I915_READ(MCH_SECP_NRG_STTS); - power *= units; + power = (1000000 * power) >> units; /* convert to uJ */ intel_runtime_pm_put(dev_priv); - seq_printf(m, "%llu", (long long unsigned)power); + seq_printf(m, "%llu", power); return 0; } @@ -3394,8 +3322,10 @@ static int i915_engine_info(struct seq_file *m, void *unused) ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); read = GEN8_CSB_READ_PTR(ptr); write = GEN8_CSB_WRITE_PTR(ptr); - seq_printf(m, "\tExeclist CSB read %d, write %d\n", - read, write); + seq_printf(m, "\tExeclist CSB read %d, write %d, interrupt posted? %s\n", + read, write, + yesno(test_bit(ENGINE_IRQ_EXECLIST, + &engine->irq_posted))); if (read >= GEN8_CSB_ENTRIES) read = 0; if (write >= GEN8_CSB_ENTRIES) @@ -4624,7 +4554,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); - if (IS_GEN9_BC(dev_priv)) + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; @@ -4854,7 +4784,6 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_gem_gtt", i915_gem_gtt_info, 0}, {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, {"i915_gem_stolen", i915_gem_stolen_list_info }, - {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, {"i915_gem_request", i915_gem_request_info, 0}, {"i915_gem_seqno", i915_gem_seqno_info, 0}, {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4c96a7214482..43100229613c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -237,17 +237,17 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv) !IS_KABYLAKE(dev_priv)); } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_KBP; - DRM_DEBUG_KMS("Found KabyPoint PCH\n"); + DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n"); WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)); } else if (id == INTEL_PCH_CNP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CNP; - DRM_DEBUG_KMS("Found CannonPoint PCH\n"); + DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n"); WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CNP; - DRM_DEBUG_KMS("Found CannonPoint LP PCH\n"); + DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n"); WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv)); } else if (id == INTEL_PCH_P2X_DEVICE_ID_TYPE || @@ -388,6 +388,7 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_EXEC_FENCE: case I915_PARAM_HAS_EXEC_CAPTURE: case I915_PARAM_HAS_EXEC_BATCH_FIRST: + case I915_PARAM_HAS_EXEC_FENCE_ARRAY: /* For the time being all of these are always true; * if some supported hardware does not have one of these * features this value needs to be provided from @@ -596,7 +597,8 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { static void i915_gem_fini(struct drm_i915_private *dev_priv) { - flush_workqueue(dev_priv->wq); + /* Flush any outstanding unpin_work. */ + i915_gem_drain_workqueue(dev_priv); mutex_lock(&dev_priv->drm.struct_mutex); intel_uc_fini_hw(dev_priv); @@ -875,7 +877,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, spin_lock_init(&dev_priv->uncore.lock); spin_lock_init(&dev_priv->mm.object_stat_lock); - spin_lock_init(&dev_priv->mmio_flip_lock); mutex_init(&dev_priv->sb_lock); mutex_init(&dev_priv->modeset_restore_lock); mutex_init(&dev_priv->av_mutex); @@ -1240,6 +1241,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) */ static void i915_driver_unregister(struct drm_i915_private *dev_priv) { + intel_fbdev_unregister(dev_priv); intel_audio_deinit(dev_priv); intel_gpu_ips_teardown(); @@ -1371,7 +1373,7 @@ void i915_driver_unload(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); struct pci_dev *pdev = dev_priv->drm.pdev; - intel_fbdev_fini(dev); + i915_driver_unregister(dev_priv); if (i915_gem_suspend(dev_priv)) DRM_ERROR("failed to idle hardware; continuing to unload!\n"); @@ -1382,8 +1384,6 @@ void i915_driver_unload(struct drm_device *dev) intel_gvt_cleanup(dev_priv); - i915_driver_unregister(dev_priv); - intel_modeset_cleanup(dev); /* @@ -1409,9 +1409,6 @@ void i915_driver_unload(struct drm_device *dev) cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); i915_reset_error_state(dev_priv); - /* Flush any outstanding unpin_work. */ - drain_workqueue(dev_priv->wq); - i915_gem_fini(dev_priv); intel_uc_fini_fw(dev_priv); intel_fbc_cleanup_cfb(dev_priv); @@ -1835,7 +1832,8 @@ static int i915_resume_switcheroo(struct drm_device *dev) /** * i915_reset - reset chip after a hang - * @dev_priv: device private to reset + * @i915: #drm_i915_private to reset + * @flags: Instructions * * Reset the chip. Useful if a hang is detected. Marks the device as wedged * on failure. @@ -1850,33 +1848,34 @@ static int i915_resume_switcheroo(struct drm_device *dev) * - re-init interrupt state * - re-init display */ -void i915_reset(struct drm_i915_private *dev_priv) +void i915_reset(struct drm_i915_private *i915, unsigned int flags) { - struct i915_gpu_error *error = &dev_priv->gpu_error; + struct i915_gpu_error *error = &i915->gpu_error; int ret; - lockdep_assert_held(&dev_priv->drm.struct_mutex); + lockdep_assert_held(&i915->drm.struct_mutex); GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags)); if (!test_bit(I915_RESET_HANDOFF, &error->flags)) return; /* Clear any previous failed attempts at recovery. Time to try again. */ - if (!i915_gem_unset_wedged(dev_priv)) + if (!i915_gem_unset_wedged(i915)) goto wakeup; + if (!(flags & I915_RESET_QUIET)) + dev_notice(i915->drm.dev, "Resetting chip after gpu hang\n"); error->reset_count++; - pr_notice("drm/i915: Resetting chip after gpu hang\n"); - disable_irq(dev_priv->drm.irq); - ret = i915_gem_reset_prepare(dev_priv); + disable_irq(i915->drm.irq); + ret = i915_gem_reset_prepare(i915); if (ret) { DRM_ERROR("GPU recovery failed\n"); - intel_gpu_reset(dev_priv, ALL_ENGINES); + intel_gpu_reset(i915, ALL_ENGINES); goto error; } - ret = intel_gpu_reset(dev_priv, ALL_ENGINES); + ret = intel_gpu_reset(i915, ALL_ENGINES); if (ret) { if (ret != -ENODEV) DRM_ERROR("Failed to reset chip: %i\n", ret); @@ -1885,8 +1884,8 @@ void i915_reset(struct drm_i915_private *dev_priv) goto error; } - i915_gem_reset(dev_priv); - intel_overlay_reset(dev_priv); + i915_gem_reset(i915); + intel_overlay_reset(i915); /* Ok, now get things going again... */ @@ -1902,17 +1901,17 @@ void i915_reset(struct drm_i915_private *dev_priv) * was running at the time of the reset (i.e. we weren't VT * switched away). */ - ret = i915_gem_init_hw(dev_priv); + ret = i915_gem_init_hw(i915); if (ret) { DRM_ERROR("Failed hw init on reset %d\n", ret); goto error; } - i915_queue_hangcheck(dev_priv); + i915_queue_hangcheck(i915); finish: - i915_gem_reset_finish(dev_priv); - enable_irq(dev_priv->drm.irq); + i915_gem_reset_finish(i915); + enable_irq(i915->drm.irq); wakeup: clear_bit(I915_RESET_HANDOFF, &error->flags); @@ -1920,14 +1919,15 @@ wakeup: return; error: - i915_gem_set_wedged(dev_priv); - i915_gem_retire_requests(dev_priv); + i915_gem_set_wedged(i915); + i915_gem_retire_requests(i915); goto finish; } /** * i915_reset_engine - reset GPU engine to recover from a hang * @engine: engine to reset + * @flags: options * * Reset a specific GPU engine. Useful if a hang is detected. * Returns zero on successful reset or otherwise an error code. @@ -1937,7 +1937,7 @@ error: * - reset engine (which will force the engine to idle) * - re-init/configure engine */ -int i915_reset_engine(struct intel_engine_cs *engine) +int i915_reset_engine(struct intel_engine_cs *engine, unsigned int flags) { struct i915_gpu_error *error = &engine->i915->gpu_error; struct drm_i915_gem_request *active_request; @@ -1945,7 +1945,11 @@ int i915_reset_engine(struct intel_engine_cs *engine) GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); - DRM_DEBUG_DRIVER("resetting %s\n", engine->name); + if (!(flags & I915_RESET_QUIET)) { + dev_notice(engine->i915->drm.dev, + "Resetting %s after gpu hang\n", engine->name); + } + error->reset_engine_count[engine->id]++; active_request = i915_gem_reset_prepare_engine(engine); if (IS_ERR(active_request)) { @@ -1954,18 +1958,7 @@ int i915_reset_engine(struct intel_engine_cs *engine) goto out; } - /* - * The request that caused the hang is stuck on elsp, we know the - * active request and can drop it, adjust head to skip the offending - * request to resume executing remaining requests in the queue. - */ - i915_gem_reset_engine(engine, active_request); - - /* Finally, reset just this engine. */ ret = intel_gpu_reset(engine->i915, intel_engine_flag(engine)); - - i915_gem_reset_finish_engine(engine); - if (ret) { /* If we fail here, we expect to fallback to a global reset */ DRM_DEBUG_DRIVER("Failed to reset %s, ret=%d\n", @@ -1974,6 +1967,13 @@ int i915_reset_engine(struct intel_engine_cs *engine) } /* + * The request that caused the hang is stuck on elsp, we know the + * active request and can drop it, adjust head to skip the offending + * request to resume executing remaining requests in the queue. + */ + i915_gem_reset_engine(engine, active_request); + + /* * The engine and its registers (and workarounds in case of render) * have been reset to their default values. Follow the init_ring * process to program RING_MODE, HWSP and re-enable submission. @@ -1982,8 +1982,8 @@ int i915_reset_engine(struct intel_engine_cs *engine) if (ret) goto out; - error->reset_engine_count[engine->id]++; out: + i915_gem_reset_finish_engine(engine); return ret; } @@ -2730,6 +2730,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), }; static struct drm_driver driver = { @@ -2738,7 +2740,7 @@ static struct drm_driver driver = { */ .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC, + DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ, .release = i915_driver_release, .open = i915_driver_open, .lastclose = i915_driver_lastclose, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7c6fab08a2e6..60267e375e88 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -80,8 +80,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20170717" -#define DRIVER_TIMESTAMP 1500275179 +#define DRIVER_DATE "20170818" +#define DRIVER_TIMESTAMP 1503088845 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and * WARN_ON()) for hw state sanity checks to check for unexpected conditions @@ -602,7 +602,7 @@ struct drm_i915_file_private { * to limit the badly behaving clients access to gpu. */ #define I915_MAX_CLIENT_CONTEXT_BANS 3 - int context_bans; + atomic_t context_bans; }; /* Used by dp and fdi links */ @@ -646,6 +646,7 @@ struct intel_opregion { u32 swsci_sbcb_sub_functions; struct opregion_asle *asle; void *rvda; + void *vbt_firmware; const void *vbt; u32 vbt_size; u32 *lid_state; @@ -715,11 +716,6 @@ struct drm_i915_display_funcs { void (*fdi_link_train)(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); void (*init_clock_gating)(struct drm_i915_private *dev_priv); - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags); void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); /* clock updates for mode set */ /* cursor updates */ @@ -1063,6 +1059,11 @@ struct intel_fbc { bool underrun_detected; struct work_struct underrun_work; + /* + * Due to the atomic rules we can't access some structures without the + * appropriate locking, so we cache information here in order to avoid + * these problems. + */ struct intel_fbc_state_cache { struct i915_vma *vma; @@ -1084,6 +1085,13 @@ struct intel_fbc { } fb; } state_cache; + /* + * This structure contains everything that's relevant to program the + * hardware registers. When we want to figure out if we need to disable + * and re-enable FBC for a new configuration we just check if there's + * something different in the struct. The genx_fbc_activate functions + * are supposed to read from it in order to program the registers. + */ struct intel_fbc_reg_params { struct i915_vma *vma; @@ -1159,8 +1167,8 @@ enum intel_pch { PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ PCH_SPT, /* Sunrisepoint PCH */ - PCH_KBP, /* Kabypoint PCH */ - PCH_CNP, /* Cannonpoint PCH */ + PCH_KBP, /* Kaby Lake PCH */ + PCH_CNP, /* Cannon Lake PCH */ PCH_NOP, }; @@ -1388,12 +1396,23 @@ struct i915_power_well { bool hw_enabled; u64 domains; /* unique identifier for this power well */ - unsigned long id; + enum i915_power_well_id id; /* * Arbitraty data associated with this power well. Platform and power * well specific. */ - unsigned long data; + union { + struct { + enum dpio_phy phy; + } bxt; + struct { + /* Mask of pipes whose IRQ logic is backed by the pw */ + u8 irq_pipe_mask; + /* The pw is backing the VGA functionality */ + bool has_vga:1; + bool has_fuses:1; + } hsw; + }; const struct i915_power_well_ops *ops; }; @@ -1510,6 +1529,8 @@ struct i915_gpu_error { /* Protected by the above dev->gpu_error.lock. */ struct i915_gpu_state *first_error; + atomic_t pending_fb_pin; + unsigned long missed_irq_rings; /** @@ -1569,6 +1590,7 @@ struct i915_gpu_error { unsigned long flags; #define I915_RESET_BACKOFF 0 #define I915_RESET_HANDOFF 1 +#define I915_RESET_MODESET 2 #define I915_WEDGED (BITS_PER_LONG - 1) #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) @@ -1884,6 +1906,7 @@ struct i915_workarounds { struct i915_virtual_gpu { bool active; + u32 caps; }; /* used in computing the new watermarks state */ @@ -1903,6 +1926,24 @@ struct i915_oa_reg { u32 value; }; +struct i915_oa_config { + char uuid[UUID_STRING_LEN + 1]; + int id; + + const struct i915_oa_reg *mux_regs; + u32 mux_regs_len; + const struct i915_oa_reg *b_counter_regs; + u32 b_counter_regs_len; + const struct i915_oa_reg *flex_regs; + u32 flex_regs_len; + + struct attribute_group sysfs_metric; + struct attribute *attrs[2]; + struct device_attribute sysfs_metric_id; + + atomic_t ref_count; +}; + struct i915_perf_stream; /** @@ -2015,6 +2056,11 @@ struct i915_perf_stream { * type of configured stream. */ const struct i915_perf_stream_ops *ops; + + /** + * @oa_config: The OA configuration used by the stream. + */ + struct i915_oa_config *oa_config; }; /** @@ -2022,6 +2068,25 @@ struct i915_perf_stream { */ struct i915_oa_ops { /** + * @is_valid_b_counter_reg: Validates register's address for + * programming boolean counters for a particular platform. + */ + bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, + u32 addr); + + /** + * @is_valid_mux_reg: Validates register's address for programming mux + * for a particular platform. + */ + bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); + + /** + * @is_valid_flex_reg: Validates register's address for programming + * flex EU filtering for a particular platform. + */ + bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); + + /** * @init_oa_buffer: Resets the head and tail pointers of the * circular buffer for periodic OA reports. * @@ -2039,20 +2104,13 @@ struct i915_oa_ops { void (*init_oa_buffer)(struct drm_i915_private *dev_priv); /** - * @select_metric_set: The auto generated code that checks whether a - * requested OA config is applicable to the system and if so sets up - * the mux, oa and flex eu register config pointers according to the - * current dev_priv->perf.oa.metrics_set. - */ - int (*select_metric_set)(struct drm_i915_private *dev_priv); - - /** * @enable_metric_set: Selects and applies any MUX configuration to set * up the Boolean and Custom (B/C) counters that are part of the * counter reports being sampled. May apply system constraints such as * disabling EU clock gating as required. */ - int (*enable_metric_set)(struct drm_i915_private *dev_priv); + int (*enable_metric_set)(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config); /** * @disable_metric_set: Remove system constraints associated with using @@ -2098,6 +2156,7 @@ struct drm_i915_private { struct kmem_cache *objects; struct kmem_cache *vmas; + struct kmem_cache *luts; struct kmem_cache *requests; struct kmem_cache *dependencies; struct kmem_cache *priorities; @@ -2148,9 +2207,6 @@ struct drm_i915_private { /* protects the irq masks */ spinlock_t irq_lock; - /* protects the mmio flip data */ - spinlock_t mmio_flip_lock; - bool display_irqs_enabled; /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ @@ -2255,7 +2311,6 @@ struct drm_i915_private { struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; - wait_queue_head_t pending_flip_queue; #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; @@ -2416,10 +2471,32 @@ struct drm_i915_private { struct kobject *metrics_kobj; struct ctl_table_header *sysctl_header; + /* + * Lock associated with adding/modifying/removing OA configs + * in dev_priv->perf.metrics_idr. + */ + struct mutex metrics_lock; + + /* + * List of dynamic configurations, you need to hold + * dev_priv->perf.metrics_lock to access it. + */ + struct idr metrics_idr; + + /* + * Lock associated with anything below within this structure + * except exclusive_stream. + */ struct mutex lock; struct list_head streams; struct { + /* + * The stream currently using the OA unit. If accessed + * outside a syscall associated to its file + * descriptor, you need to hold + * dev_priv->drm.struct_mutex. + */ struct i915_perf_stream *exclusive_stream; u32 specific_ctx_id; @@ -2438,16 +2515,7 @@ struct drm_i915_private { int period_exponent; int timestamp_frequency; - int metrics_set; - - const struct i915_oa_reg *mux_regs[6]; - int mux_regs_lens[6]; - int n_mux_configs; - - const struct i915_oa_reg *b_counter_regs; - int b_counter_regs_len; - const struct i915_oa_reg *flex_regs; - int flex_regs_len; + struct i915_oa_config test_config; struct { struct i915_vma *vma; @@ -2534,7 +2602,6 @@ struct drm_i915_private { struct i915_oa_ops ops; const struct i915_oa_format *oa_formats; - int n_builtin_sets; } oa; } perf; @@ -3108,8 +3175,12 @@ extern int i915_driver_load(struct pci_dev *pdev, extern void i915_driver_unload(struct drm_device *dev); extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); -extern void i915_reset(struct drm_i915_private *dev_priv); -extern int i915_reset_engine(struct intel_engine_cs *engine); + +#define I915_RESET_QUIET BIT(0) +extern void i915_reset(struct drm_i915_private *i915, unsigned int flags); +extern int i915_reset_engine(struct intel_engine_cs *engine, + unsigned int flags); + extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); extern int intel_guc_reset(struct drm_i915_private *dev_priv); extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); @@ -3129,7 +3200,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, void intel_hpd_init(struct drm_i915_private *dev_priv); void intel_hpd_init_work(struct drm_i915_private *dev_priv); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); -bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); +enum port intel_hpd_pin_to_port(enum hpd_pin pin); +enum hpd_pin intel_hpd_pin(enum port port); bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); @@ -3298,6 +3370,26 @@ static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) } while (flush_work(&i915->mm.free_work)); } +static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) +{ + /* + * Similar to objects above (see i915_gem_drain_freed-objects), in + * general we have workers that are armed by RCU and then rearm + * themselves in their callbacks. To be paranoid, we need to + * drain the workqueue a second time after waiting for the RCU + * grace period so that we catch work queued via RCU from the first + * pass. As neither drain_workqueue() nor flush_workqueue() report + * a result, we make an assumption that we only don't require more + * than 2 passes to catch all recursive RCU delayed work. + * + */ + int pass = 2; + do { + rcu_barrier(); + drain_workqueue(i915->wq); + } while (--pass); +} + struct i915_vma * __must_check i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, @@ -3595,6 +3687,10 @@ i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, int i915_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, uint32_t *reg_state); @@ -4082,6 +4178,11 @@ static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) { + /* nsecs_to_jiffies64() does not guard against overflow */ + if (NSEC_PER_SEC % HZ && + div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) + return MAX_JIFFY_OFFSET; + return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); } @@ -4228,10 +4329,11 @@ int remap_io_mapping(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, unsigned long size, struct io_mapping *iomap); -static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj) +static inline bool +intel_engine_can_store_dword(struct intel_engine_cs *engine) { - return (obj->cache_level != I915_CACHE_NONE || - HAS_LLC(to_i915(obj->base.dev))); + return __intel_engine_can_store_dword(INTEL_GEN(engine->i915), + engine->class); } #endif diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d6f9b4cb6e9b..b9e8e0d6e97b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -52,7 +52,7 @@ static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) if (obj->cache_dirty) return false; - if (!obj->cache_coherent) + if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) return true; return obj->pin_display; @@ -253,7 +253,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, if (needs_clflush && (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && - !obj->cache_coherent) + !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) drm_clflush_sg(pages); __start_cpu_write(obj); @@ -561,46 +561,6 @@ static struct intel_rps_client *to_rps_client(struct drm_file *file) return &fpriv->rps; } -int -i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, - int align) -{ - int ret; - - if (align > obj->base.size) - return -EINVAL; - - if (obj->ops == &i915_gem_phys_ops) - return 0; - - if (obj->mm.madv != I915_MADV_WILLNEED) - return -EFAULT; - - if (obj->base.filp == NULL) - return -EINVAL; - - ret = i915_gem_object_unbind(obj); - if (ret) - return ret; - - __i915_gem_object_put_pages(obj, I915_MM_NORMAL); - if (obj->mm.pages) - return -EBUSY; - - GEM_BUG_ON(obj->ops != &i915_gem_object_ops); - obj->ops = &i915_gem_phys_ops; - - ret = i915_gem_object_pin_pages(obj); - if (ret) - goto err_xfer; - - return 0; - -err_xfer: - obj->ops = &i915_gem_object_ops; - return ret; -} - static int i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, struct drm_i915_gem_pwrite *args, @@ -840,7 +800,8 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, if (ret) return ret; - if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || + !static_cpu_has(X86_FEATURE_CLFLUSH)) { ret = i915_gem_object_set_to_cpu_domain(obj, false); if (ret) goto err_unpin; @@ -892,7 +853,8 @@ int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, if (ret) return ret; - if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { + if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || + !static_cpu_has(X86_FEATURE_CLFLUSH)) { ret = i915_gem_object_set_to_cpu_domain(obj, true); if (ret) goto err_unpin; @@ -2740,34 +2702,38 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, return 0; } -static bool ban_context(const struct i915_gem_context *ctx) +static bool ban_context(const struct i915_gem_context *ctx, + unsigned int score) { return (i915_gem_context_is_bannable(ctx) && - ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); + score >= CONTEXT_SCORE_BAN_THRESHOLD); } static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) { - ctx->guilty_count++; - ctx->ban_score += CONTEXT_SCORE_GUILTY; - if (ban_context(ctx)) - i915_gem_context_set_banned(ctx); + unsigned int score; + bool banned; - DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", - ctx->name, ctx->ban_score, - yesno(i915_gem_context_is_banned(ctx))); + atomic_inc(&ctx->guilty_count); - if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) + score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score); + banned = ban_context(ctx, score); + DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", + ctx->name, score, yesno(banned)); + if (!banned) return; - ctx->file_priv->context_bans++; - DRM_DEBUG_DRIVER("client %s has had %d context banned\n", - ctx->name, ctx->file_priv->context_bans); + i915_gem_context_set_banned(ctx); + if (!IS_ERR_OR_NULL(ctx->file_priv)) { + atomic_inc(&ctx->file_priv->context_bans); + DRM_DEBUG_DRIVER("client %s has had %d context banned\n", + ctx->name, atomic_read(&ctx->file_priv->context_bans)); + } } static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) { - ctx->active_count++; + atomic_inc(&ctx->active_count); } struct drm_i915_gem_request * @@ -2850,11 +2816,9 @@ i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) if (engine->irq_seqno_barrier) engine->irq_seqno_barrier(engine); - if (engine_stalled(engine)) { - request = i915_gem_find_active_request(engine); - if (request && request->fence.error == -EIO) - request = ERR_PTR(-EIO); /* Previous reset failed! */ - } + request = i915_gem_find_active_request(engine); + if (request && request->fence.error == -EIO) + request = ERR_PTR(-EIO); /* Previous reset failed! */ return request; } @@ -2923,12 +2887,11 @@ static void engine_skip_context(struct drm_i915_gem_request *request) spin_unlock_irqrestore(&engine->timeline->lock, flags); } -/* Returns true if the request was guilty of hang */ -static bool i915_gem_reset_request(struct drm_i915_gem_request *request) +/* Returns the request if it was guilty of the hang */ +static struct drm_i915_gem_request * +i915_gem_reset_request(struct intel_engine_cs *engine, + struct drm_i915_gem_request *request) { - /* Read once and return the resolution */ - const bool guilty = !i915_gem_request_completed(request); - /* The guilty request will get skipped on a hung engine. * * Users of client default contexts do not rely on logical @@ -2950,27 +2913,47 @@ static bool i915_gem_reset_request(struct drm_i915_gem_request *request) * subsequent hangs. */ - if (guilty) { + if (engine_stalled(engine)) { i915_gem_context_mark_guilty(request->ctx); skip_request(request); + + /* If this context is now banned, skip all pending requests. */ + if (i915_gem_context_is_banned(request->ctx)) + engine_skip_context(request); } else { - i915_gem_context_mark_innocent(request->ctx); - dma_fence_set_error(&request->fence, -EAGAIN); + /* + * Since this is not the hung engine, it may have advanced + * since the hang declaration. Double check by refinding + * the active request at the time of the reset. + */ + request = i915_gem_find_active_request(engine); + if (request) { + i915_gem_context_mark_innocent(request->ctx); + dma_fence_set_error(&request->fence, -EAGAIN); + + /* Rewind the engine to replay the incomplete rq */ + spin_lock_irq(&engine->timeline->lock); + request = list_prev_entry(request, link); + if (&request->link == &engine->timeline->requests) + request = NULL; + spin_unlock_irq(&engine->timeline->lock); + } } - return guilty; + return request; } void i915_gem_reset_engine(struct intel_engine_cs *engine, struct drm_i915_gem_request *request) { - if (request && i915_gem_reset_request(request)) { + engine->irq_posted = 0; + + if (request) + request = i915_gem_reset_request(engine, request); + + if (request) { DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", engine->name, request->global_seqno); - - /* If this context is now banned, skip all pending requests. */ - if (i915_gem_context_is_banned(request->ctx)) - engine_skip_context(request); } /* Setup the CS to resume from the breadcrumb of the hung request */ @@ -3026,6 +3009,7 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) static void nop_submit_request(struct drm_i915_gem_request *request) { + GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error)); dma_fence_set_error(&request->fence, -EIO); i915_gem_request_submit(request); intel_engine_init_global_seqno(request->engine, request->global_seqno); @@ -3051,13 +3035,6 @@ static void engine_set_wedged(struct intel_engine_cs *engine) dma_fence_set_error(&request->fence, -EIO); spin_unlock_irqrestore(&engine->timeline->lock, flags); - /* Mark all pending requests as complete so that any concurrent - * (lockless) lookup doesn't try and wait upon the request as we - * reset it. - */ - intel_engine_init_global_seqno(engine, - intel_engine_last_submit(engine)); - /* * Clear the execlists queue up before freeing the requests, as those * are the ones that keep the context and ringbuffer backing objects @@ -3086,6 +3063,13 @@ static void engine_set_wedged(struct intel_engine_cs *engine) */ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); } + + /* Mark all pending requests as complete so that any concurrent + * (lockless) lookup doesn't try and wait upon the request as we + * reset it. + */ + intel_engine_init_global_seqno(engine, + intel_engine_last_submit(engine)); } static int __i915_gem_set_wedged_BKL(void *data) @@ -3094,10 +3078,12 @@ static int __i915_gem_set_wedged_BKL(void *data) struct intel_engine_cs *engine; enum intel_engine_id id; - set_bit(I915_WEDGED, &i915->gpu_error.flags); for_each_engine(engine, i915, id) engine_set_wedged(engine); + set_bit(I915_WEDGED, &i915->gpu_error.flags); + wake_up_all(&i915->gpu_error.reset_queue); + return 0; } @@ -3256,25 +3242,33 @@ out_rearm: void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) { + struct drm_i915_private *i915 = to_i915(gem->dev); struct drm_i915_gem_object *obj = to_intel_bo(gem); struct drm_i915_file_private *fpriv = file->driver_priv; - struct i915_vma *vma, *vn; + struct i915_lut_handle *lut, *ln; - mutex_lock(&obj->base.dev->struct_mutex); - list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) - if (vma->vm->file == fpriv) + mutex_lock(&i915->drm.struct_mutex); + + list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { + struct i915_gem_context *ctx = lut->ctx; + struct i915_vma *vma; + + if (ctx->file_priv != fpriv) + continue; + + vma = radix_tree_delete(&ctx->handles_vma, lut->handle); + + if (!i915_vma_is_ggtt(vma)) i915_vma_close(vma); - vma = obj->vma_hashed; - if (vma && vma->ctx->file_priv == fpriv) - i915_vma_unlink_ctx(vma); + list_del(&lut->obj_link); + list_del(&lut->ctx_link); - if (i915_gem_object_is_active(obj) && - !i915_gem_object_has_active_reference(obj)) { - i915_gem_object_set_active_reference(obj); - i915_gem_object_get(obj); + kmem_cache_free(i915->luts, lut); + __i915_gem_object_release_unless_active(obj); } - mutex_unlock(&obj->base.dev->struct_mutex); + + mutex_unlock(&i915->drm.struct_mutex); } static unsigned long to_wait_timeout(s64 timeout_ns) @@ -3300,7 +3294,7 @@ static unsigned long to_wait_timeout(s64 timeout_ns) * -ERESTARTSYS: signal interrupted the wait * -ENONENT: object doesn't exist * Also possible, but rare: - * -EAGAIN: GPU wedged + * -EAGAIN: incomplete, restart syscall * -ENOMEM: damn * -ENODEV: Internal IRQ fail * -E?: The add request failed @@ -3348,6 +3342,10 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) */ if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) args->timeout_ns = 0; + + /* Asked to wait beyond the jiffie/scheduler precision? */ + if (ret == -ETIME && args->timeout_ns) + ret = -EAGAIN; } i915_gem_object_put(obj); @@ -3689,8 +3687,7 @@ restart: list_for_each_entry(vma, &obj->vma_list, obj_link) vma->node.color = cache_level; - obj->cache_level = cache_level; - obj->cache_coherent = i915_gem_object_is_coherent(obj); + i915_gem_object_set_cache_coherency(obj, cache_level); obj->cache_dirty = true; /* Always invalidate stale cachelines */ return 0; @@ -4263,6 +4260,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->global_link); INIT_LIST_HEAD(&obj->userfault_link); INIT_LIST_HEAD(&obj->vma_list); + INIT_LIST_HEAD(&obj->lut_list); INIT_LIST_HEAD(&obj->batch_pool_link); obj->ops = ops; @@ -4295,6 +4293,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) { struct drm_i915_gem_object *obj; struct address_space *mapping; + unsigned int cache_level; gfp_t mask; int ret; @@ -4333,7 +4332,7 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; - if (HAS_LLC(dev_priv)) { + if (HAS_LLC(dev_priv)) /* On some devices, we can have the GPU use the LLC (the CPU * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than @@ -4346,12 +4345,11 @@ i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) * However, we maintain the display planes as UC, and so * need to rebind when first used as such. */ - obj->cache_level = I915_CACHE_LLC; - } else - obj->cache_level = I915_CACHE_NONE; + cache_level = I915_CACHE_LLC; + else + cache_level = I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + i915_gem_object_set_cache_coherency(obj, cache_level); trace_i915_gem_object_create(obj); @@ -4506,8 +4504,8 @@ void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) { lockdep_assert_held(&obj->base.dev->struct_mutex); - GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); - if (i915_gem_object_is_active(obj)) + if (!i915_gem_object_has_active_reference(obj) && + i915_gem_object_is_active(obj)) i915_gem_object_set_active_reference(obj); else i915_gem_object_put(obj); @@ -4899,12 +4897,16 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) if (!dev_priv->vmas) goto err_objects; + dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0); + if (!dev_priv->luts) + goto err_vmas; + dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, SLAB_HWCACHE_ALIGN | SLAB_RECLAIM_ACCOUNT | SLAB_TYPESAFE_BY_RCU); if (!dev_priv->requests) - goto err_vmas; + goto err_luts; dev_priv->dependencies = KMEM_CACHE(i915_dependency, SLAB_HWCACHE_ALIGN | @@ -4936,8 +4938,6 @@ i915_gem_load_init(struct drm_i915_private *dev_priv) init_waitqueue_head(&dev_priv->gpu_error.wait_queue); init_waitqueue_head(&dev_priv->gpu_error.reset_queue); - init_waitqueue_head(&dev_priv->pending_flip_queue); - atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); spin_lock_init(&dev_priv->fb_tracking.lock); @@ -4950,6 +4950,8 @@ err_dependencies: kmem_cache_destroy(dev_priv->dependencies); err_requests: kmem_cache_destroy(dev_priv->requests); +err_luts: + kmem_cache_destroy(dev_priv->luts); err_vmas: kmem_cache_destroy(dev_priv->vmas); err_objects: @@ -4972,6 +4974,7 @@ void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) kmem_cache_destroy(dev_priv->priorities); kmem_cache_destroy(dev_priv->dependencies); kmem_cache_destroy(dev_priv->requests); + kmem_cache_destroy(dev_priv->luts); kmem_cache_destroy(dev_priv->vmas); kmem_cache_destroy(dev_priv->objects); @@ -5304,6 +5307,64 @@ i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, return sg_dma_address(sg) + (offset << PAGE_SHIFT); } +int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) +{ + struct sg_table *pages; + int err; + + if (align > obj->base.size) + return -EINVAL; + + if (obj->ops == &i915_gem_phys_ops) + return 0; + + if (obj->ops != &i915_gem_object_ops) + return -EINVAL; + + err = i915_gem_object_unbind(obj); + if (err) + return err; + + mutex_lock(&obj->mm.lock); + + if (obj->mm.madv != I915_MADV_WILLNEED) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.quirked) { + err = -EFAULT; + goto err_unlock; + } + + if (obj->mm.mapping) { + err = -EBUSY; + goto err_unlock; + } + + pages = obj->mm.pages; + obj->ops = &i915_gem_phys_ops; + + err = ____i915_gem_object_get_pages(obj); + if (err) + goto err_xfer; + + /* Perma-pin (until release) the physical set of pages */ + __i915_gem_object_pin_pages(obj); + + if (!IS_ERR_OR_NULL(pages)) + i915_gem_object_ops.put_pages(obj, pages); + mutex_unlock(&obj->mm.lock); + return 0; + +err_xfer: + obj->ops = &i915_gem_object_ops; + obj->mm.pages = pages; +err_unlock: + mutex_unlock(&obj->mm.lock); + return err; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/scatterlist.c" #include "selftests/mock_gem_device.c" diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index 348b29a845c9..8a04d33055be 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -139,7 +139,8 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, * snooping behaviour occurs naturally as the result of our domain * tracking. */ - if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent) + if (!(flags & I915_CLFLUSH_FORCE) && + obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) return false; trace_i915_gem_object_clflush(obj); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 1a87d04e7937..58a2a44f88bd 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -93,69 +93,28 @@ #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 -/* Initial size (as log2) to preallocate the handle->object hashtable */ -#define VMA_HT_BITS 2u /* 4 x 2 pointers, 64 bytes minimum */ - -static void resize_vma_ht(struct work_struct *work) +static void lut_close(struct i915_gem_context *ctx) { - struct i915_gem_context_vma_lut *lut = - container_of(work, typeof(*lut), resize); - unsigned int bits, new_bits, size, i; - struct hlist_head *new_ht; - - GEM_BUG_ON(!(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)); - - bits = 1 + ilog2(4*lut->ht_count/3 + 1); - new_bits = min_t(unsigned int, - max(bits, VMA_HT_BITS), - sizeof(unsigned int) * BITS_PER_BYTE - 1); - if (new_bits == lut->ht_bits) - goto out; - - new_ht = kzalloc(sizeof(*new_ht)<<new_bits, GFP_KERNEL | __GFP_NOWARN); - if (!new_ht) - new_ht = vzalloc(sizeof(*new_ht)<<new_bits); - if (!new_ht) - /* Pretend resize succeeded and stop calling us for a bit! */ - goto out; + struct i915_lut_handle *lut, *ln; + struct radix_tree_iter iter; + void __rcu **slot; - size = BIT(lut->ht_bits); - for (i = 0; i < size; i++) { - struct i915_vma *vma; - struct hlist_node *tmp; - - hlist_for_each_entry_safe(vma, tmp, &lut->ht[i], ctx_node) - hlist_add_head(&vma->ctx_node, - &new_ht[hash_32(vma->ctx_handle, - new_bits)]); + list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) { + list_del(&lut->obj_link); + kmem_cache_free(ctx->i915->luts, lut); } - kvfree(lut->ht); - lut->ht = new_ht; - lut->ht_bits = new_bits; -out: - smp_store_release(&lut->ht_size, BIT(bits)); - GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); -} -static void vma_lut_free(struct i915_gem_context *ctx) -{ - struct i915_gem_context_vma_lut *lut = &ctx->vma_lut; - unsigned int i, size; + radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) { + struct i915_vma *vma = rcu_dereference_raw(*slot); + struct drm_i915_gem_object *obj = vma->obj; - if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) - cancel_work_sync(&lut->resize); + radix_tree_iter_delete(&ctx->handles_vma, &iter, slot); - size = BIT(lut->ht_bits); - for (i = 0; i < size; i++) { - struct i915_vma *vma; + if (!i915_vma_is_ggtt(vma)) + i915_vma_close(vma); - hlist_for_each_entry(vma, &lut->ht[i], ctx_node) { - vma->obj->vma_hashed = NULL; - vma->ctx = NULL; - i915_vma_put(vma); - } + __i915_gem_object_release_unless_active(obj); } - kvfree(lut->ht); } static void i915_gem_context_free(struct i915_gem_context *ctx) @@ -165,7 +124,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx) lockdep_assert_held(&ctx->i915->drm.struct_mutex); GEM_BUG_ON(!i915_gem_context_is_closed(ctx)); - vma_lut_free(ctx); i915_ppgtt_put(ctx->ppgtt); for (i = 0; i < I915_NUM_ENGINES; i++) { @@ -239,8 +197,11 @@ void i915_gem_context_release(struct kref *ref) static void context_close(struct i915_gem_context *ctx) { i915_gem_context_set_closed(ctx); + + lut_close(ctx); if (ctx->ppgtt) i915_ppgtt_close(&ctx->ppgtt->base); + ctx->file_priv = ERR_PTR(-EBADF); i915_gem_context_put(ctx); } @@ -313,16 +274,8 @@ __create_hw_context(struct drm_i915_private *dev_priv, ctx->i915 = dev_priv; ctx->priority = I915_PRIORITY_NORMAL; - ctx->vma_lut.ht_bits = VMA_HT_BITS; - ctx->vma_lut.ht_size = BIT(VMA_HT_BITS); - BUILD_BUG_ON(BIT(VMA_HT_BITS) == I915_CTX_RESIZE_IN_PROGRESS); - ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size, - sizeof(*ctx->vma_lut.ht), - GFP_KERNEL); - if (!ctx->vma_lut.ht) - goto err_out; - - INIT_WORK(&ctx->vma_lut.resize, resize_vma_ht); + INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + INIT_LIST_HEAD(&ctx->handles_list); /* Default context will never have a file_priv */ ret = DEFAULT_CONTEXT_HANDLE; @@ -372,8 +325,6 @@ err_pid: put_pid(ctx->pid); idr_remove(&file_priv->context_idr, ctx->user_handle); err_lut: - kvfree(ctx->vma_lut.ht); -err_out: context_close(ctx); return ERR_PTR(ret); } @@ -741,19 +692,19 @@ static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, } static bool -needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, - struct intel_engine_cs *engine, - struct i915_gem_context *to) +needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine) { + struct i915_gem_context *from = engine->legacy_active_context; + if (!ppgtt) return false; /* Always load the ppgtt on first use */ - if (!engine->legacy_active_context) + if (!from) return true; /* Same context without new entries, skip */ - if (engine->legacy_active_context == to && + if ((!from->ppgtt || from->ppgtt == ppgtt) && !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) return false; @@ -797,7 +748,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) if (skip_rcs_switch(ppgtt, engine, to)) return 0; - if (needs_pd_load_pre(ppgtt, engine, to)) { + if (needs_pd_load_pre(ppgtt, engine)) { /* Older GENs and non render rings still want the load first, * "PP_DCLV followed by PP_DIR_BASE register through Load * Register Immediate commands in Ring Buffer before submitting @@ -894,7 +845,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; - if (needs_pd_load_pre(ppgtt, engine, to)) { + if (needs_pd_load_pre(ppgtt, engine)) { int ret; trace_switch_mm(engine, to); @@ -905,6 +856,7 @@ int i915_switch_context(struct drm_i915_gem_request *req) ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); } + engine->legacy_active_context = to; return 0; } @@ -977,7 +929,7 @@ int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) static bool client_is_banned(struct drm_i915_file_private *file_priv) { - return file_priv->context_bans > I915_MAX_CLIENT_CONTEXT_BANS; + return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS; } int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, @@ -1179,8 +1131,8 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, else args->reset_count = 0; - args->batch_active = READ_ONCE(ctx->guilty_count); - args->batch_pending = READ_ONCE(ctx->active_count); + args->batch_active = atomic_read(&ctx->guilty_count); + args->batch_pending = atomic_read(&ctx->active_count); ret = 0; out: diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 04320f80f9f4..44688e22a5c2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -27,6 +27,7 @@ #include <linux/bitops.h> #include <linux/list.h> +#include <linux/radix-tree.h> struct pid; @@ -149,32 +150,6 @@ struct i915_gem_context { /** ggtt_offset_bias: placement restriction for context objects */ u32 ggtt_offset_bias; - struct i915_gem_context_vma_lut { - /** ht_size: last request size to allocate the hashtable for. */ - unsigned int ht_size; -#define I915_CTX_RESIZE_IN_PROGRESS BIT(0) - /** ht_bits: real log2(size) of hashtable. */ - unsigned int ht_bits; - /** ht_count: current number of entries inside the hashtable */ - unsigned int ht_count; - - /** ht: the array of buckets comprising the simple hashtable */ - struct hlist_head *ht; - - /** - * resize: After an execbuf completes, we check the load factor - * of the hashtable. If the hashtable is too full, or too empty, - * we schedule a task to resize the hashtable. During the - * resize, the entries are moved between different buckets and - * so we cannot simultaneously read the hashtable as it is - * being resized (unlike rhashtable). Therefore we treat the - * active work as a strong barrier, pausing a subsequent - * execbuf to wait for the resize worker to complete, if - * required. - */ - struct work_struct resize; - } vma_lut; - /** engine: per-engine logical HW state */ struct intel_context { struct i915_vma *state; @@ -191,20 +166,32 @@ struct i915_gem_context { u32 desc_template; /** guilty_count: How many times this context has caused a GPU hang. */ - unsigned int guilty_count; + atomic_t guilty_count; /** * @active_count: How many times this context was active during a GPU * hang, but did not cause it. */ - unsigned int active_count; + atomic_t active_count; #define CONTEXT_SCORE_GUILTY 10 #define CONTEXT_SCORE_BAN_THRESHOLD 40 /** ban_score: Accumulated score of all hangs caused by this context. */ - int ban_score; + atomic_t ban_score; /** remap_slice: Bitmask of cache lines that need remapping */ u8 remap_slice; + + /** handles_vma: rbtree to look up our context specific obj/vma for + * the user handle. (user handles are per fd, but the binding is + * per vm, which may be one per context or shared with the global GTT) + */ + struct radix_tree_root handles_vma; + + /** handles_list: reverse list of all the rbtree entries in use for + * this context, which allows us to free all the allocations on + * context close. + */ + struct list_head handles_list; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c index a193f1b36c67..4df039ef2ce3 100644 --- a/drivers/gpu/drm/i915/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/i915_gem_evict.c @@ -318,8 +318,8 @@ int i915_gem_evict_for_node(struct i915_address_space *vm, /* Overlap of objects in the same batch? */ if (i915_vma_is_pinned(vma)) { ret = -ENOSPC; - if (vma->exec_entry && - vma->exec_entry->flags & EXEC_OBJECT_PINNED) + if (vma->exec_flags && + *vma->exec_flags & EXEC_OBJECT_PINNED) ret = -EINVAL; break; } diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 5fa44767c29e..3d74f3a27c13 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -32,6 +32,7 @@ #include <linux/uaccess.h> #include <drm/drmP.h> +#include <drm/drm_syncobj.h> #include <drm/i915_drm.h> #include "i915_drv.h" @@ -191,6 +192,8 @@ struct i915_execbuffer { struct drm_file *file; /** per-file lookup tables and limits */ struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ + struct i915_vma **vma; + unsigned int *flags; struct intel_engine_cs *engine; /** engine to queue the request to */ struct i915_gem_context *ctx; /** context for building the request */ @@ -244,13 +247,7 @@ struct i915_execbuffer { struct hlist_head *buckets; /** ht for relocation handles */ }; -/* - * As an alternative to creating a hashtable of handle-to-vma for a batch, - * we used the last available reserved field in the execobject[] and stash - * a link from the execobj to its vma. - */ -#define __exec_to_vma(ee) (ee)->rsvd2 -#define exec_to_vma(ee) u64_to_ptr(struct i915_vma, __exec_to_vma(ee)) +#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags]) /* * Used to convert any address to canonical form. @@ -319,85 +316,82 @@ static int eb_create(struct i915_execbuffer *eb) static bool eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, - const struct i915_vma *vma) + const struct i915_vma *vma, + unsigned int flags) { - if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) - return true; - if (vma->node.size < entry->pad_to_size) return true; if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) return true; - if (entry->flags & EXEC_OBJECT_PINNED && + if (flags & EXEC_OBJECT_PINNED && vma->node.start != entry->offset) return true; - if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && + if (flags & __EXEC_OBJECT_NEEDS_BIAS && vma->node.start < BATCH_OFFSET_BIAS) return true; - if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && + if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && (vma->node.start + vma->node.size - 1) >> 32) return true; return false; } -static inline void +static inline bool eb_pin_vma(struct i915_execbuffer *eb, - struct drm_i915_gem_exec_object2 *entry, + const struct drm_i915_gem_exec_object2 *entry, struct i915_vma *vma) { - u64 flags; + unsigned int exec_flags = *vma->exec_flags; + u64 pin_flags; if (vma->node.size) - flags = vma->node.start; + pin_flags = vma->node.start; else - flags = entry->offset & PIN_OFFSET_MASK; + pin_flags = entry->offset & PIN_OFFSET_MASK; - flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_GTT)) - flags |= PIN_GLOBAL; + pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED; + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_GTT)) + pin_flags |= PIN_GLOBAL; - if (unlikely(i915_vma_pin(vma, 0, 0, flags))) - return; + if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) + return false; - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { if (unlikely(i915_vma_get_fence(vma))) { i915_vma_unpin(vma); - return; + return false; } if (i915_vma_pin_fence(vma)) - entry->flags |= __EXEC_OBJECT_HAS_FENCE; + exec_flags |= __EXEC_OBJECT_HAS_FENCE; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; + *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN; + return !eb_vma_misplaced(entry, vma, exec_flags); } -static inline void -__eb_unreserve_vma(struct i915_vma *vma, - const struct drm_i915_gem_exec_object2 *entry) +static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) { - GEM_BUG_ON(!(entry->flags & __EXEC_OBJECT_HAS_PIN)); + GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); - if (unlikely(entry->flags & __EXEC_OBJECT_HAS_FENCE)) + if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) i915_vma_unpin_fence(vma); __i915_vma_unpin(vma); } static inline void -eb_unreserve_vma(struct i915_vma *vma, - struct drm_i915_gem_exec_object2 *entry) +eb_unreserve_vma(struct i915_vma *vma, unsigned int *flags) { - if (!(entry->flags & __EXEC_OBJECT_HAS_PIN)) + if (!(*flags & __EXEC_OBJECT_HAS_PIN)) return; - __eb_unreserve_vma(vma, entry); - entry->flags &= ~__EXEC_OBJECT_RESERVED; + __eb_unreserve_vma(vma, *flags); + *flags &= ~__EXEC_OBJECT_RESERVED; } static int @@ -427,7 +421,7 @@ eb_validate_vma(struct i915_execbuffer *eb, entry->pad_to_size = 0; } - if (unlikely(vma->exec_entry)) { + if (unlikely(vma->exec_flags)) { DRM_DEBUG("Object [handle %d, index %d] appears more than once in object list\n", entry->handle, (int)(entry - eb->exec)); return -EINVAL; @@ -440,14 +434,25 @@ eb_validate_vma(struct i915_execbuffer *eb, */ entry->offset = gen8_noncanonical_addr(entry->offset); + if (!eb->reloc_cache.has_fence) { + entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; + } else { + if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || + eb->reloc_cache.needs_unfenced) && + i915_gem_object_is_tiled(vma->obj)) + entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; + } + + if (!(entry->flags & EXEC_OBJECT_PINNED)) + entry->flags |= eb->context_flags; + return 0; } static int -eb_add_vma(struct i915_execbuffer *eb, - struct drm_i915_gem_exec_object2 *entry, - struct i915_vma *vma) +eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma) { + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; int err; GEM_BUG_ON(i915_vma_is_closed(vma)); @@ -468,40 +473,28 @@ eb_add_vma(struct i915_execbuffer *eb, if (entry->relocation_count) list_add_tail(&vma->reloc_link, &eb->relocs); - if (!eb->reloc_cache.has_fence) { - entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; - } else { - if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || - eb->reloc_cache.needs_unfenced) && - i915_gem_object_is_tiled(vma->obj)) - entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; - } - - if (!(entry->flags & EXEC_OBJECT_PINNED)) - entry->flags |= eb->context_flags; - /* * Stash a pointer from the vma to execobj, so we can query its flags, * size, alignment etc as provided by the user. Also we stash a pointer * to the vma inside the execobj so that we can use a direct lookup * to find the right target VMA when doing relocations. */ - vma->exec_entry = entry; - __exec_to_vma(entry) = (uintptr_t)vma; + eb->vma[i] = vma; + eb->flags[i] = entry->flags; + vma->exec_flags = &eb->flags[i]; err = 0; - eb_pin_vma(eb, entry, vma); - if (eb_vma_misplaced(entry, vma)) { - eb_unreserve_vma(vma, entry); - - list_add_tail(&vma->exec_link, &eb->unbound); - if (drm_mm_node_allocated(&vma->node)) - err = i915_vma_unbind(vma); - } else { + if (eb_pin_vma(eb, entry, vma)) { if (entry->offset != vma->node.start) { entry->offset = vma->node.start | UPDATE; eb->args->flags |= __EXEC_HAS_RELOC; } + } else { + eb_unreserve_vma(vma, vma->exec_flags); + + list_add_tail(&vma->exec_link, &eb->unbound); + if (drm_mm_node_allocated(&vma->node)) + err = i915_vma_unbind(vma); } return err; } @@ -526,32 +519,35 @@ static inline int use_cpu_reloc(const struct reloc_cache *cache, static int eb_reserve_vma(const struct i915_execbuffer *eb, struct i915_vma *vma) { - struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; - u64 flags; + struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); + unsigned int exec_flags = *vma->exec_flags; + u64 pin_flags; int err; - flags = PIN_USER | PIN_NONBLOCK; - if (entry->flags & EXEC_OBJECT_NEEDS_GTT) - flags |= PIN_GLOBAL; + pin_flags = PIN_USER | PIN_NONBLOCK; + if (exec_flags & EXEC_OBJECT_NEEDS_GTT) + pin_flags |= PIN_GLOBAL; /* * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, * limit address to the first 4GBs for unflagged objects. */ - if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) - flags |= PIN_ZONE_4G; + if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) + pin_flags |= PIN_ZONE_4G; - if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) - flags |= PIN_MAPPABLE; + if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) + pin_flags |= PIN_MAPPABLE; - if (entry->flags & EXEC_OBJECT_PINNED) { - flags |= entry->offset | PIN_OFFSET_FIXED; - flags &= ~PIN_NONBLOCK; /* force overlapping PINNED checks */ - } else if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) { - flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; + if (exec_flags & EXEC_OBJECT_PINNED) { + pin_flags |= entry->offset | PIN_OFFSET_FIXED; + pin_flags &= ~PIN_NONBLOCK; /* force overlapping checks */ + } else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) { + pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; } - err = i915_vma_pin(vma, entry->pad_to_size, entry->alignment, flags); + err = i915_vma_pin(vma, + entry->pad_to_size, entry->alignment, + pin_flags); if (err) return err; @@ -560,7 +556,7 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, eb->args->flags |= __EXEC_HAS_RELOC; } - if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) { + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { err = i915_vma_get_fence(vma); if (unlikely(err)) { i915_vma_unpin(vma); @@ -568,11 +564,11 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, } if (i915_vma_pin_fence(vma)) - entry->flags |= __EXEC_OBJECT_HAS_FENCE; + exec_flags |= __EXEC_OBJECT_HAS_FENCE; } - entry->flags |= __EXEC_OBJECT_HAS_PIN; - GEM_BUG_ON(eb_vma_misplaced(entry, vma)); + *vma->exec_flags = exec_flags | __EXEC_OBJECT_HAS_PIN; + GEM_BUG_ON(eb_vma_misplaced(entry, vma, exec_flags)); return 0; } @@ -614,18 +610,18 @@ static int eb_reserve(struct i915_execbuffer *eb) INIT_LIST_HEAD(&eb->unbound); INIT_LIST_HEAD(&last); for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; - if (entry->flags & EXEC_OBJECT_PINNED && - entry->flags & __EXEC_OBJECT_HAS_PIN) + if (flags & EXEC_OBJECT_PINNED && + flags & __EXEC_OBJECT_HAS_PIN) continue; - vma = exec_to_vma(entry); - eb_unreserve_vma(vma, entry); + eb_unreserve_vma(vma, &eb->flags[i]); - if (entry->flags & EXEC_OBJECT_PINNED) + if (flags & EXEC_OBJECT_PINNED) list_add(&vma->exec_link, &eb->unbound); - else if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) + else if (flags & __EXEC_OBJECT_NEEDS_MAP) list_add_tail(&vma->exec_link, &eb->unbound); else list_add_tail(&vma->exec_link, &last); @@ -649,19 +645,6 @@ static int eb_reserve(struct i915_execbuffer *eb) } while (1); } -static inline struct hlist_head * -ht_head(const struct i915_gem_context_vma_lut *lut, u32 handle) -{ - return &lut->ht[hash_32(handle, lut->ht_bits)]; -} - -static inline bool -ht_needs_resize(const struct i915_gem_context_vma_lut *lut) -{ - return (4*lut->ht_count > 3*lut->ht_size || - 4*lut->ht_count + 1 < lut->ht_size); -} - static unsigned int eb_batch_index(const struct i915_execbuffer *eb) { if (eb->args->flags & I915_EXEC_BATCH_FIRST) @@ -678,13 +661,6 @@ static int eb_select_context(struct i915_execbuffer *eb) if (unlikely(!ctx)) return -ENOENT; - if (unlikely(i915_gem_context_is_banned(ctx))) { - DRM_DEBUG("Context %u tried to submit while banned\n", - ctx->user_handle); - i915_gem_context_put(ctx); - return -EIO; - } - eb->ctx = ctx; eb->vm = ctx->ppgtt ? &ctx->ppgtt->base : &eb->i915->ggtt.base; @@ -697,132 +673,74 @@ static int eb_select_context(struct i915_execbuffer *eb) static int eb_lookup_vmas(struct i915_execbuffer *eb) { -#define INTERMEDIATE BIT(0) - const unsigned int count = eb->buffer_count; - struct i915_gem_context_vma_lut *lut = &eb->ctx->vma_lut; - struct i915_vma *vma; - struct idr *idr; + struct radix_tree_root *handles_vma = &eb->ctx->handles_vma; + struct drm_i915_gem_object *uninitialized_var(obj); unsigned int i; - int slow_pass = -1; int err; - INIT_LIST_HEAD(&eb->relocs); - INIT_LIST_HEAD(&eb->unbound); - - if (unlikely(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS)) - flush_work(&lut->resize); - GEM_BUG_ON(lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS); - - for (i = 0; i < count; i++) { - __exec_to_vma(&eb->exec[i]) = 0; - - hlist_for_each_entry(vma, - ht_head(lut, eb->exec[i].handle), - ctx_node) { - if (vma->ctx_handle != eb->exec[i].handle) - continue; - - err = eb_add_vma(eb, &eb->exec[i], vma); - if (unlikely(err)) - return err; - - goto next_vma; - } + if (unlikely(i915_gem_context_is_closed(eb->ctx))) + return -ENOENT; - if (slow_pass < 0) - slow_pass = i; -next_vma: ; - } + if (unlikely(i915_gem_context_is_banned(eb->ctx))) + return -EIO; - if (slow_pass < 0) - goto out; + INIT_LIST_HEAD(&eb->relocs); + INIT_LIST_HEAD(&eb->unbound); - spin_lock(&eb->file->table_lock); - /* - * Grab a reference to the object and release the lock so we can lookup - * or create the VMA without using GFP_ATOMIC - */ - idr = &eb->file->object_idr; - for (i = slow_pass; i < count; i++) { - struct drm_i915_gem_object *obj; + for (i = 0; i < eb->buffer_count; i++) { + u32 handle = eb->exec[i].handle; + struct i915_lut_handle *lut; + struct i915_vma *vma; - if (__exec_to_vma(&eb->exec[i])) - continue; + vma = radix_tree_lookup(handles_vma, handle); + if (likely(vma)) + goto add_vma; - obj = to_intel_bo(idr_find(idr, eb->exec[i].handle)); + obj = i915_gem_object_lookup(eb->file, handle); if (unlikely(!obj)) { - spin_unlock(&eb->file->table_lock); - DRM_DEBUG("Invalid object handle %d at index %d\n", - eb->exec[i].handle, i); err = -ENOENT; - goto err; + goto err_vma; } - __exec_to_vma(&eb->exec[i]) = INTERMEDIATE | (uintptr_t)obj; - } - spin_unlock(&eb->file->table_lock); - - for (i = slow_pass; i < count; i++) { - struct drm_i915_gem_object *obj; - - if (!(__exec_to_vma(&eb->exec[i]) & INTERMEDIATE)) - continue; - - /* - * NOTE: We can leak any vmas created here when something fails - * later on. But that's no issue since vma_unbind can deal with - * vmas which are not actually bound. And since only - * lookup_or_create exists as an interface to get at the vma - * from the (obj, vm) we don't run the risk of creating - * duplicated vmas for the same vm. - */ - obj = u64_to_ptr(typeof(*obj), - __exec_to_vma(&eb->exec[i]) & ~INTERMEDIATE); vma = i915_vma_instance(obj, eb->vm, NULL); if (unlikely(IS_ERR(vma))) { - DRM_DEBUG("Failed to lookup VMA\n"); err = PTR_ERR(vma); - goto err; + goto err_obj; } - /* First come, first served */ - if (!vma->ctx) { - vma->ctx = eb->ctx; - vma->ctx_handle = eb->exec[i].handle; - hlist_add_head(&vma->ctx_node, - ht_head(lut, eb->exec[i].handle)); - lut->ht_count++; - lut->ht_size |= I915_CTX_RESIZE_IN_PROGRESS; - if (i915_vma_is_ggtt(vma)) { - GEM_BUG_ON(obj->vma_hashed); - obj->vma_hashed = vma; - } + lut = kmem_cache_alloc(eb->i915->luts, GFP_KERNEL); + if (unlikely(!lut)) { + err = -ENOMEM; + goto err_obj; + } - i915_vma_get(vma); + err = radix_tree_insert(handles_vma, handle, vma); + if (unlikely(err)) { + kfree(lut); + goto err_obj; } - err = eb_add_vma(eb, &eb->exec[i], vma); - if (unlikely(err)) - goto err; + list_add(&lut->obj_link, &obj->lut_list); + list_add(&lut->ctx_link, &eb->ctx->handles_list); + lut->ctx = eb->ctx; + lut->handle = handle; - /* Only after we validated the user didn't use our bits */ - if (vma->ctx != eb->ctx) { - i915_vma_get(vma); - eb->exec[i].flags |= __EXEC_OBJECT_HAS_REF; - } - } + /* transfer ref to ctx */ + obj = NULL; - if (lut->ht_size & I915_CTX_RESIZE_IN_PROGRESS) { - if (ht_needs_resize(lut)) - queue_work(system_highpri_wq, &lut->resize); - else - lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; +add_vma: + err = eb_add_vma(eb, i, vma); + if (unlikely(err)) + goto err_obj; + + GEM_BUG_ON(vma != eb->vma[i]); + GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); } -out: /* take note of the batch buffer before we might reorder the lists */ i = eb_batch_index(eb); - eb->batch = exec_to_vma(&eb->exec[i]); + eb->batch = eb->vma[i]; + GEM_BUG_ON(eb->batch->exec_flags != &eb->flags[i]); /* * SNA is doing fancy tricks with compressing batch buffers, which leads @@ -833,22 +751,20 @@ out: * Note that actual hangs have only been observed on gen7, but for * paranoia do it everywhere. */ - if (!(eb->exec[i].flags & EXEC_OBJECT_PINNED)) - eb->exec[i].flags |= __EXEC_OBJECT_NEEDS_BIAS; + if (!(eb->flags[i] & EXEC_OBJECT_PINNED)) + eb->flags[i] |= __EXEC_OBJECT_NEEDS_BIAS; if (eb->reloc_cache.has_fence) - eb->exec[i].flags |= EXEC_OBJECT_NEEDS_FENCE; + eb->flags[i] |= EXEC_OBJECT_NEEDS_FENCE; eb->args->flags |= __EXEC_VALIDATED; return eb_reserve(eb); -err: - for (i = slow_pass; i < count; i++) { - if (__exec_to_vma(&eb->exec[i]) & INTERMEDIATE) - __exec_to_vma(&eb->exec[i]) = 0; - } - lut->ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; +err_obj: + if (obj) + i915_gem_object_put(obj); +err_vma: + eb->vma[i] = NULL; return err; -#undef INTERMEDIATE } static struct i915_vma * @@ -857,7 +773,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) if (eb->lut_size < 0) { if (handle >= -eb->lut_size) return NULL; - return exec_to_vma(&eb->exec[handle]); + return eb->vma[handle]; } else { struct hlist_head *head; struct i915_vma *vma; @@ -877,24 +793,21 @@ static void eb_release_vmas(const struct i915_execbuffer *eb) unsigned int i; for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + struct i915_vma *vma = eb->vma[i]; + unsigned int flags = eb->flags[i]; if (!vma) - continue; + break; - GEM_BUG_ON(vma->exec_entry != entry); - vma->exec_entry = NULL; - __exec_to_vma(entry) = 0; + GEM_BUG_ON(vma->exec_flags != &eb->flags[i]); + vma->exec_flags = NULL; + eb->vma[i] = NULL; - if (entry->flags & __EXEC_OBJECT_HAS_PIN) - __eb_unreserve_vma(vma, entry); + if (flags & __EXEC_OBJECT_HAS_PIN) + __eb_unreserve_vma(vma, flags); - if (entry->flags & __EXEC_OBJECT_HAS_REF) + if (flags & __EXEC_OBJECT_HAS_REF) i915_vma_put(vma); - - entry->flags &= - ~(__EXEC_OBJECT_RESERVED | __EXEC_OBJECT_HAS_REF); } } @@ -1267,7 +1180,9 @@ relocate_entry(struct i915_vma *vma, if (!eb->reloc_cache.vaddr && (DBG_FORCE_RELOC == FORCE_GPU_RELOC || - !reservation_object_test_signaled_rcu(vma->resv, true))) { + !reservation_object_test_signaled_rcu(vma->resv, true)) && + __intel_engine_can_store_dword(eb->reloc_cache.gen, + eb->engine->class)) { const unsigned int gen = eb->reloc_cache.gen; unsigned int len; u32 *batch; @@ -1277,10 +1192,8 @@ relocate_entry(struct i915_vma *vma, len = offset & 7 ? 8 : 5; else if (gen >= 4) len = 4; - else if (gen >= 3) + else len = 3; - else /* On gen2 MI_STORE_DWORD_IMM uses a physical address */ - goto repeat; batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) @@ -1383,7 +1296,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, } if (reloc->write_domain) { - target->exec_entry->flags |= EXEC_OBJECT_WRITE; + *target->exec_flags |= EXEC_OBJECT_WRITE; /* * Sandybridge PPGTT errata: We need a global gtt mapping @@ -1433,9 +1346,9 @@ eb_relocate_entry(struct i915_execbuffer *eb, * patching using the GPU (though that should be serialised by the * timeline). To be completely sure, and since we are required to * do relocations we are already stalling, disable the user's opt - * of our synchronisation. + * out of our synchronisation. */ - vma->exec_entry->flags &= ~EXEC_OBJECT_ASYNC; + *vma->exec_flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ return relocate_entry(vma, reloc, eb, target); @@ -1446,7 +1359,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; struct drm_i915_gem_relocation_entry __user *urelocs; - const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; + const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); unsigned int remain; urelocs = u64_to_user_ptr(entry->relocs_ptr); @@ -1529,7 +1442,7 @@ out: static int eb_relocate_vma_slow(struct i915_execbuffer *eb, struct i915_vma *vma) { - const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; + const struct drm_i915_gem_exec_object2 *entry = exec_entry(eb, vma); struct drm_i915_gem_relocation_entry *relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); unsigned int i; @@ -1733,6 +1646,8 @@ repeat: if (err) goto err; + GEM_BUG_ON(!eb->batch); + list_for_each_entry(vma, &eb->relocs, reloc_link) { if (!have_copy) { pagefault_disable(); @@ -1826,11 +1741,11 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) int err; for (i = 0; i < count; i++) { - struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; struct drm_i915_gem_object *obj = vma->obj; - if (entry->flags & EXEC_OBJECT_CAPTURE) { + if (flags & EXEC_OBJECT_CAPTURE) { struct i915_gem_capture_list *capture; capture = kmalloc(sizeof(*capture), GFP_KERNEL); @@ -1838,35 +1753,47 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) return -ENOMEM; capture->next = eb->request->capture_list; - capture->vma = vma; + capture->vma = eb->vma[i]; eb->request->capture_list = capture; } - if (unlikely(obj->cache_dirty && !obj->cache_coherent)) { + /* + * If the GPU is not _reading_ through the CPU cache, we need + * to make sure that any writes (both previous GPU writes from + * before a change in snooping levels and normal CPU writes) + * caught in that cache are flushed to main memory. + * + * We want to say + * obj->cache_dirty && + * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) + * but gcc's optimiser doesn't handle that as well and emits + * two jumps instead of one. Maybe one day... + */ + if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { if (i915_gem_clflush_object(obj, 0)) - entry->flags &= ~EXEC_OBJECT_ASYNC; + flags &= ~EXEC_OBJECT_ASYNC; } - if (entry->flags & EXEC_OBJECT_ASYNC) - goto skip_flushes; + if (flags & EXEC_OBJECT_ASYNC) + continue; err = i915_gem_request_await_object - (eb->request, obj, entry->flags & EXEC_OBJECT_WRITE); + (eb->request, obj, flags & EXEC_OBJECT_WRITE); if (err) return err; - -skip_flushes: - i915_vma_move_to_active(vma, eb->request, entry->flags); - __eb_unreserve_vma(vma, entry); - vma->exec_entry = NULL; } for (i = 0; i < count; i++) { - const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; - struct i915_vma *vma = exec_to_vma(entry); + unsigned int flags = eb->flags[i]; + struct i915_vma *vma = eb->vma[i]; + + i915_vma_move_to_active(vma, eb->request, flags); + eb_export_fence(vma, eb->request, flags); - eb_export_fence(vma, eb->request, entry->flags); - if (unlikely(entry->flags & __EXEC_OBJECT_HAS_REF)) + __eb_unreserve_vma(vma, flags); + vma->exec_flags = NULL; + + if (unlikely(flags & __EXEC_OBJECT_HAS_REF)) i915_vma_put(vma); } eb->exec = NULL; @@ -1884,8 +1811,10 @@ static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) return false; /* Kernel clipping was a DRI1 misfeature */ - if (exec->num_cliprects || exec->cliprects_ptr) - return false; + if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) { + if (exec->num_cliprects || exec->cliprects_ptr) + return false; + } if (exec->DR4 == 0xffffffff) { DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); @@ -1993,11 +1922,11 @@ static struct i915_vma *eb_parse(struct i915_execbuffer *eb, bool is_master) if (IS_ERR(vma)) goto out; - vma->exec_entry = - memset(&eb->exec[eb->buffer_count++], - 0, sizeof(*vma->exec_entry)); - vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; - __exec_to_vma(vma->exec_entry) = (uintptr_t)i915_vma_get(vma); + eb->vma[eb->buffer_count] = i915_vma_get(vma); + eb->flags[eb->buffer_count] = + __EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_REF; + vma->exec_flags = &eb->flags[eb->buffer_count]; + eb->buffer_count++; out: i915_gem_object_unpin_pages(shadow_batch_obj); @@ -2116,11 +2045,131 @@ eb_select_engine(struct drm_i915_private *dev_priv, return engine; } +static void +__free_fence_array(struct drm_syncobj **fences, unsigned int n) +{ + while (n--) + drm_syncobj_put(ptr_mask_bits(fences[n], 2)); + kvfree(fences); +} + +static struct drm_syncobj ** +get_fence_array(struct drm_i915_gem_execbuffer2 *args, + struct drm_file *file) +{ + const unsigned int nfences = args->num_cliprects; + struct drm_i915_gem_exec_fence __user *user; + struct drm_syncobj **fences; + unsigned int n; + int err; + + if (!(args->flags & I915_EXEC_FENCE_ARRAY)) + return NULL; + + if (nfences > SIZE_MAX / sizeof(*fences)) + return ERR_PTR(-EINVAL); + + user = u64_to_user_ptr(args->cliprects_ptr); + if (!access_ok(VERIFY_READ, user, nfences * 2 * sizeof(u32))) + return ERR_PTR(-EFAULT); + + fences = kvmalloc_array(args->num_cliprects, sizeof(*fences), + __GFP_NOWARN | GFP_TEMPORARY); + if (!fences) + return ERR_PTR(-ENOMEM); + + for (n = 0; n < nfences; n++) { + struct drm_i915_gem_exec_fence fence; + struct drm_syncobj *syncobj; + + if (__copy_from_user(&fence, user++, sizeof(fence))) { + err = -EFAULT; + goto err; + } + + syncobj = drm_syncobj_find(file, fence.handle); + if (!syncobj) { + DRM_DEBUG("Invalid syncobj handle provided\n"); + err = -ENOENT; + goto err; + } + + fences[n] = ptr_pack_bits(syncobj, fence.flags, 2); + } + + return fences; + +err: + __free_fence_array(fences, n); + return ERR_PTR(err); +} + +static void +put_fence_array(struct drm_i915_gem_execbuffer2 *args, + struct drm_syncobj **fences) +{ + if (fences) + __free_fence_array(fences, args->num_cliprects); +} + +static int +await_fence_array(struct i915_execbuffer *eb, + struct drm_syncobj **fences) +{ + const unsigned int nfences = eb->args->num_cliprects; + unsigned int n; + int err; + + for (n = 0; n < nfences; n++) { + struct drm_syncobj *syncobj; + struct dma_fence *fence; + unsigned int flags; + + syncobj = ptr_unpack_bits(fences[n], &flags, 2); + if (!(flags & I915_EXEC_FENCE_WAIT)) + continue; + + rcu_read_lock(); + fence = dma_fence_get_rcu_safe(&syncobj->fence); + rcu_read_unlock(); + if (!fence) + return -EINVAL; + + err = i915_gem_request_await_dma_fence(eb->request, fence); + dma_fence_put(fence); + if (err < 0) + return err; + } + + return 0; +} + +static void +signal_fence_array(struct i915_execbuffer *eb, + struct drm_syncobj **fences) +{ + const unsigned int nfences = eb->args->num_cliprects; + struct dma_fence * const fence = &eb->request->fence; + unsigned int n; + + for (n = 0; n < nfences; n++) { + struct drm_syncobj *syncobj; + unsigned int flags; + + syncobj = ptr_unpack_bits(fences[n], &flags, 2); + if (!(flags & I915_EXEC_FENCE_SIGNAL)) + continue; + + drm_syncobj_replace_fence(syncobj, fence); + } +} + static int i915_gem_do_execbuffer(struct drm_device *dev, struct drm_file *file, struct drm_i915_gem_execbuffer2 *args, - struct drm_i915_gem_exec_object2 *exec) + struct drm_i915_gem_exec_object2 *exec, + struct drm_syncobj **fences) { struct i915_execbuffer eb; struct dma_fence *in_fence = NULL; @@ -2136,7 +2185,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.args = args; if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; + eb.exec = exec; + eb.vma = (struct i915_vma **)(exec + args->buffer_count + 1); + eb.vma[0] = NULL; + eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1); + eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; if (USES_FULL_PPGTT(eb.i915)) eb.invalid_flags |= EXEC_OBJECT_NEEDS_GTT; @@ -2224,7 +2278,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } - if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) { + if (unlikely(*eb.batch->exec_flags & EXEC_OBJECT_WRITE)) { DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); err = -EINVAL; goto err_vma; @@ -2306,6 +2360,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_request; } + if (fences) { + err = await_fence_array(&eb, fences); + if (err) + goto err_request; + } + if (out_fence_fd != -1) { out_fence = sync_file_create(&eb.request->fence); if (!out_fence) { @@ -2329,6 +2389,9 @@ err_request: __i915_add_request(eb.request, err == 0); add_to_client(eb.request, file); + if (fences) + signal_fence_array(&eb, fences); + if (out_fence) { if (err == 0) { fd_install(out_fence_fd, out_fence->file); @@ -2368,7 +2431,9 @@ int i915_gem_execbuffer(struct drm_device *dev, void *data, struct drm_file *file) { - const size_t sz = sizeof(struct drm_i915_gem_exec_object2); + const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) + + sizeof(struct i915_vma *) + + sizeof(unsigned int)); struct drm_i915_gem_execbuffer *args = data; struct drm_i915_gem_execbuffer2 exec2; struct drm_i915_gem_exec_object *exec_list = NULL; @@ -2430,7 +2495,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, exec2_list[i].flags = 0; } - err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list); + err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL); if (exec2.flags & __EXEC_HAS_RELOC) { struct drm_i915_gem_exec_object __user *user_exec_list = u64_to_user_ptr(args->buffers_ptr); @@ -2459,9 +2524,12 @@ int i915_gem_execbuffer2(struct drm_device *dev, void *data, struct drm_file *file) { - const size_t sz = sizeof(struct drm_i915_gem_exec_object2); + const size_t sz = (sizeof(struct drm_i915_gem_exec_object2) + + sizeof(struct i915_vma *) + + sizeof(unsigned int)); struct drm_i915_gem_execbuffer2 *args = data; struct drm_i915_gem_exec_object2 *exec2_list; + struct drm_syncobj **fences = NULL; int err; if (args->buffer_count < 1 || args->buffer_count > SIZE_MAX / sz - 1) { @@ -2488,7 +2556,15 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, return -EFAULT; } - err = i915_gem_do_execbuffer(dev, file, args, exec2_list); + if (args->flags & I915_EXEC_FENCE_ARRAY) { + fences = get_fence_array(args, file); + if (IS_ERR(fences)) { + kvfree(exec2_list); + return PTR_ERR(fences); + } + } + + err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences); /* * Now that we have begun execution of the batchbuffer, we ignore @@ -2518,6 +2594,7 @@ end_user: } args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; + put_fence_array(args, fences); kvfree(exec2_list); return err; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 10aa7762d9a6..d60f38adc4c4 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -144,9 +144,9 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; if (intel_vgpu_active(dev_priv)) { - /* emulation is too hard */ + /* GVT-g has no support for 32bit ppgtt */ has_full_ppgtt = false; - has_full_48bit_ppgtt = false; + has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv); } if (!has_aliasing_ppgtt) @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; } - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) - return has_full_48bit_ppgtt ? 3 : 2; - else - return has_aliasing_ppgtt ? 1 : 0; + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { + if (has_full_48bit_ppgtt) + return 3; + + if (has_full_ppgtt) + return 2; + } + + return has_aliasing_ppgtt ? 1 : 0; } static int ppgtt_bind_vma(struct i915_vma *vma, @@ -2737,6 +2742,24 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return 0; } +static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv) +{ + /* XXX: spec is unclear if this is still needed for CNL+ */ + if (!USES_PPGTT(dev_priv)) { + I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC); + return; + } + + I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC); + I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); + I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); + I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC); + I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); + I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); + I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); + I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); +} + /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability * bits. When using advanced contexts each context stores its own PAT, but * writing this data shouldn't be harmful even in those cases. */ @@ -2851,7 +2874,9 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; - if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + cnl_setup_private_ppat(dev_priv); + else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); @@ -3133,7 +3158,9 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) ggtt->base.closed = false; if (INTEL_GEN(dev_priv) >= 8) { - if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + cnl_setup_private_ppat(dev_priv); + else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) chv_setup_private_ppat(dev_priv); else bdw_setup_private_ppat(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c b/drivers/gpu/drm/i915/i915_gem_internal.c index 568bf83af1f5..c1f64ddaf8aa 100644 --- a/drivers/gpu/drm/i915/i915_gem_internal.c +++ b/drivers/gpu/drm/i915/i915_gem_internal.c @@ -174,6 +174,7 @@ i915_gem_object_create_internal(struct drm_i915_private *i915, phys_addr_t size) { struct drm_i915_gem_object *obj; + unsigned int cache_level; GEM_BUG_ON(!size); GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE)); @@ -190,9 +191,9 @@ i915_gem_object_create_internal(struct drm_i915_private *i915, obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); return obj; } diff --git a/drivers/gpu/drm/i915/i915_gem_object.c b/drivers/gpu/drm/i915/i915_gem_object.c new file mode 100644 index 000000000000..aab8cdd80e6d --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gem_object.c @@ -0,0 +1,48 @@ +/* + * Copyright © 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "i915_drv.h" +#include "i915_gem_object.h" + +/** + * Mark up the object's coherency levels for a given cache_level + * @obj: #drm_i915_gem_object + * @cache_level: cache level + */ +void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, + unsigned int cache_level) +{ + obj->cache_level = cache_level; + + if (cache_level != I915_CACHE_NONE) + obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ | + I915_BO_CACHE_COHERENT_FOR_WRITE); + else if (HAS_LLC(to_i915(obj->base.dev))) + obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ; + else + obj->cache_coherent = 0; + + obj->cache_dirty = + !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE); +} diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 5b19a4916a4d..c30d8f808185 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -33,8 +33,24 @@ #include <drm/i915_drm.h> +#include "i915_gem_request.h" #include "i915_selftest.h" +struct drm_i915_gem_object; + +/* + * struct i915_lut_handle tracks the fast lookups from handle to vma used + * for execbuf. Although we use a radixtree for that mapping, in order to + * remove them as the object or context is closed, we need a secondary list + * and a translation entry (i915_lut_handle). + */ +struct i915_lut_handle { + struct list_head obj_link; + struct list_head ctx_link; + struct i915_gem_context *ctx; + u32 handle; +}; + struct drm_i915_gem_object_ops { unsigned int flags; #define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0) @@ -86,7 +102,15 @@ struct drm_i915_gem_object { * They are also added to @vma_list for easy iteration. */ struct rb_root vma_tree; - struct i915_vma *vma_hashed; + + /** + * @lut_list: List of vma lookup entries in use for this object. + * + * If this object is closed, we need to remove all of its VMA from + * the fast lookup index in associated contexts; @lut_list provides + * this translation from object to context->handles_vma. + */ + struct list_head lut_list; /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; @@ -118,8 +142,10 @@ struct drm_i915_gem_object { */ unsigned long gt_ro:1; unsigned int cache_level:3; + unsigned int cache_coherent:2; +#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) +#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) unsigned int cache_dirty:1; - unsigned int cache_coherent:1; atomic_t frontbuffer_bits; unsigned int frontbuffer_ggtt_origin; /* write once */ @@ -391,6 +417,8 @@ i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) return engine; } +void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, + unsigned int cache_level); void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj); #endif diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 7032c542a9b1..4dd4c2159a92 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct drm_i915_gem_request *req) goto err_unpin; } + ret = req->engine->emit_flush(req, EMIT_INVALIDATE); + if (ret) + goto err_unpin; + ret = req->engine->emit_bb_start(req, so->batch_offset, so->batch_size, I915_DISPATCH_SECURE); diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 483af8921060..813a3b546d6e 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -213,6 +213,10 @@ static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno) cond_resched(); } + /* Check we are idle before we fiddle with hw state! */ + GEM_BUG_ON(!intel_engine_is_idle(engine)); + GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); + /* Finally reset hw state */ intel_engine_init_global_seqno(engine, seqno); tl->seqno = seqno; @@ -240,27 +244,60 @@ int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno) return reset_all_global_seqno(dev_priv, seqno - 1); } -static int reserve_seqno(struct intel_engine_cs *engine) +static void mark_busy(struct drm_i915_private *i915) { + if (i915->gt.awake) + return; + + GEM_BUG_ON(!i915->gt.active_requests); + + intel_runtime_pm_get_noresume(i915); + i915->gt.awake = true; + + intel_enable_gt_powersave(i915); + i915_update_gfx_val(i915); + if (INTEL_GEN(i915) >= 6) + gen6_rps_busy(i915); + + queue_delayed_work(i915->wq, + &i915->gt.retire_work, + round_jiffies_up_relative(HZ)); +} + +static int reserve_engine(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; u32 active = ++engine->timeline->inflight_seqnos; u32 seqno = engine->timeline->seqno; int ret; /* Reservation is fine until we need to wrap around */ - if (likely(!add_overflows(seqno, active))) - return 0; - - ret = reset_all_global_seqno(engine->i915, 0); - if (ret) { - engine->timeline->inflight_seqnos--; - return ret; + if (unlikely(add_overflows(seqno, active))) { + ret = reset_all_global_seqno(i915, 0); + if (ret) { + engine->timeline->inflight_seqnos--; + return ret; + } } + if (!i915->gt.active_requests++) + mark_busy(i915); + return 0; } -static void unreserve_seqno(struct intel_engine_cs *engine) +static void unreserve_engine(struct intel_engine_cs *engine) { + struct drm_i915_private *i915 = engine->i915; + + if (!--i915->gt.active_requests) { + /* Cancel the mark_busy() from our reserve_engine() */ + GEM_BUG_ON(!i915->gt.awake); + mod_delayed_work(i915->wq, + &i915->gt.idle_work, + msecs_to_jiffies(100)); + } + GEM_BUG_ON(!engine->timeline->inflight_seqnos); engine->timeline->inflight_seqnos--; } @@ -329,13 +366,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) list_del_init(&request->link); spin_unlock_irq(&engine->timeline->lock); - if (!--request->i915->gt.active_requests) { - GEM_BUG_ON(!request->i915->gt.awake); - mod_delayed_work(request->i915->wq, - &request->i915->gt.idle_work, - msecs_to_jiffies(100)); - } - unreserve_seqno(request->engine); + unreserve_engine(request->engine); advance_ring(request); free_capture_list(request); @@ -370,8 +401,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request) i915_gem_request_remove_from_client(request); /* Retirement decays the ban score as it is a sign of ctx progress */ - if (request->ctx->ban_score > 0) - request->ctx->ban_score--; + atomic_dec_if_positive(&request->ctx->ban_score); /* The backing object for the context is done after switching to the * *next* context. Therefore we cannot retire the previous context until @@ -572,7 +602,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, return ERR_CAST(ring); GEM_BUG_ON(!ring); - ret = reserve_seqno(engine); + ret = reserve_engine(engine); if (ret) goto err_unpin; @@ -678,7 +708,7 @@ err_ctx: kmem_cache_free(dev_priv->requests, req); err_unreserve: - unreserve_seqno(engine); + unreserve_engine(engine); err_unpin: engine->context_unpin(engine, ctx); return ERR_PTR(ret); @@ -860,28 +890,6 @@ i915_gem_request_await_object(struct drm_i915_gem_request *to, return ret; } -static void i915_gem_mark_busy(const struct intel_engine_cs *engine) -{ - struct drm_i915_private *dev_priv = engine->i915; - - if (dev_priv->gt.awake) - return; - - GEM_BUG_ON(!dev_priv->gt.active_requests); - - intel_runtime_pm_get_noresume(dev_priv); - dev_priv->gt.awake = true; - - intel_enable_gt_powersave(dev_priv); - i915_update_gfx_val(dev_priv); - if (INTEL_GEN(dev_priv) >= 6) - gen6_rps_busy(dev_priv); - - queue_delayed_work(dev_priv->wq, - &dev_priv->gt.retire_work, - round_jiffies_up_relative(HZ)); -} - /* * NB: This function is not allowed to fail. Doing so would mean the the * request is not being tracked for completion but the work itself is @@ -963,9 +971,6 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) list_add_tail(&request->ring_link, &ring->request_list); request->emitted_jiffies = jiffies; - if (!request->i915->gt.active_requests++) - i915_gem_mark_busy(engine); - /* Let the backend know a new request has arrived that may need * to adjust the existing execution schedule due to a high priority * request - i.e. we may want to preempt the current request in order @@ -1068,7 +1073,7 @@ static bool __i915_wait_request_check_and_reset(struct drm_i915_gem_request *req return false; __set_current_state(TASK_RUNNING); - i915_reset(request->i915); + i915_reset(request->i915, 0); return true; } diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index a817b3e0b17e..507c9f0d8df1 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -254,9 +254,10 @@ static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv) * This is a BIOS w/a: Some BIOS wrap stolen in the root * PCI bus, but have an off-by-one error. Hence retry the * reservation starting from 1 instead of 0. + * There's also BIOS with off-by-one on the other end. */ r = devm_request_mem_region(dev_priv->drm.dev, base + 1, - ggtt->stolen_size - 1, + ggtt->stolen_size - 2, "Graphics Stolen Memory"); /* * GEN3 firmware likes to smash pci bridges into the stolen @@ -579,6 +580,7 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, struct drm_mm_node *stolen) { struct drm_i915_gem_object *obj; + unsigned int cache_level; obj = i915_gem_object_alloc(dev_priv); if (obj == NULL) @@ -589,8 +591,8 @@ _i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, obj->stolen = stolen; obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT; - obj->cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = true; /* assumptions! more like cache_oblivious */ + cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); if (i915_gem_object_pin_pages(obj)) goto cleanup; diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c index ccd09e8419f5..f152a38d7079 100644 --- a/drivers/gpu/drm/i915/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/i915_gem_userptr.c @@ -804,9 +804,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file i915_gem_object_init(obj, &i915_gem_userptr_ops); obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = I915_CACHE_LLC; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); obj->userptr.ptr = args->user_ptr; obj->userptr.read_only = !!(args->flags & I915_USERPTR_READ_ONLY); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index ae70283470a6..ed5a1eb839ad 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1266,7 +1266,7 @@ static void record_request(struct drm_i915_gem_request *request, struct drm_i915_error_request *erq) { erq->context = request->ctx->hw_id; - erq->ban_score = request->ctx->ban_score; + erq->ban_score = atomic_read(&request->ctx->ban_score); erq->seqno = request->global_seqno; erq->jiffies = request->emitted_jiffies; erq->head = request->head; @@ -1357,9 +1357,9 @@ static void record_context(struct drm_i915_error_context *e, e->handle = ctx->user_handle; e->hw_id = ctx->hw_id; - e->ban_score = ctx->ban_score; - e->guilty = ctx->guilty_count; - e->active = ctx->active_count; + e->ban_score = atomic_read(&ctx->ban_score); + e->guilty = atomic_read(&ctx->guilty_count); + e->active = atomic_read(&ctx->active_count); } static void request_record_user_bo(struct drm_i915_gem_request *request, diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index eb4f1dca2077..e21ce9c18b6e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -275,17 +275,17 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; } static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; } static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) { - return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; + return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; } /** @@ -1501,7 +1501,8 @@ static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, *pin_mask |= BIT(i); - if (!intel_hpd_pin_to_port(i, &port)) + port = intel_hpd_pin_to_port(i); + if (port == PORT_NONE) continue; if (long_pulse_detect(port, dig_hotplug_reg)) @@ -1661,7 +1662,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) spin_unlock(&dev_priv->irq_lock); } - if (INTEL_INFO(dev_priv)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) return; if (HAS_VEBOX(dev_priv)) { @@ -1708,18 +1709,6 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) } } -static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, - enum pipe pipe) -{ - bool ret; - - ret = drm_handle_vblank(&dev_priv->drm, pipe); - if (ret) - intel_finish_page_flip_mmio(dev_priv, pipe); - - return ret; -} - static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, u32 iir, u32 pipe_stats[I915_MAX_PIPES]) { @@ -1784,12 +1773,8 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; for_each_pipe(dev_priv, pipe) { - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) - intel_finish_page_flip_cs(dev_priv, pipe); + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -2086,10 +2071,10 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); if (pch_iir & SDE_TRANSA_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); if (pch_iir & SDE_TRANSB_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); } static void ivb_err_int_handler(struct drm_i915_private *dev_priv) @@ -2123,13 +2108,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) DRM_ERROR("PCH poison interrupt\n"); if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) - intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); + intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C); I915_WRITE(SERR_INT, serr_int); } @@ -2241,19 +2226,14 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, DRM_ERROR("Poison interrupt\n"); for_each_pipe(dev_priv, pipe) { - if (de_iir & DE_PIPE_VBLANK(pipe) && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); + if (de_iir & DE_PIPE_VBLANK(pipe)) + drm_handle_vblank(&dev_priv->drm, pipe); if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); if (de_iir & DE_PIPE_CRC_DONE(pipe)) i9xx_pipe_crc_irq_handler(dev_priv, pipe); - - /* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE(pipe)) - intel_finish_page_flip_cs(dev_priv, pipe); } /* check event from PCH */ @@ -2292,13 +2272,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, intel_opregion_asle_intr(dev_priv); for_each_pipe(dev_priv, pipe) { - if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - /* plane/pipes map 1:1 on ilk+ */ - if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) - intel_finish_page_flip_cs(dev_priv, pipe); + if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) + drm_handle_vblank(&dev_priv->drm, pipe); } /* check event from PCH */ @@ -2440,7 +2415,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; tmp_mask = GEN8_AUX_CHANNEL_A; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) tmp_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; @@ -2479,7 +2454,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } for_each_pipe(dev_priv, pipe) { - u32 flip_done, fault_errors; + u32 fault_errors; if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) continue; @@ -2493,18 +2468,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); - if (iir & GEN8_PIPE_VBLANK && - intel_pipe_handle_vblank(dev_priv, pipe)) - intel_check_page_flip(dev_priv, pipe); - - flip_done = iir; - if (INTEL_INFO(dev_priv)->gen >= 9) - flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; - else - flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; - - if (flip_done) - intel_finish_page_flip_cs(dev_priv, pipe); + if (iir & GEN8_PIPE_VBLANK) + drm_handle_vblank(&dev_priv->drm, pipe); if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -2513,7 +2478,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); fault_errors = iir; - if (INTEL_INFO(dev_priv)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; else fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -2660,7 +2625,7 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) */ do { if (mutex_trylock(&dev_priv->drm.struct_mutex)) { - i915_reset(dev_priv); + i915_reset(dev_priv, 0); mutex_unlock(&dev_priv->drm.struct_mutex); } } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags, @@ -2676,32 +2641,6 @@ static void i915_reset_device(struct drm_i915_private *dev_priv) KOBJ_CHANGE, reset_done_event); } -static inline void -i915_err_print_instdone(struct drm_i915_private *dev_priv, - struct intel_instdone *instdone) -{ - int slice; - int subslice; - - pr_err(" INSTDONE: 0x%08x\n", instdone->instdone); - - if (INTEL_GEN(dev_priv) <= 3) - return; - - pr_err(" SC_INSTDONE: 0x%08x\n", instdone->slice_common); - - if (INTEL_GEN(dev_priv) <= 6) - return; - - for_each_instdone_slice_subslice(dev_priv, slice, subslice) - pr_err(" SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", - slice, subslice, instdone->sampler[slice][subslice]); - - for_each_instdone_slice_subslice(dev_priv, slice, subslice) - pr_err(" ROW_INSTDONE[%d][%d]: 0x%08x\n", - slice, subslice, instdone->row[slice][subslice]); -} - static void i915_clear_error_registers(struct drm_i915_private *dev_priv) { u32 eir; @@ -2770,12 +2709,12 @@ void i915_handle_error(struct drm_i915_private *dev_priv, */ if (intel_has_reset_engine(dev_priv)) { for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { - BUILD_BUG_ON(I915_RESET_HANDOFF >= I915_RESET_ENGINE); + BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, &dev_priv->gpu_error.flags)) continue; - if (i915_reset_engine(engine) == 0) + if (i915_reset_engine(engine, 0) == 0) engine_mask &= ~intel_engine_flag(engine); clear_bit(I915_RESET_ENGINE + engine->id, @@ -3074,7 +3013,7 @@ static void gen8_irq_reset(struct drm_device *dev) } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask) + u8 pipe_mask) { uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; @@ -3088,7 +3027,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, } void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask) + u8 pipe_mask) { enum pipe pipe; @@ -3492,7 +3431,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_misc_masked = GEN8_DE_MISC_GSE; enum pipe pipe; - if (INTEL_INFO(dev_priv)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | @@ -3675,34 +3614,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev) /* * Returns true when a page flip has completed. */ -static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, - int plane, int pipe, u32 iir) -{ - u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); - - if (!intel_pipe_handle_vblank(dev_priv, pipe)) - return false; - - if ((iir & flip_pending) == 0) - goto check_page_flip; - - /* We detect FlipDone by looking for the change in PendingFlip from '1' - * to '0' on the following vblank, i.e. IIR has the Pendingflip - * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence - * the flip is completed (no longer pending). Since this doesn't raise - * an interrupt per se, we watch for the change at vblank. - */ - if (I915_READ16(ISR) & flip_pending) - goto check_page_flip; - - intel_finish_page_flip_cs(dev_priv, pipe); - return true; - -check_page_flip: - intel_check_page_flip(dev_priv, pipe); - return false; -} - static irqreturn_t i8xx_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; @@ -3710,9 +3621,6 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) u16 iir, new_iir; u32 pipe_stats[2]; int pipe; - u16 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; irqreturn_t ret; if (!intel_irqs_enabled(dev_priv)) @@ -3726,7 +3634,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) if (iir == 0) goto out; - while (iir & ~flip_mask) { + while (iir) { /* Can't rely on pipestat interrupt bit in iir as it might * have been cleared after the pipestat interrupt was received. * It doesn't set the bit in iir again, but it still produces @@ -3748,7 +3656,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) } spin_unlock(&dev_priv->irq_lock); - I915_WRITE16(IIR, iir & ~flip_mask); + I915_WRITE16(IIR, iir); new_iir = I915_READ16(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -3759,9 +3667,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) if (HAS_FBC(dev_priv)) plane = !plane; - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && - i8xx_handle_vblank(dev_priv, plane, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); + if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -3861,45 +3768,11 @@ static int i915_irq_postinstall(struct drm_device *dev) return 0; } -/* - * Returns true when a page flip has completed. - */ -static bool i915_handle_vblank(struct drm_i915_private *dev_priv, - int plane, int pipe, u32 iir) -{ - u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); - - if (!intel_pipe_handle_vblank(dev_priv, pipe)) - return false; - - if ((iir & flip_pending) == 0) - goto check_page_flip; - - /* We detect FlipDone by looking for the change in PendingFlip from '1' - * to '0' on the following vblank, i.e. IIR has the Pendingflip - * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence - * the flip is completed (no longer pending). Since this doesn't raise - * an interrupt per se, we watch for the change at vblank. - */ - if (I915_READ(ISR) & flip_pending) - goto check_page_flip; - - intel_finish_page_flip_cs(dev_priv, pipe); - return true; - -check_page_flip: - intel_check_page_flip(dev_priv, pipe); - return false; -} - static irqreturn_t i915_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; struct drm_i915_private *dev_priv = to_i915(dev); u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; - u32 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; int pipe, ret = IRQ_NONE; if (!intel_irqs_enabled(dev_priv)) @@ -3910,7 +3783,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) iir = I915_READ(IIR); do { - bool irq_received = (iir & ~flip_mask) != 0; + bool irq_received = (iir) != 0; bool blc_event = false; /* Can't rely on pipestat interrupt bit in iir as it might @@ -3945,7 +3818,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) i9xx_hpd_irq_handler(dev_priv, hotplug_status); } - I915_WRITE(IIR, iir & ~flip_mask); + I915_WRITE(IIR, iir); new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -3956,9 +3829,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) if (HAS_FBC(dev_priv)) plane = !plane; - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && - i915_handle_vblank(dev_priv, plane, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); + if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -3991,7 +3863,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) */ ret = IRQ_HANDLED; iir = new_iir; - } while (iir & ~flip_mask); + } while (iir); enable_rpm_wakeref_asserts(dev_priv); @@ -4126,9 +3998,6 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) u32 iir, new_iir; u32 pipe_stats[I915_MAX_PIPES]; int ret = IRQ_NONE, pipe; - u32 flip_mask = - I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | - I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; if (!intel_irqs_enabled(dev_priv)) return IRQ_NONE; @@ -4139,7 +4008,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) iir = I915_READ(IIR); for (;;) { - bool irq_received = (iir & ~flip_mask) != 0; + bool irq_received = (iir) != 0; bool blc_event = false; /* Can't rely on pipestat interrupt bit in iir as it might @@ -4177,7 +4046,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) i9xx_hpd_irq_handler(dev_priv, hotplug_status); } - I915_WRITE(IIR, iir & ~flip_mask); + I915_WRITE(IIR, iir); new_iir = I915_READ(IIR); /* Flush posted writes */ if (iir & I915_USER_INTERRUPT) @@ -4186,9 +4055,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) notify_ring(dev_priv->engine[VCS]); for_each_pipe(dev_priv, pipe) { - if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && - i915_handle_vblank(dev_priv, pipe, pipe, iir)) - flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); + if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) + drm_handle_vblank(&dev_priv->drm, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -4290,16 +4158,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv) * * TODO: verify if this can be reproduced on VLV,CHV. */ - if (INTEL_INFO(dev_priv)->gen <= 7) + if (INTEL_GEN(dev_priv) <= 7) dev_priv->rps.pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_INFO(dev_priv)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) dev_priv->rps.pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; if (IS_GEN2(dev_priv)) { /* Gen2 doesn't have a hardware frame counter */ dev->max_vblank_count = 0; - } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { + } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ dev->driver->get_vblank_counter = g4x_get_vblank_counter; } else { @@ -4346,7 +4214,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = i965_enable_vblank; dev->driver->disable_vblank = i965_disable_vblank; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; - } else if (INTEL_INFO(dev_priv)->gen >= 8) { + } else if (INTEL_GEN(dev_priv) >= 8) { dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_preinstall = gen8_irq_reset; dev->driver->irq_postinstall = gen8_irq_postinstall; diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c index d4462c2aaaee..abdf4d0abcce 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.c +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -31,3981 +31,6 @@ #include "i915_drv.h" #include "i915_oa_bdw.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_DATA_PORT_READS_COALESCING, - METRIC_SET_ID_DATA_PORT_WRITES_COALESCING, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_L3_4, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER_1, - METRIC_SET_ID_SAMPLER_2, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_bdw = 22; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_0_slices_0x01[] = { - { _MMIO(0x9888), 0x143f000f }, - { _MMIO(0x9888), 0x14110014 }, - { _MMIO(0x9888), 0x14310014 }, - { _MMIO(0x9888), 0x14bf000f }, - { _MMIO(0x9888), 0x118a0317 }, - { _MMIO(0x9888), 0x13837be0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x005c4000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x003d8000 }, - { _MMIO(0x9888), 0x183d0800 }, - { _MMIO(0x9888), 0x0a3f0023 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x00584000 }, - { _MMIO(0x9888), 0x08584000 }, - { _MMIO(0x9888), 0x0a5a4000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b8000 }, - { _MMIO(0x9888), 0x185b2400 }, - { _MMIO(0x9888), 0x0a1d4000 }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18380001 }, - { _MMIO(0x9888), 0x00392000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a391000 }, - { _MMIO(0x9888), 0x00104000 }, - { _MMIO(0x9888), 0x08104000 }, - { _MMIO(0x9888), 0x00110030 }, - { _MMIO(0x9888), 0x08110031 }, - { _MMIO(0x9888), 0x10110000 }, - { _MMIO(0x9888), 0x00134000 }, - { _MMIO(0x9888), 0x16130020 }, - { _MMIO(0x9888), 0x06308000 }, - { _MMIO(0x9888), 0x08308000 }, - { _MMIO(0x9888), 0x06311800 }, - { _MMIO(0x9888), 0x08311880 }, - { _MMIO(0x9888), 0x10310000 }, - { _MMIO(0x9888), 0x0e334000 }, - { _MMIO(0x9888), 0x16330080 }, - { _MMIO(0x9888), 0x0abf1180 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x0ada8000 }, - { _MMIO(0x9888), 0x0a9d8000 }, - { _MMIO(0x9888), 0x109f0002 }, - { _MMIO(0x9888), 0x0ab94000 }, - { _MMIO(0x9888), 0x0d888000 }, - { _MMIO(0x9888), 0x038a0380 }, - { _MMIO(0x9888), 0x058a000e }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a00a0 }, - { _MMIO(0x9888), 0x078a0000 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x238b2820 }, - { _MMIO(0x9888), 0x258b2550 }, - { _MMIO(0x9888), 0x198c1000 }, - { _MMIO(0x9888), 0x0b8d8000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x0d831021 }, - { _MMIO(0x9888), 0x0f83572f }, - { _MMIO(0x9888), 0x01835680 }, - { _MMIO(0x9888), 0x0383002c }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830001 }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0x9888), 0x4d801110 }, - { _MMIO(0x9888), 0x4f800331 }, - { _MMIO(0x9888), 0x43800802 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801465 }, - { _MMIO(0x9888), 0x53801111 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800ca5 }, - { _MMIO(0x9888), 0x41800003 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_1_slices_0x02[] = { - { _MMIO(0x9888), 0x143f000f }, - { _MMIO(0x9888), 0x14bf000f }, - { _MMIO(0x9888), 0x14910014 }, - { _MMIO(0x9888), 0x14b10014 }, - { _MMIO(0x9888), 0x118a0317 }, - { _MMIO(0x9888), 0x13837be0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x0a3f0023 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x0a5a4000 }, - { _MMIO(0x9888), 0x0a1d4000 }, - { _MMIO(0x9888), 0x0e1f8000 }, - { _MMIO(0x9888), 0x0a391000 }, - { _MMIO(0x9888), 0x00dc4000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x00bd8000 }, - { _MMIO(0x9888), 0x18bd0800 }, - { _MMIO(0x9888), 0x0abf1180 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x00d84000 }, - { _MMIO(0x9888), 0x08d84000 }, - { _MMIO(0x9888), 0x0ada8000 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db2400 }, - { _MMIO(0x9888), 0x0a9d8000 }, - { _MMIO(0x9888), 0x0c9f0800 }, - { _MMIO(0x9888), 0x0e9f2a00 }, - { _MMIO(0x9888), 0x109f0002 }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b80001 }, - { _MMIO(0x9888), 0x00b92000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab94000 }, - { _MMIO(0x9888), 0x00904000 }, - { _MMIO(0x9888), 0x08904000 }, - { _MMIO(0x9888), 0x00910030 }, - { _MMIO(0x9888), 0x08910031 }, - { _MMIO(0x9888), 0x10910000 }, - { _MMIO(0x9888), 0x00934000 }, - { _MMIO(0x9888), 0x16930020 }, - { _MMIO(0x9888), 0x06b08000 }, - { _MMIO(0x9888), 0x08b08000 }, - { _MMIO(0x9888), 0x06b11800 }, - { _MMIO(0x9888), 0x08b11880 }, - { _MMIO(0x9888), 0x10b10000 }, - { _MMIO(0x9888), 0x0eb34000 }, - { _MMIO(0x9888), 0x16b30080 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88b800 }, - { _MMIO(0x9888), 0x038a0380 }, - { _MMIO(0x9888), 0x058a000e }, - { _MMIO(0x9888), 0x1b8a0080 }, - { _MMIO(0x9888), 0x078a0000 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x238b2840 }, - { _MMIO(0x9888), 0x258b26a0 }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1100 }, - { _MMIO(0x9888), 0x018d2000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8d8000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x0d831021 }, - { _MMIO(0x9888), 0x0f83572f }, - { _MMIO(0x9888), 0x01835680 }, - { _MMIO(0x9888), 0x0383002c }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830001 }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0x9888), 0x4d801550 }, - { _MMIO(0x9888), 0x4f800331 }, - { _MMIO(0x9888), 0x43800802 }, - { _MMIO(0x9888), 0x51800400 }, - { _MMIO(0x9888), 0x458004a1 }, - { _MMIO(0x9888), 0x53805555 }, - { _MMIO(0x9888), 0x47800421 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f801421 }, - { _MMIO(0x9888), 0x41800845 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) { - regs[n] = mux_config_render_basic_0_slices_0x01; - lens[n] = ARRAY_SIZE(mux_config_render_basic_0_slices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) { - regs[n] = mux_config_render_basic_1_slices_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_basic_1_slices_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01[] = { - { _MMIO(0x9888), 0x105c00e0 }, - { _MMIO(0x9888), 0x105800e0 }, - { _MMIO(0x9888), 0x103800e0 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x065c2100 }, - { _MMIO(0x9888), 0x0a5c0041 }, - { _MMIO(0x9888), 0x0c5c6600 }, - { _MMIO(0x9888), 0x005c6580 }, - { _MMIO(0x9888), 0x085c8000 }, - { _MMIO(0x9888), 0x0e5c8000 }, - { _MMIO(0x9888), 0x00580042 }, - { _MMIO(0x9888), 0x08582080 }, - { _MMIO(0x9888), 0x0c58004c }, - { _MMIO(0x9888), 0x0e582580 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x185b1000 }, - { _MMIO(0x9888), 0x1a5b0104 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x08380042 }, - { _MMIO(0x9888), 0x0a382080 }, - { _MMIO(0x9888), 0x0e38404c }, - { _MMIO(0x9888), 0x0238404b }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x16380000 }, - { _MMIO(0x9888), 0x18381145 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b5550 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f850a80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x03844000 }, - { _MMIO(0x9888), 0x17808137 }, - { _MMIO(0x9888), 0x1980c147 }, - { _MMIO(0x9888), 0x1b80c0e5 }, - { _MMIO(0x9888), 0x1d80c0e3 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x13804000 }, - { _MMIO(0x9888), 0x15800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x4f800111 }, - { _MMIO(0x9888), 0x43800062 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800062 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800062 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f801062 }, - { _MMIO(0x9888), 0x41801084 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_2_slices_0x02[] = { - { _MMIO(0x9888), 0x10dc00e0 }, - { _MMIO(0x9888), 0x10d800e0 }, - { _MMIO(0x9888), 0x10b800e0 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800005 }, - { _MMIO(0x9888), 0x06dc2100 }, - { _MMIO(0x9888), 0x0adc0041 }, - { _MMIO(0x9888), 0x0cdc6600 }, - { _MMIO(0x9888), 0x00dc6580 }, - { _MMIO(0x9888), 0x08dc8000 }, - { _MMIO(0x9888), 0x0edc8000 }, - { _MMIO(0x9888), 0x00d80042 }, - { _MMIO(0x9888), 0x08d82080 }, - { _MMIO(0x9888), 0x0cd8004c }, - { _MMIO(0x9888), 0x0ed82580 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x18db1000 }, - { _MMIO(0x9888), 0x1adb0104 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x08b80042 }, - { _MMIO(0x9888), 0x0ab82080 }, - { _MMIO(0x9888), 0x0eb8404c }, - { _MMIO(0x9888), 0x02b8404b }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x16b80000 }, - { _MMIO(0x9888), 0x18b81145 }, - { _MMIO(0x9888), 0x04b80000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b92000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x238b0540 }, - { _MMIO(0x9888), 0x258baaa0 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d2000 }, - { _MMIO(0x9888), 0x1f850a80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x03844000 }, - { _MMIO(0x9888), 0x17808137 }, - { _MMIO(0x9888), 0x1980c147 }, - { _MMIO(0x9888), 0x1b80c0e5 }, - { _MMIO(0x9888), 0x1d80c0e3 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x13804000 }, - { _MMIO(0x9888), 0x15800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d805000 }, - { _MMIO(0x9888), 0x4f800555 }, - { _MMIO(0x9888), 0x43800062 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800062 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800062 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800062 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) { - regs[n] = mux_config_compute_basic_0_slices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.slice_mask & 0x02) { - regs[n] = mux_config_compute_basic_2_slices_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_2_slices_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0a1e0000 }, - { _MMIO(0x9888), 0x0c1f000f }, - { _MMIO(0x9888), 0x10176800 }, - { _MMIO(0x9888), 0x1191001f }, - { _MMIO(0x9888), 0x0b880320 }, - { _MMIO(0x9888), 0x01890c40 }, - { _MMIO(0x9888), 0x118a1c00 }, - { _MMIO(0x9888), 0x118d7c00 }, - { _MMIO(0x9888), 0x118e0020 }, - { _MMIO(0x9888), 0x118f4c00 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x13900001 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x0c3d8000 }, - { _MMIO(0x9888), 0x06584000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x081e0040 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x021f5400 }, - { _MMIO(0x9888), 0x001f0000 }, - { _MMIO(0x9888), 0x101f0010 }, - { _MMIO(0x9888), 0x0e1f0080 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c13c000 }, - { _MMIO(0x9888), 0x06164000 }, - { _MMIO(0x9888), 0x06170012 }, - { _MMIO(0x9888), 0x00170000 }, - { _MMIO(0x9888), 0x01910005 }, - { _MMIO(0x9888), 0x07880002 }, - { _MMIO(0x9888), 0x01880c00 }, - { _MMIO(0x9888), 0x0f880000 }, - { _MMIO(0x9888), 0x0d880000 }, - { _MMIO(0x9888), 0x05880000 }, - { _MMIO(0x9888), 0x09890032 }, - { _MMIO(0x9888), 0x078a0800 }, - { _MMIO(0x9888), 0x0f8a0a00 }, - { _MMIO(0x9888), 0x198a4000 }, - { _MMIO(0x9888), 0x1b8a2000 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x038a4000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b54c0 }, - { _MMIO(0x9888), 0x258baa55 }, - { _MMIO(0x9888), 0x278b0019 }, - { _MMIO(0x9888), 0x198c0100 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x0f8d0015 }, - { _MMIO(0x9888), 0x018d1000 }, - { _MMIO(0x9888), 0x098d8000 }, - { _MMIO(0x9888), 0x0b8df000 }, - { _MMIO(0x9888), 0x0d8d3000 }, - { _MMIO(0x9888), 0x038de000 }, - { _MMIO(0x9888), 0x058d3000 }, - { _MMIO(0x9888), 0x0d8e0004 }, - { _MMIO(0x9888), 0x058e000c }, - { _MMIO(0x9888), 0x098e0000 }, - { _MMIO(0x9888), 0x078e0000 }, - { _MMIO(0x9888), 0x038e0000 }, - { _MMIO(0x9888), 0x0b8f0020 }, - { _MMIO(0x9888), 0x198f0c00 }, - { _MMIO(0x9888), 0x078f8000 }, - { _MMIO(0x9888), 0x098f4000 }, - { _MMIO(0x9888), 0x0b900980 }, - { _MMIO(0x9888), 0x03900d80 }, - { _MMIO(0x9888), 0x01900000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801111 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f801011 }, - { _MMIO(0x9888), 0x43800443 }, - { _MMIO(0x9888), 0x51801111 }, - { _MMIO(0x9888), 0x45800422 }, - { _MMIO(0x9888), 0x53801111 }, - { _MMIO(0x9888), 0x47800c60 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800422 }, - { _MMIO(0x9888), 0x41800021 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x198b0343 }, - { _MMIO(0x9888), 0x13845800 }, - { _MMIO(0x9888), 0x15840018 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b6b62 }, - { _MMIO(0x9888), 0x078b006a }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b0000 }, - { _MMIO(0x9888), 0x258b0000 }, - { _MMIO(0x9888), 0x1f85a080 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385000a }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01840018 }, - { _MMIO(0x9888), 0x07844c80 }, - { _MMIO(0x9888), 0x09840d9a }, - { _MMIO(0x9888), 0x0b840e9c }, - { _MMIO(0x9888), 0x0d840f9e }, - { _MMIO(0x9888), 0x0f840010 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x03848000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x2f8000e5 }, - { _MMIO(0x9888), 0x138080e3 }, - { _MMIO(0x9888), 0x1580c0e1 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f804000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800842 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801042 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800084 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x198b0343 }, - { _MMIO(0x9888), 0x13845400 }, - { _MMIO(0x9888), 0x3580001a }, - { _MMIO(0x9888), 0x3d800805 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b6b62 }, - { _MMIO(0x9888), 0x078b006a }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b0000 }, - { _MMIO(0x9888), 0x258b0000 }, - { _MMIO(0x9888), 0x1f85a080 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x23850002 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01840010 }, - { _MMIO(0x9888), 0x07844880 }, - { _MMIO(0x9888), 0x09840992 }, - { _MMIO(0x9888), 0x0b840a94 }, - { _MMIO(0x9888), 0x0d840b96 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x03848000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x2d800147 }, - { _MMIO(0x9888), 0x2f8000e5 }, - { _MMIO(0x9888), 0x138080e3 }, - { _MMIO(0x9888), 0x1580c0e1 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f800000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800842 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801082 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800084 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x143d0160 }, - { _MMIO(0x9888), 0x163d2800 }, - { _MMIO(0x9888), 0x183d0120 }, - { _MMIO(0x9888), 0x105800e0 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x003d0011 }, - { _MMIO(0x9888), 0x063d0900 }, - { _MMIO(0x9888), 0x083d0a13 }, - { _MMIO(0x9888), 0x0a3d0b15 }, - { _MMIO(0x9888), 0x0c3d2317 }, - { _MMIO(0x9888), 0x043d21b7 }, - { _MMIO(0x9888), 0x103d0000 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0e5825c1 }, - { _MMIO(0x9888), 0x00586100 }, - { _MMIO(0x9888), 0x0258204c }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x0c58c000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5400 }, - { _MMIO(0x9888), 0x1a5b0155 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_2_subslices_0x02[] = { - { _MMIO(0x9888), 0x105c00e0 }, - { _MMIO(0x9888), 0x145b0160 }, - { _MMIO(0x9888), 0x165b2800 }, - { _MMIO(0x9888), 0x185b0120 }, - { _MMIO(0x9888), 0x0e5c25c1 }, - { _MMIO(0x9888), 0x005c6100 }, - { _MMIO(0x9888), 0x025c204c }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x005b0011 }, - { _MMIO(0x9888), 0x065b0900 }, - { _MMIO(0x9888), 0x085b0a13 }, - { _MMIO(0x9888), 0x0a5b0b15 }, - { _MMIO(0x9888), 0x0c5b2317 }, - { _MMIO(0x9888), 0x045b21b7 }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x0e5b0000 }, - { _MMIO(0x9888), 0x1a5b0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_4_subslices_0x04[] = { - { _MMIO(0x9888), 0x103800e0 }, - { _MMIO(0x9888), 0x143a0160 }, - { _MMIO(0x9888), 0x163a2800 }, - { _MMIO(0x9888), 0x183a0120 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faa2a }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e38a5c1 }, - { _MMIO(0x9888), 0x0038a100 }, - { _MMIO(0x9888), 0x0238204c }, - { _MMIO(0x9888), 0x16388000 }, - { _MMIO(0x9888), 0x183802aa }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06380000 }, - { _MMIO(0x9888), 0x08388000 }, - { _MMIO(0x9888), 0x0a388000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x003a0011 }, - { _MMIO(0x9888), 0x063a0900 }, - { _MMIO(0x9888), 0x083a0a13 }, - { _MMIO(0x9888), 0x0a3a0b15 }, - { _MMIO(0x9888), 0x0c3a2317 }, - { _MMIO(0x9888), 0x043a21b7 }, - { _MMIO(0x9888), 0x103a0000 }, - { _MMIO(0x9888), 0x0e3a0000 }, - { _MMIO(0x9888), 0x1a3a0000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x238b2aa0 }, - { _MMIO(0x9888), 0x258b5551 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_1_subslices_0x08[] = { - { _MMIO(0x9888), 0x14bd0160 }, - { _MMIO(0x9888), 0x16bd2800 }, - { _MMIO(0x9888), 0x18bd0120 }, - { _MMIO(0x9888), 0x10d800e0 }, - { _MMIO(0x9888), 0x00dcc000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x00bd0011 }, - { _MMIO(0x9888), 0x06bd0900 }, - { _MMIO(0x9888), 0x08bd0a13 }, - { _MMIO(0x9888), 0x0abd0b15 }, - { _MMIO(0x9888), 0x0cbd2317 }, - { _MMIO(0x9888), 0x04bd21b7 }, - { _MMIO(0x9888), 0x10bd0000 }, - { _MMIO(0x9888), 0x0ebd0000 }, - { _MMIO(0x9888), 0x1abd0000 }, - { _MMIO(0x9888), 0x0ed825c1 }, - { _MMIO(0x9888), 0x00d86100 }, - { _MMIO(0x9888), 0x02d8204c }, - { _MMIO(0x9888), 0x06d88000 }, - { _MMIO(0x9888), 0x08d8c000 }, - { _MMIO(0x9888), 0x0ad8c000 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x04d8c000 }, - { _MMIO(0x9888), 0x00db4000 }, - { _MMIO(0x9888), 0x0edb4000 }, - { _MMIO(0x9888), 0x18db5400 }, - { _MMIO(0x9888), 0x1adb0155 }, - { _MMIO(0x9888), 0x02db4000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db4000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b81555 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_3_subslices_0x10[] = { - { _MMIO(0x9888), 0x10dc00e0 }, - { _MMIO(0x9888), 0x14db0160 }, - { _MMIO(0x9888), 0x16db2800 }, - { _MMIO(0x9888), 0x18db0120 }, - { _MMIO(0x9888), 0x0edc25c1 }, - { _MMIO(0x9888), 0x00dc6100 }, - { _MMIO(0x9888), 0x02dc204c }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dcc000 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x00db0011 }, - { _MMIO(0x9888), 0x06db0900 }, - { _MMIO(0x9888), 0x08db0a13 }, - { _MMIO(0x9888), 0x0adb0b15 }, - { _MMIO(0x9888), 0x0cdb2317 }, - { _MMIO(0x9888), 0x04db21b7 }, - { _MMIO(0x9888), 0x10db0000 }, - { _MMIO(0x9888), 0x0edb0000 }, - { _MMIO(0x9888), 0x1adb0000 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x00b84000 }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b81555 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_5_subslices_0x20[] = { - { _MMIO(0x9888), 0x10b800e0 }, - { _MMIO(0x9888), 0x14ba0160 }, - { _MMIO(0x9888), 0x16ba2800 }, - { _MMIO(0x9888), 0x18ba0120 }, - { _MMIO(0x9888), 0x0c9fa800 }, - { _MMIO(0x9888), 0x0e9faa2a }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb8a5c1 }, - { _MMIO(0x9888), 0x00b8a100 }, - { _MMIO(0x9888), 0x02b8204c }, - { _MMIO(0x9888), 0x16b88000 }, - { _MMIO(0x9888), 0x18b802aa }, - { _MMIO(0x9888), 0x04b80000 }, - { _MMIO(0x9888), 0x06b80000 }, - { _MMIO(0x9888), 0x08b88000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x00b9a000 }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x00ba0011 }, - { _MMIO(0x9888), 0x06ba0900 }, - { _MMIO(0x9888), 0x08ba0a13 }, - { _MMIO(0x9888), 0x0aba0b15 }, - { _MMIO(0x9888), 0x0cba2317 }, - { _MMIO(0x9888), 0x04ba21b7 }, - { _MMIO(0x9888), 0x10ba0000 }, - { _MMIO(0x9888), 0x0eba0000 }, - { _MMIO(0x9888), 0x1aba0000 }, - { _MMIO(0x9888), 0x01888000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x238b5540 }, - { _MMIO(0x9888), 0x258baaa2 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x018c4000 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x018da000 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa2 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 6); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 6); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_compute_extended_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x08) { - regs[n] = mux_config_compute_extended_1_subslices_0x08; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_1_subslices_0x08); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x02) { - regs[n] = mux_config_compute_extended_2_subslices_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_2_subslices_0x02); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x10) { - regs[n] = mux_config_compute_extended_3_subslices_0x10; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_3_subslices_0x10); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x04) { - regs[n] = mux_config_compute_extended_4_subslices_0x04; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_4_subslices_0x04); - n++; - } - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x20) { - regs[n] = mux_config_compute_extended_5_subslices_0x20; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_5_subslices_0x20); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x143f00b3 }, - { _MMIO(0x9888), 0x14bf00b3 }, - { _MMIO(0x9888), 0x138303c0 }, - { _MMIO(0x9888), 0x3b800060 }, - { _MMIO(0x9888), 0x3d800805 }, - { _MMIO(0x9888), 0x003f0029 }, - { _MMIO(0x9888), 0x063f1400 }, - { _MMIO(0x9888), 0x083f1225 }, - { _MMIO(0x9888), 0x0e3f1327 }, - { _MMIO(0x9888), 0x103f0000 }, - { _MMIO(0x9888), 0x005a4000 }, - { _MMIO(0x9888), 0x065a8000 }, - { _MMIO(0x9888), 0x085ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x001d4000 }, - { _MMIO(0x9888), 0x061d8000 }, - { _MMIO(0x9888), 0x081dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1f2a00 }, - { _MMIO(0x9888), 0x101f0280 }, - { _MMIO(0x9888), 0x00391000 }, - { _MMIO(0x9888), 0x06394000 }, - { _MMIO(0x9888), 0x08395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x0abf1429 }, - { _MMIO(0x9888), 0x0cbf1225 }, - { _MMIO(0x9888), 0x00bf1380 }, - { _MMIO(0x9888), 0x02bf0026 }, - { _MMIO(0x9888), 0x10bf0000 }, - { _MMIO(0x9888), 0x0adac000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02da4000 }, - { _MMIO(0x9888), 0x0a9dc000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029d4000 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f002a }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0ab95000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b91000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f880003 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a8020 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x238b0520 }, - { _MMIO(0x9888), 0x258ba950 }, - { _MMIO(0x9888), 0x278b0016 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0001 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x03835180 }, - { _MMIO(0x9888), 0x05834022 }, - { _MMIO(0x9888), 0x11830000 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x05844000 }, - { _MMIO(0x9888), 0x1b80c137 }, - { _MMIO(0x9888), 0x1d80c147 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x15804000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x4f800111 }, - { _MMIO(0x9888), 0x43800842 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800840 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800800 }, - { _MMIO(0x9888), 0x418014a2 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0xba98ba98 }, - { _MMIO(0x2748), 0xba98ba98 }, - { _MMIO(0x2744), 0x00003377 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fff2 }, - { _MMIO(0x2774), 0x00007ff0 }, - { _MMIO(0x2778), 0x0007ffe2 }, - { _MMIO(0x277c), 0x00007ff0 }, - { _MMIO(0x2780), 0x0007ffc2 }, - { _MMIO(0x2784), 0x00007ff0 }, - { _MMIO(0x2788), 0x0007ff82 }, - { _MMIO(0x278c), 0x00007ff0 }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000bfef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000bfdf }, - { _MMIO(0x27a0), 0x0007fffa }, - { _MMIO(0x27a4), 0x0000bfbf }, - { _MMIO(0x27a8), 0x0007fffa }, - { _MMIO(0x27ac), 0x0000bf7f }, -}; - -static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_data_port_reads_coalescing_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x103d0005 }, - { _MMIO(0x9888), 0x163d240b }, - { _MMIO(0x9888), 0x1058022f }, - { _MMIO(0x9888), 0x185b5520 }, - { _MMIO(0x9888), 0x198b0003 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065cc000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025c4000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x003d0000 }, - { _MMIO(0x9888), 0x063d00b0 }, - { _MMIO(0x9888), 0x083d0182 }, - { _MMIO(0x9888), 0x0a3d10a0 }, - { _MMIO(0x9888), 0x0c3d11a2 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x183d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0e582242 }, - { _MMIO(0x9888), 0x00586700 }, - { _MMIO(0x9888), 0x0258004f }, - { _MMIO(0x9888), 0x0658c000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x0c58c000 }, - { _MMIO(0x9888), 0x045b6300 }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x1a5b0155 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x0a5b0000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faaa0 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381555 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x0639a000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x04398000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b0062 }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b5555 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800001 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800041 }, -}; - -static int -get_data_port_reads_coalescing_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_data_port_reads_coalescing_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_data_port_reads_coalescing_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0xba98ba98 }, - { _MMIO(0x2748), 0xba98ba98 }, - { _MMIO(0x2744), 0x00003377 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ff72 }, - { _MMIO(0x2774), 0x0000bfd0 }, - { _MMIO(0x2778), 0x0007ff62 }, - { _MMIO(0x277c), 0x0000bfd0 }, - { _MMIO(0x2780), 0x0007ff42 }, - { _MMIO(0x2784), 0x0000bfd0 }, - { _MMIO(0x2788), 0x0007ff02 }, - { _MMIO(0x278c), 0x0000bfd0 }, - { _MMIO(0x2790), 0x0005fff2 }, - { _MMIO(0x2794), 0x0000bfd0 }, - { _MMIO(0x2798), 0x0005ffe2 }, - { _MMIO(0x279c), 0x0000bfd0 }, - { _MMIO(0x27a0), 0x0005ffc2 }, - { _MMIO(0x27a4), 0x0000bfd0 }, - { _MMIO(0x27a8), 0x0005ff82 }, - { _MMIO(0x27ac), 0x0000bfd0 }, -}; - -static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_data_port_writes_coalescing_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x103d0005 }, - { _MMIO(0x9888), 0x143d0120 }, - { _MMIO(0x9888), 0x163d2400 }, - { _MMIO(0x9888), 0x1058022f }, - { _MMIO(0x9888), 0x105b0000 }, - { _MMIO(0x9888), 0x198b0003 }, - { _MMIO(0x9888), 0x005cc000 }, - { _MMIO(0x9888), 0x065cc000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0e5cc000 }, - { _MMIO(0x9888), 0x025c4000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x003d0000 }, - { _MMIO(0x9888), 0x063d0094 }, - { _MMIO(0x9888), 0x083d0182 }, - { _MMIO(0x9888), 0x0a3d1814 }, - { _MMIO(0x9888), 0x0e3d0000 }, - { _MMIO(0x9888), 0x183d0000 }, - { _MMIO(0x9888), 0x1a3d0000 }, - { _MMIO(0x9888), 0x0c3d0000 }, - { _MMIO(0x9888), 0x0e582242 }, - { _MMIO(0x9888), 0x00586700 }, - { _MMIO(0x9888), 0x0258004f }, - { _MMIO(0x9888), 0x0658c000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x0a58c000 }, - { _MMIO(0x9888), 0x045b6a80 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5400 }, - { _MMIO(0x9888), 0x1a5b0141 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x0a5b0000 }, - { _MMIO(0x9888), 0x0c5b4000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1faaa0 }, - { _MMIO(0x9888), 0x101f0282 }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18381415 }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x0039a000 }, - { _MMIO(0x9888), 0x0639a000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x02392000 }, - { _MMIO(0x9888), 0x04398000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a82a0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x038b6300 }, - { _MMIO(0x9888), 0x058b0062 }, - { _MMIO(0x9888), 0x118b0000 }, - { _MMIO(0x9888), 0x238b02a0 }, - { _MMIO(0x9888), 0x258b1555 }, - { _MMIO(0x9888), 0x278b0014 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x21852aaa }, - { _MMIO(0x9888), 0x23850028 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830141 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0xd24), 0x00000000 }, - { _MMIO(0x9888), 0x4d801000 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f800001 }, - { _MMIO(0x9888), 0x43800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800420 }, - { _MMIO(0x9888), 0x3f800421 }, - { _MMIO(0x9888), 0x41800041 }, -}; - -static int -get_data_port_writes_coalescing_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_data_port_writes_coalescing_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_data_port_writes_coalescing_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fff7 }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x105c0232 }, - { _MMIO(0x9888), 0x10580232 }, - { _MMIO(0x9888), 0x10380232 }, - { _MMIO(0x9888), 0x10dc0232 }, - { _MMIO(0x9888), 0x10d80232 }, - { _MMIO(0x9888), 0x10b80232 }, - { _MMIO(0x9888), 0x118e4400 }, - { _MMIO(0x9888), 0x025c6080 }, - { _MMIO(0x9888), 0x045c004b }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x00582080 }, - { _MMIO(0x9888), 0x0258004b }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x04386080 }, - { _MMIO(0x9888), 0x0638404b }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a380000 }, - { _MMIO(0x9888), 0x0c380000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0cdc25c1 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0ad825c1 }, - { _MMIO(0x9888), 0x18db4000 }, - { _MMIO(0x9888), 0x1adb0001 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb825c1 }, - { _MMIO(0x9888), 0x18b80154 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baa05 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x098dc000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x098e05c0 }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x198f0020 }, - { _MMIO(0x9888), 0x2185aa0a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x19835000 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x19808000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x51800040 }, - { _MMIO(0x9888), 0x43800400 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800c62 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801042 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x418014a4 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x10bf03da }, - { _MMIO(0x9888), 0x14bf0001 }, - { _MMIO(0x9888), 0x12980340 }, - { _MMIO(0x9888), 0x12990340 }, - { _MMIO(0x9888), 0x0cbf1187 }, - { _MMIO(0x9888), 0x0ebf1205 }, - { _MMIO(0x9888), 0x00bf0500 }, - { _MMIO(0x9888), 0x02bf042b }, - { _MMIO(0x9888), 0x04bf002c }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02dac000 }, - { _MMIO(0x9888), 0x04da4000 }, - { _MMIO(0x9888), 0x04983400 }, - { _MMIO(0x9888), 0x10980000 }, - { _MMIO(0x9888), 0x06990034 }, - { _MMIO(0x9888), 0x10990000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029dc000 }, - { _MMIO(0x9888), 0x049d4000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00ba }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b95000 }, - { _MMIO(0x9888), 0x04b91000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0cba4000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x258b800a }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x103f03da }, - { _MMIO(0x9888), 0x143f0001 }, - { _MMIO(0x9888), 0x12180340 }, - { _MMIO(0x9888), 0x12190340 }, - { _MMIO(0x9888), 0x0c3f1187 }, - { _MMIO(0x9888), 0x0e3f1205 }, - { _MMIO(0x9888), 0x003f0500 }, - { _MMIO(0x9888), 0x023f042b }, - { _MMIO(0x9888), 0x043f002c }, - { _MMIO(0x9888), 0x0c5ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x04183400 }, - { _MMIO(0x9888), 0x10180000 }, - { _MMIO(0x9888), 0x06190034 }, - { _MMIO(0x9888), 0x10190000 }, - { _MMIO(0x9888), 0x0c1dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x101f02a8 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00ba }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a4000 }, - { _MMIO(0x9888), 0x1b8aa800 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258b4005 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x121b0340 }, - { _MMIO(0x9888), 0x103f0274 }, - { _MMIO(0x9888), 0x123f0000 }, - { _MMIO(0x9888), 0x129b0340 }, - { _MMIO(0x9888), 0x10bf0274 }, - { _MMIO(0x9888), 0x12bf0000 }, - { _MMIO(0x9888), 0x041b3400 }, - { _MMIO(0x9888), 0x101b0000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x0a3d4000 }, - { _MMIO(0x9888), 0x003f0080 }, - { _MMIO(0x9888), 0x023f0793 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f002a }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04399000 }, - { _MMIO(0x9888), 0x069b0034 }, - { _MMIO(0x9888), 0x109b0000 }, - { _MMIO(0x9888), 0x06dc4000 }, - { _MMIO(0x9888), 0x0cbd4000 }, - { _MMIO(0x9888), 0x0cbf0981 }, - { _MMIO(0x9888), 0x0ebf0a0f }, - { _MMIO(0x9888), 0x06d84000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0cdb4000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0080 }, - { _MMIO(0x9888), 0x0cb84000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800c00 }, - { _MMIO(0x9888), 0x47800c63 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a5 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800045 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_4[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_4[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_4[] = { - { _MMIO(0x9888), 0x121a0340 }, - { _MMIO(0x9888), 0x103f0017 }, - { _MMIO(0x9888), 0x123f0020 }, - { _MMIO(0x9888), 0x129a0340 }, - { _MMIO(0x9888), 0x10bf0017 }, - { _MMIO(0x9888), 0x12bf0020 }, - { _MMIO(0x9888), 0x041a3400 }, - { _MMIO(0x9888), 0x101a0000 }, - { _MMIO(0x9888), 0x043b8000 }, - { _MMIO(0x9888), 0x0a3e0010 }, - { _MMIO(0x9888), 0x003f0200 }, - { _MMIO(0x9888), 0x023f0113 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x02592000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a1c8000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0a1e8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f001a }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x069a0034 }, - { _MMIO(0x9888), 0x109a0000 }, - { _MMIO(0x9888), 0x06bb4000 }, - { _MMIO(0x9888), 0x0abe0040 }, - { _MMIO(0x9888), 0x0cbf0984 }, - { _MMIO(0x9888), 0x0ebf0a02 }, - { _MMIO(0x9888), 0x02d94000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0c9c0400 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x0c9e0400 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0040 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x47800842 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801084 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800044 }, -}; - -static int -get_l3_4_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_4; - lens[n] = ARRAY_SIZE(mux_config_l3_4); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00006000 }, - { _MMIO(0x2774), 0x0000f3ff }, - { _MMIO(0x2778), 0x00001800 }, - { _MMIO(0x277c), 0x0000fcff }, - { _MMIO(0x2780), 0x00000600 }, - { _MMIO(0x2784), 0x0000ff3f }, - { _MMIO(0x2788), 0x00000180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000060 }, - { _MMIO(0x2794), 0x0000fff3 }, - { _MMIO(0x2798), 0x00000018 }, - { _MMIO(0x279c), 0x0000fffc }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x143b000e }, - { _MMIO(0x9888), 0x043c55c0 }, - { _MMIO(0x9888), 0x0a1e0280 }, - { _MMIO(0x9888), 0x0c1e0408 }, - { _MMIO(0x9888), 0x10390000 }, - { _MMIO(0x9888), 0x12397a1f }, - { _MMIO(0x9888), 0x14bb000e }, - { _MMIO(0x9888), 0x04bc5000 }, - { _MMIO(0x9888), 0x0a9e0296 }, - { _MMIO(0x9888), 0x0c9e0008 }, - { _MMIO(0x9888), 0x10b90000 }, - { _MMIO(0x9888), 0x12b97a1f }, - { _MMIO(0x9888), 0x063b0042 }, - { _MMIO(0x9888), 0x103b0000 }, - { _MMIO(0x9888), 0x083c0000 }, - { _MMIO(0x9888), 0x0a3e0040 }, - { _MMIO(0x9888), 0x043f8000 }, - { _MMIO(0x9888), 0x02594000 }, - { _MMIO(0x9888), 0x045a8000 }, - { _MMIO(0x9888), 0x0c1c0400 }, - { _MMIO(0x9888), 0x041d8000 }, - { _MMIO(0x9888), 0x081e02c0 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1f0260 }, - { _MMIO(0x9888), 0x101f0014 }, - { _MMIO(0x9888), 0x003905e0 }, - { _MMIO(0x9888), 0x06390bc0 }, - { _MMIO(0x9888), 0x02390018 }, - { _MMIO(0x9888), 0x04394000 }, - { _MMIO(0x9888), 0x04bb0042 }, - { _MMIO(0x9888), 0x10bb0000 }, - { _MMIO(0x9888), 0x02bc05c0 }, - { _MMIO(0x9888), 0x08bc0000 }, - { _MMIO(0x9888), 0x0abe0004 }, - { _MMIO(0x9888), 0x02bf8000 }, - { _MMIO(0x9888), 0x02d91000 }, - { _MMIO(0x9888), 0x02da8000 }, - { _MMIO(0x9888), 0x089c8000 }, - { _MMIO(0x9888), 0x029d8000 }, - { _MMIO(0x9888), 0x089e8000 }, - { _MMIO(0x9888), 0x0e9e0000 }, - { _MMIO(0x9888), 0x0e9fa806 }, - { _MMIO(0x9888), 0x109f0142 }, - { _MMIO(0x9888), 0x08b90617 }, - { _MMIO(0x9888), 0x0ab90be0 }, - { _MMIO(0x9888), 0x02b94000 }, - { _MMIO(0x9888), 0x0d88f000 }, - { _MMIO(0x9888), 0x0f88000c }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x1b8a2800 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b52a0 }, - { _MMIO(0x9888), 0x258b6a95 }, - { _MMIO(0x9888), 0x278b0029 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1500 }, - { _MMIO(0x9888), 0x1b8c0014 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d8000 }, - { _MMIO(0x9888), 0x058d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4d800444 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f804000 }, - { _MMIO(0x9888), 0x43801080 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800084 }, - { _MMIO(0x9888), 0x53800044 }, - { _MMIO(0x9888), 0x47801080 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x41800840 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_1[] = { - { _MMIO(0x9888), 0x18921400 }, - { _MMIO(0x9888), 0x149500ab }, - { _MMIO(0x9888), 0x18b21400 }, - { _MMIO(0x9888), 0x14b500ab }, - { _MMIO(0x9888), 0x18d21400 }, - { _MMIO(0x9888), 0x14d500ab }, - { _MMIO(0x9888), 0x0cdc8000 }, - { _MMIO(0x9888), 0x0edc4000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x1abd00a0 }, - { _MMIO(0x9888), 0x0abd8000 }, - { _MMIO(0x9888), 0x0cd88000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x04d88000 }, - { _MMIO(0x9888), 0x1adb0050 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x06db8000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x109f02a0 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x18b82500 }, - { _MMIO(0x9888), 0x02b88000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb98000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x1aba0200 }, - { _MMIO(0x9888), 0x02ba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04908000 }, - { _MMIO(0x9888), 0x04918000 }, - { _MMIO(0x9888), 0x04927300 }, - { _MMIO(0x9888), 0x10920000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a934000 }, - { _MMIO(0x9888), 0x0a946000 }, - { _MMIO(0x9888), 0x0c959000 }, - { _MMIO(0x9888), 0x0e950098 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b04000 }, - { _MMIO(0x9888), 0x04b14000 }, - { _MMIO(0x9888), 0x04b20073 }, - { _MMIO(0x9888), 0x10b20000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x06b38000 }, - { _MMIO(0x9888), 0x08b34000 }, - { _MMIO(0x9888), 0x04b4c000 }, - { _MMIO(0x9888), 0x02b59890 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d04000 }, - { _MMIO(0x9888), 0x06d14000 }, - { _MMIO(0x9888), 0x06d20073 }, - { _MMIO(0x9888), 0x10d20000 }, - { _MMIO(0x9888), 0x18d30020 }, - { _MMIO(0x9888), 0x02d38000 }, - { _MMIO(0x9888), 0x0cd34000 }, - { _MMIO(0x9888), 0x0ad48000 }, - { _MMIO(0x9888), 0x04d42000 }, - { _MMIO(0x9888), 0x0ed59000 }, - { _MMIO(0x9888), 0x00d59800 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0f88000e }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x258b000a }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8d8000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_1; - lens[n] = ARRAY_SIZE(mux_config_sampler_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_2[] = { - { _MMIO(0x9888), 0x18121400 }, - { _MMIO(0x9888), 0x141500ab }, - { _MMIO(0x9888), 0x18321400 }, - { _MMIO(0x9888), 0x143500ab }, - { _MMIO(0x9888), 0x18521400 }, - { _MMIO(0x9888), 0x145500ab }, - { _MMIO(0x9888), 0x0c5c8000 }, - { _MMIO(0x9888), 0x0e5c4000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x1a3d00a0 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0c588000 }, - { _MMIO(0x9888), 0x0e584000 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x1a5b0050 }, - { _MMIO(0x9888), 0x045b8000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x101f02a0 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x18382500 }, - { _MMIO(0x9888), 0x02388000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c398000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x1a3a0200 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x04108000 }, - { _MMIO(0x9888), 0x04118000 }, - { _MMIO(0x9888), 0x04127300 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x1813000a }, - { _MMIO(0x9888), 0x0a134000 }, - { _MMIO(0x9888), 0x0a146000 }, - { _MMIO(0x9888), 0x0c159000 }, - { _MMIO(0x9888), 0x0e150098 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04304000 }, - { _MMIO(0x9888), 0x04314000 }, - { _MMIO(0x9888), 0x04320073 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x04338000 }, - { _MMIO(0x9888), 0x06338000 }, - { _MMIO(0x9888), 0x08334000 }, - { _MMIO(0x9888), 0x0434c000 }, - { _MMIO(0x9888), 0x02359890 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x06504000 }, - { _MMIO(0x9888), 0x06514000 }, - { _MMIO(0x9888), 0x06520073 }, - { _MMIO(0x9888), 0x10520000 }, - { _MMIO(0x9888), 0x18530020 }, - { _MMIO(0x9888), 0x02538000 }, - { _MMIO(0x9888), 0x0c534000 }, - { _MMIO(0x9888), 0x0a548000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x0e559000 }, - { _MMIO(0x9888), 0x00559800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x1b8aa000 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_2; - lens[n] = ARRAY_SIZE(mux_config_sampler_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000ffbf }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fff7 }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fff9 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x16154d60 }, - { _MMIO(0x9888), 0x16352e60 }, - { _MMIO(0x9888), 0x16554d60 }, - { _MMIO(0x9888), 0x16950000 }, - { _MMIO(0x9888), 0x16b50000 }, - { _MMIO(0x9888), 0x16d50000 }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x025b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04388000 }, - { _MMIO(0x9888), 0x06388000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x043a8000 }, - { _MMIO(0x9888), 0x063a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x0a138000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x0415cfc7 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x02338000 }, - { _MMIO(0x9888), 0x0c338000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x0035c700 }, - { _MMIO(0x9888), 0x063500cf }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04538000 }, - { _MMIO(0x9888), 0x06538000 }, - { _MMIO(0x9888), 0x0454c000 }, - { _MMIO(0x9888), 0x0255cfc7 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dc4000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x1abd00a8 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db0800 }, - { _MMIO(0x9888), 0x1adb0254 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b8156a }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x18baa000 }, - { _MMIO(0x9888), 0x1aba0002 }, - { _MMIO(0x9888), 0x16934000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a947000 }, - { _MMIO(0x9888), 0x0c95c5c1 }, - { _MMIO(0x9888), 0x0e9500c3 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x0eb38000 }, - { _MMIO(0x9888), 0x16b30040 }, - { _MMIO(0x9888), 0x18b30020 }, - { _MMIO(0x9888), 0x06b48000 }, - { _MMIO(0x9888), 0x08b41000 }, - { _MMIO(0x9888), 0x0ab48000 }, - { _MMIO(0x9888), 0x06b5c500 }, - { _MMIO(0x9888), 0x08b500c3 }, - { _MMIO(0x9888), 0x0eb5c100 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x16d31500 }, - { _MMIO(0x9888), 0x08d4e000 }, - { _MMIO(0x9888), 0x08d5c100 }, - { _MMIO(0x9888), 0x0ad5c3c5 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baaa5 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800c42 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800063 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800800 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a4 }, - { _MMIO(0x9888), 0x41801042 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000000 }, - { _MMIO(0x2784), 0x0000ff9f }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffe7 }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fffb }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000fffd }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x16150000 }, - { _MMIO(0x9888), 0x16350000 }, - { _MMIO(0x9888), 0x16550000 }, - { _MMIO(0x9888), 0x16952e60 }, - { _MMIO(0x9888), 0x16b54d60 }, - { _MMIO(0x9888), 0x16d52e60 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5c4000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183da000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x08588000 }, - { _MMIO(0x9888), 0x0a584000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5800 }, - { _MMIO(0x9888), 0x1a5b000a }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18382a55 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x1a3a02a0 }, - { _MMIO(0x9888), 0x0e138000 }, - { _MMIO(0x9888), 0x16130500 }, - { _MMIO(0x9888), 0x06148000 }, - { _MMIO(0x9888), 0x08146000 }, - { _MMIO(0x9888), 0x0615c100 }, - { _MMIO(0x9888), 0x0815c500 }, - { _MMIO(0x9888), 0x0a1500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x16335040 }, - { _MMIO(0x9888), 0x08349000 }, - { _MMIO(0x9888), 0x0a341000 }, - { _MMIO(0x9888), 0x083500c1 }, - { _MMIO(0x9888), 0x0a35c500 }, - { _MMIO(0x9888), 0x0c3500c3 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x1853002a }, - { _MMIO(0x9888), 0x0a54e000 }, - { _MMIO(0x9888), 0x0c55c500 }, - { _MMIO(0x9888), 0x0e55c1c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dc4000 }, - { _MMIO(0x9888), 0x04bd8000 }, - { _MMIO(0x9888), 0x06bd8000 }, - { _MMIO(0x9888), 0x02d8c000 }, - { _MMIO(0x9888), 0x02db8000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0aba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04938000 }, - { _MMIO(0x9888), 0x06938000 }, - { _MMIO(0x9888), 0x0494c000 }, - { _MMIO(0x9888), 0x0295cfc7 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x02b38000 }, - { _MMIO(0x9888), 0x08b38000 }, - { _MMIO(0x9888), 0x04b42000 }, - { _MMIO(0x9888), 0x06b41000 }, - { _MMIO(0x9888), 0x00b5c700 }, - { _MMIO(0x9888), 0x04b500cf }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x0ad38000 }, - { _MMIO(0x9888), 0x0cd38000 }, - { _MMIO(0x9888), 0x06d46000 }, - { _MMIO(0x9888), 0x04d5c700 }, - { _MMIO(0x9888), 0x06d500cf }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x258b555a }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800882 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801082 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800002 }, - { _MMIO(0x9888), 0x41800c62 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x161503e0 }, - { _MMIO(0x9888), 0x163503e0 }, - { _MMIO(0x9888), 0x165503e0 }, - { _MMIO(0x9888), 0x169503e0 }, - { _MMIO(0x9888), 0x16b503e0 }, - { _MMIO(0x9888), 0x16d503e0 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x04584000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b8000 }, - { _MMIO(0x9888), 0x0e1f00a8 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x06141000 }, - { _MMIO(0x9888), 0x041500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x0a338000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x0435c300 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x0c538000 }, - { _MMIO(0x9888), 0x06544000 }, - { _MMIO(0x9888), 0x065500c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dc4000 }, - { _MMIO(0x9888), 0x02bd8000 }, - { _MMIO(0x9888), 0x00d88000 }, - { _MMIO(0x9888), 0x02db4000 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f0002 }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x06ba8000 }, - { _MMIO(0x9888), 0x02938000 }, - { _MMIO(0x9888), 0x04942000 }, - { _MMIO(0x9888), 0x0095c300 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x04b44000 }, - { _MMIO(0x9888), 0x02b500c3 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d38000 }, - { _MMIO(0x9888), 0x04d48000 }, - { _MMIO(0x9888), 0x02d5c300 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b3500 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c40 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41801482 }, - { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x14100812 }, - { _MMIO(0x9888), 0x14125800 }, - { _MMIO(0x9888), 0x161200c0 }, - { _MMIO(0x9888), 0x14300812 }, - { _MMIO(0x9888), 0x14325800 }, - { _MMIO(0x9888), 0x163200c0 }, - { _MMIO(0x9888), 0x005c4000 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5cc000 }, - { _MMIO(0x9888), 0x003d8000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183d2800 }, - { _MMIO(0x9888), 0x00584000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x0858c000 }, - { _MMIO(0x9888), 0x005b4000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b9400 }, - { _MMIO(0x9888), 0x1a5b002a }, - { _MMIO(0x9888), 0x0c1f0800 }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f002a }, - { _MMIO(0x9888), 0x00384000 }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18380155 }, - { _MMIO(0x9888), 0x00392000 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x00100047 }, - { _MMIO(0x9888), 0x06101a80 }, - { _MMIO(0x9888), 0x10100000 }, - { _MMIO(0x9888), 0x0810c000 }, - { _MMIO(0x9888), 0x0811c000 }, - { _MMIO(0x9888), 0x08126151 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x00134000 }, - { _MMIO(0x9888), 0x0e134000 }, - { _MMIO(0x9888), 0x161300a0 }, - { _MMIO(0x9888), 0x0a301ac7 }, - { _MMIO(0x9888), 0x10300000 }, - { _MMIO(0x9888), 0x0c30c000 }, - { _MMIO(0x9888), 0x0c31c000 }, - { _MMIO(0x9888), 0x0c326151 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x16332a00 }, - { _MMIO(0x9888), 0x18330001 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8a2aa0 }, - { _MMIO(0x9888), 0x238b0020 }, - { _MMIO(0x9888), 0x258b5550 }, - { _MMIO(0x9888), 0x278b0001 }, - { _MMIO(0x9888), 0x1f850080 }, - { _MMIO(0x9888), 0x2185aaa0 }, - { _MMIO(0x9888), 0x23850002 }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830015 }, - { _MMIO(0x9888), 0x01844000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x11804000 }, - { _MMIO(0x9888), 0x17808000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3d800800 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800002 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800884 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800002 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -4035,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x000000a0 }, { _MMIO(0x9888), 0x198b0000 }, { _MMIO(0x9888), 0x078b0066 }, { _MMIO(0x9888), 0x118b0000 }, @@ -4047,1330 +73,38 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x4f800000 }, { _MMIO(0x9888), 0x41800000 }, { _MMIO(0x9888), 0x31800000 }, -}; - -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_DATA_PORT_READS_COALESCING: - dev_priv->perf.oa.n_mux_configs = - get_data_port_reads_coalescing_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_data_port_reads_coalescing; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_data_port_reads_coalescing); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_data_port_reads_coalescing; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing); - - return 0; - case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING: - dev_priv->perf.oa.n_mux_configs = - get_data_port_writes_coalescing_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_data_port_writes_coalescing; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_data_port_writes_coalescing); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_data_port_writes_coalescing; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_L3_4: - dev_priv->perf.oa.n_mux_configs = - get_l3_4_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_4; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_4); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_4; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_4); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER_1: - dev_priv->perf.oa.n_mux_configs = - get_sampler_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_1); - - return 0; - case METRIC_SET_ID_SAMPLER_2: - dev_priv->perf.oa.n_mux_configs = - get_sampler_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_2); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "35fbc9b2-a891-40a6-a38d-022bb7057552", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "233d0544-fff7-4281-8291-e02f222aff72", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "27a364dc-8225-4ecb-b607-d6f1925598d9", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING); -} - -static struct device_attribute dev_attr_data_port_reads_coalescing_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_data_port_reads_coalescing_id, - .store = NULL, -}; - -static struct attribute *attrs_data_port_reads_coalescing[] = { - &dev_attr_data_port_reads_coalescing_id.attr, - NULL, -}; - -static struct attribute_group group_data_port_reads_coalescing = { - .name = "857fc630-2f09-4804-85f1-084adfadd5ab", - .attrs = attrs_data_port_reads_coalescing, -}; - -static ssize_t -show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING); -} - -static struct device_attribute dev_attr_data_port_writes_coalescing_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_data_port_writes_coalescing_id, - .store = NULL, -}; - -static struct attribute *attrs_data_port_writes_coalescing[] = { - &dev_attr_data_port_writes_coalescing_id.attr, - NULL, -}; - -static struct attribute_group group_data_port_writes_coalescing = { - .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20", - .attrs = attrs_data_port_writes_coalescing, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "446ae59b-ff2e-41c9-b49e-0184a54bf00a", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "84a7956f-1ea4-4d0d-837f-e39a0376e38c", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); -} - -static struct device_attribute dev_attr_l3_4_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_4_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_4[] = { - &dev_attr_l3_4_id.attr, - NULL, -}; - -static struct attribute_group group_l3_4 = { - .name = "92b493d9-df18-4bed-be06-5cac6f2a6f5f", - .attrs = attrs_l3_4, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "14345c35-cc46-40d0-bb04-6ed1fbb43679", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); -} - -static struct device_attribute dev_attr_sampler_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_1_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_1[] = { - &dev_attr_sampler_1_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_1 = { - .name = "f0c6ba37-d3d3-4211-91b5-226730312a54", - .attrs = attrs_sampler_1, -}; - -static ssize_t -show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); -} - -static struct device_attribute dev_attr_sampler_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_2_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_2[] = { - &dev_attr_sampler_2_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_2 = { - .name = "30bf3702-48cf-4bca-b412-7cf50bb2f564", - .attrs = attrs_sampler_2, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "238bec85-df05-44f3-b905-d166712f2451", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "24bf02cd-8693-4583-981c-c4165b33da01", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "e1743ca0-7fc8-410b-a066-de7bbb9280b7", - .attrs = attrs_vme_pipe, + { _MMIO(0x9840), 0x00000080 }, }; static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "d6de6f55-e526-4f79-a6a6-d7315c09044e", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "d6de6f55-e526-4f79-a6a6-d7315c09044e", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); - if (ret) - goto error_data_port_reads_coalescing; - } - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); - if (ret) - goto error_data_port_writes_coalescing; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (ret) - goto error_l3_4; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (ret) - goto error_sampler_1; - } - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (ret) - goto error_sampler_2; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); -error_sampler_2: - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); -error_sampler_1: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); -error_l3_4: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); -error_data_port_writes_coalescing: - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); -error_data_port_reads_coalescing: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_data_port_reads_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); - if (get_data_port_writes_coalescing_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h b/drivers/gpu/drm/i915/i915_oa_bdw.h index 6363ff9f64c0..b812d16162ac 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.h +++ b/drivers/gpu/drm/i915/i915_oa_bdw.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_BDW_H__ #define __I915_OA_BDW_H__ -extern int i915_oa_n_builtin_metric_sets_bdw; - -extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_bdw(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_bdw(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.c b/drivers/gpu/drm/i915/i915_oa_bxt.c index 93864d8f32dd..b69b900de0fe 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.c +++ b/drivers/gpu/drm/i915/i915_oa_bxt.c @@ -31,1702 +31,6 @@ #include "i915_drv.h" #include "i915_oa_bxt.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_bxt = 15; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_0_sku_gte_0x03[] = { - { _MMIO(0x9888), 0x166c00f0 }, - { _MMIO(0x9888), 0x12120280 }, - { _MMIO(0x9888), 0x12320280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x419000a0 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2e0800 }, - { _MMIO(0x9888), 0x0e2e5900 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x1c4f0010 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a0fcc00 }, - { _MMIO(0x9888), 0x1c0f0002 }, - { _MMIO(0x9888), 0x1c2c0040 }, - { _MMIO(0x9888), 0x00101000 }, - { _MMIO(0x9888), 0x04101000 }, - { _MMIO(0x9888), 0x00114000 }, - { _MMIO(0x9888), 0x08114000 }, - { _MMIO(0x9888), 0x00120020 }, - { _MMIO(0x9888), 0x08120021 }, - { _MMIO(0x9888), 0x00141000 }, - { _MMIO(0x9888), 0x08141000 }, - { _MMIO(0x9888), 0x02308000 }, - { _MMIO(0x9888), 0x04302000 }, - { _MMIO(0x9888), 0x06318000 }, - { _MMIO(0x9888), 0x08318000 }, - { _MMIO(0x9888), 0x06320800 }, - { _MMIO(0x9888), 0x08320840 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x08344000 }, - { _MMIO(0x9888), 0x0d931831 }, - { _MMIO(0x9888), 0x0f939f3f }, - { _MMIO(0x9888), 0x01939e80 }, - { _MMIO(0x9888), 0x039303bc }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1993002a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900187 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901110 }, - { _MMIO(0x9888), 0x43900423 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900c02 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900020 }, - { _MMIO(0x9888), 0x59901111 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900821 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (dev_priv->drm.pdev->revision >= 0x03) { - regs[n] = mux_config_render_basic_0_sku_gte_0x03; - lens[n] = ARRAY_SIZE(mux_config_render_basic_0_sku_gte_0x03); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d4000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x0c2e1400 }, - { _MMIO(0x9888), 0x0e2e5100 }, - { _MMIO(0x9888), 0x102e0114 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004f6b42 }, - { _MMIO(0x9888), 0x064f6200 }, - { _MMIO(0x9888), 0x084f4100 }, - { _MMIO(0x9888), 0x0a4f0061 }, - { _MMIO(0x9888), 0x0c4f6c4c }, - { _MMIO(0x9888), 0x0e4f4b00 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0f8800 }, - { _MMIO(0x9888), 0x1c0f08a2 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c1451 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c0010 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x19938a28 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x19900177 }, - { _MMIO(0x9888), 0x1b900178 }, - { _MMIO(0x9888), 0x1d900125 }, - { _MMIO(0x9888), 0x1f900123 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c2e001f }, - { _MMIO(0x9888), 0x0a2f0000 }, - { _MMIO(0x9888), 0x10186800 }, - { _MMIO(0x9888), 0x11810019 }, - { _MMIO(0x9888), 0x15810013 }, - { _MMIO(0x9888), 0x13820020 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x17840000 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x21860000 }, - { _MMIO(0x9888), 0x178703e0 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x022e5400 }, - { _MMIO(0x9888), 0x002e0000 }, - { _MMIO(0x9888), 0x0e2e0080 }, - { _MMIO(0x9888), 0x082f0040 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x06174000 }, - { _MMIO(0x9888), 0x06180012 }, - { _MMIO(0x9888), 0x00180000 }, - { _MMIO(0x9888), 0x0d804000 }, - { _MMIO(0x9888), 0x0f804000 }, - { _MMIO(0x9888), 0x05804000 }, - { _MMIO(0x9888), 0x09810200 }, - { _MMIO(0x9888), 0x0b810030 }, - { _MMIO(0x9888), 0x03810003 }, - { _MMIO(0x9888), 0x21819140 }, - { _MMIO(0x9888), 0x23819050 }, - { _MMIO(0x9888), 0x25810018 }, - { _MMIO(0x9888), 0x0b820980 }, - { _MMIO(0x9888), 0x03820d80 }, - { _MMIO(0x9888), 0x11820000 }, - { _MMIO(0x9888), 0x0182c000 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x09824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0d830004 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x0f831000 }, - { _MMIO(0x9888), 0x01848072 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x09844000 }, - { _MMIO(0x9888), 0x0f848000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x09860092 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x01869100 }, - { _MMIO(0x9888), 0x0f870065 }, - { _MMIO(0x9888), 0x01870000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b952000 }, - { _MMIO(0x9888), 0x1d955055 }, - { _MMIO(0x9888), 0x1f951455 }, - { _MMIO(0x9888), 0x0992a000 }, - { _MMIO(0x9888), 0x0f928000 }, - { _MMIO(0x9888), 0x1192a800 }, - { _MMIO(0x9888), 0x1392028a }, - { _MMIO(0x9888), 0x0b92a000 }, - { _MMIO(0x9888), 0x0d922000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c01 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900863 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900c22 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x41900003 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900170 }, - { _MMIO(0x9888), 0x21900171 }, - { _MMIO(0x9888), 0x23900172 }, - { _MMIO(0x9888), 0x25900173 }, - { _MMIO(0x9888), 0x27900174 }, - { _MMIO(0x9888), 0x29900175 }, - { _MMIO(0x9888), 0x2b900176 }, - { _MMIO(0x9888), 0x2d900177 }, - { _MMIO(0x9888), 0x2f90017f }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900000 }, - { _MMIO(0x9888), 0x41900080 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900180 }, - { _MMIO(0x9888), 0x21900181 }, - { _MMIO(0x9888), 0x23900182 }, - { _MMIO(0x9888), 0x25900183 }, - { _MMIO(0x9888), 0x27900184 }, - { _MMIO(0x9888), 0x29900185 }, - { _MMIO(0x9888), 0x2b900186 }, - { _MMIO(0x9888), 0x2d900187 }, - { _MMIO(0x9888), 0x2f900170 }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x141c0160 }, - { _MMIO(0x9888), 0x161c0015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d5000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x0c2e5400 }, - { _MMIO(0x9888), 0x0e2e5515 }, - { _MMIO(0x9888), 0x102e0155 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x0e4cc000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0a4ea000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x0e4f4b41 }, - { _MMIO(0x9888), 0x004f4200 }, - { _MMIO(0x9888), 0x024f404c }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0a1bc000 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x001c0031 }, - { _MMIO(0x9888), 0x061c1900 }, - { _MMIO(0x9888), 0x081c1a33 }, - { _MMIO(0x9888), 0x0a1c1b35 }, - { _MMIO(0x9888), 0x0c1c3337 }, - { _MMIO(0x9888), 0x041c31c7 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0fa8aa }, - { _MMIO(0x9888), 0x1c0f0aaa }, - { _MMIO(0x9888), 0x182c8000 }, - { _MMIO(0x9888), 0x1c2c6aaa }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c2950 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993aaaa }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900400 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900001 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c03b0 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x0c2e0400 }, - { _MMIO(0x9888), 0x0e2e1500 }, - { _MMIO(0x9888), 0x102e0140 }, - { _MMIO(0x9888), 0x044c4000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004e2000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x1a4f4001 }, - { _MMIO(0x9888), 0x1c4f5005 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x180f1000 }, - { _MMIO(0x9888), 0x1a0fa800 }, - { _MMIO(0x9888), 0x1c0f0a00 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c4015 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x03931980 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993a00a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900178 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900400 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x022d4000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x064c8000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x024f6100 }, - { _MMIO(0x9888), 0x044f416b }, - { _MMIO(0x9888), 0x064f004b }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1a0f02a8 }, - { _MMIO(0x9888), 0x1a2c5500 }, - { _MMIO(0x9888), 0x0f808000 }, - { _MMIO(0x9888), 0x25810020 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1f951000 }, - { _MMIO(0x9888), 0x13920200 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4d900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1_0_sku_gte_0x03[] = { - { _MMIO(0x9888), 0x12643400 }, - { _MMIO(0x9888), 0x12653400 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x0a640024 }, - { _MMIO(0x9888), 0x10640000 }, - { _MMIO(0x9888), 0x04640000 }, - { _MMIO(0x9888), 0x0c650024 }, - { _MMIO(0x9888), 0x10650000 }, - { _MMIO(0x9888), 0x06650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static const struct i915_oa_reg mux_config_l3_1_0_sku_lt_0x03[] = { - { _MMIO(0x9888), 0x14640340 }, - { _MMIO(0x9888), 0x14650340 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x04642400 }, - { _MMIO(0x9888), 0x22640000 }, - { _MMIO(0x9888), 0x1a640000 }, - { _MMIO(0x9888), 0x06650024 }, - { _MMIO(0x9888), 0x22650000 }, - { _MMIO(0x9888), 0x1c650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (dev_priv->drm.pdev->revision >= 0x03) { - regs[n] = mux_config_l3_1_0_sku_gte_0x03; - lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_gte_0x03); - n++; - } - if (dev_priv->drm.pdev->revision < 0x03) { - regs[n] = mux_config_l3_1_0_sku_lt_0x03; - lens[n] = ARRAY_SIZE(mux_config_l3_1_0_sku_lt_0x03); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102d7800 }, - { _MMIO(0x9888), 0x122d79e0 }, - { _MMIO(0x9888), 0x0c2f0004 }, - { _MMIO(0x9888), 0x100e3800 }, - { _MMIO(0x9888), 0x180f0005 }, - { _MMIO(0x9888), 0x002d0940 }, - { _MMIO(0x9888), 0x022d802f }, - { _MMIO(0x9888), 0x042d4013 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0050 }, - { _MMIO(0x9888), 0x022f0010 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x040e0480 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x060f0027 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x1a0f0040 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x439014a0 }, - { _MMIO(0x9888), 0x459000a4 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x121300a0 }, - { _MMIO(0x9888), 0x141600ab }, - { _MMIO(0x9888), 0x123300a0 }, - { _MMIO(0x9888), 0x143600ab }, - { _MMIO(0x9888), 0x125300a0 }, - { _MMIO(0x9888), 0x145600ab }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e01a0 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0065 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0800 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f023f }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2cc030 }, - { _MMIO(0x9888), 0x04132180 }, - { _MMIO(0x9888), 0x02130000 }, - { _MMIO(0x9888), 0x0c148000 }, - { _MMIO(0x9888), 0x0e142000 }, - { _MMIO(0x9888), 0x04148000 }, - { _MMIO(0x9888), 0x1e150140 }, - { _MMIO(0x9888), 0x1c150040 }, - { _MMIO(0x9888), 0x0c163000 }, - { _MMIO(0x9888), 0x0e160068 }, - { _MMIO(0x9888), 0x10160000 }, - { _MMIO(0x9888), 0x18160000 }, - { _MMIO(0x9888), 0x0a164000 }, - { _MMIO(0x9888), 0x04330043 }, - { _MMIO(0x9888), 0x02330000 }, - { _MMIO(0x9888), 0x0234a000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x1c350015 }, - { _MMIO(0x9888), 0x02363460 }, - { _MMIO(0x9888), 0x10360000 }, - { _MMIO(0x9888), 0x04360000 }, - { _MMIO(0x9888), 0x06360000 }, - { _MMIO(0x9888), 0x08364000 }, - { _MMIO(0x9888), 0x06530043 }, - { _MMIO(0x9888), 0x02530000 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x06542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550100 }, - { _MMIO(0x9888), 0x0e563000 }, - { _MMIO(0x9888), 0x00563400 }, - { _MMIO(0x9888), 0x10560000 }, - { _MMIO(0x9888), 0x18560000 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x0c564000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9014a0 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900820 }, - { _MMIO(0x9888), 0x45901022 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x141a0000 }, - { _MMIO(0x9888), 0x143a0000 }, - { _MMIO(0x9888), 0x145a0000 }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0150 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e006a }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0bc0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f0302 }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2c00f0 }, - { _MMIO(0x9888), 0x021a3080 }, - { _MMIO(0x9888), 0x041a31e5 }, - { _MMIO(0x9888), 0x02148000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150054 }, - { _MMIO(0x9888), 0x06168000 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x0c3a3280 }, - { _MMIO(0x9888), 0x0e3a0063 }, - { _MMIO(0x9888), 0x063a0061 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x0c348000 }, - { _MMIO(0x9888), 0x0e342000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1e350140 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x18360028 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x0e5a3080 }, - { _MMIO(0x9888), 0x005a3280 }, - { _MMIO(0x9888), 0x025a0063 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x02542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550001 }, - { _MMIO(0x9888), 0x18560080 }, - { _MMIO(0x9888), 0x02568000 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x45901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x141a026b }, - { _MMIO(0x9888), 0x143a0173 }, - { _MMIO(0x9888), 0x145a026b }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0069 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x180f6000 }, - { _MMIO(0x9888), 0x1a0f030a }, - { _MMIO(0x9888), 0x1a2c03c0 }, - { _MMIO(0x9888), 0x041a37e7 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150050 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x003a3380 }, - { _MMIO(0x9888), 0x063a006f }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x00348000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1a352000 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x02368000 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x025a37e7 }, - { _MMIO(0x9888), 0x0254a000 }, - { _MMIO(0x9888), 0x1c550005 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x06568000 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900020 }, - { _MMIO(0x9888), 0x45901080 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x141a001f }, - { _MMIO(0x9888), 0x143a001f }, - { _MMIO(0x9888), 0x145a001f }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0094 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x1a0f00e0 }, - { _MMIO(0x9888), 0x1a2c0c00 }, - { _MMIO(0x9888), 0x061a0063 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x06142000 }, - { _MMIO(0x9888), 0x1c150100 }, - { _MMIO(0x9888), 0x0c168000 }, - { _MMIO(0x9888), 0x043a3180 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x04348000 }, - { _MMIO(0x9888), 0x1c350040 }, - { _MMIO(0x9888), 0x0a368000 }, - { _MMIO(0x9888), 0x045a0063 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x1c550010 }, - { _MMIO(0x9888), 0x08568000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900004 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1756,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x19800000 }, { _MMIO(0x9888), 0x07800063 }, { _MMIO(0x9888), 0x11800000 }, @@ -1769,922 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "012d72cf-82a9-4d25-8ddf-74076fd30797", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "ce416533-e49e-4211-80af-ec513590a914", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "398e2452-18d7-42d0-b241-e4d0a9148ada", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "caf3596a-7bb1-4dec-b3b3-2a080d283b49", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "00ad5a41-7eab-4f7a-9103-49d411c67219", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "8364e2a8-af63-40af-b0d5-42969a255654", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "d260f03f-b34d-4b49-a44e-436819117332", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a", - .attrs = attrs_compute_extra, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "5ee72f5c-092f-421e-8b70-225f7c3e9612", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "5ee72f5c-092f-421e-8b70-225f7c3e9612", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_bxt.h b/drivers/gpu/drm/i915/i915_oa_bxt.h index 6cf7ba746e7e..690b963a2383 100644 --- a/drivers/gpu/drm/i915/i915_oa_bxt.h +++ b/drivers/gpu/drm/i915/i915_oa_bxt.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_BXT_H__ #define __I915_OA_BXT_H__ -extern int i915_oa_n_builtin_metric_sets_bxt; - -extern int i915_oa_select_metric_set_bxt(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_bxt(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_bxt(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c index aa6bece7e75f..322a3f94cd16 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.c +++ b/drivers/gpu/drm/i915/i915_oa_chv.c @@ -31,1943 +31,6 @@ #include "i915_drv.h" #include "i915_oa_chv.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_L3_4, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER_1, - METRIC_SET_ID_SAMPLER_2, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_chv = 14; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x285a0006 }, - { _MMIO(0x9888), 0x2c110014 }, - { _MMIO(0x9888), 0x2e110000 }, - { _MMIO(0x9888), 0x2c310014 }, - { _MMIO(0x9888), 0x2e310000 }, - { _MMIO(0x9888), 0x2b8303df }, - { _MMIO(0x9888), 0x3580024f }, - { _MMIO(0x9888), 0x00580888 }, - { _MMIO(0x9888), 0x1e5a0015 }, - { _MMIO(0x9888), 0x205a0014 }, - { _MMIO(0x9888), 0x045a0000 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x02180500 }, - { _MMIO(0x9888), 0x00190555 }, - { _MMIO(0x9888), 0x021d0500 }, - { _MMIO(0x9888), 0x021f0a00 }, - { _MMIO(0x9888), 0x00380444 }, - { _MMIO(0x9888), 0x02390500 }, - { _MMIO(0x9888), 0x003a0666 }, - { _MMIO(0x9888), 0x00100111 }, - { _MMIO(0x9888), 0x06110030 }, - { _MMIO(0x9888), 0x0a110031 }, - { _MMIO(0x9888), 0x0e110046 }, - { _MMIO(0x9888), 0x04110000 }, - { _MMIO(0x9888), 0x00110000 }, - { _MMIO(0x9888), 0x00130111 }, - { _MMIO(0x9888), 0x00300444 }, - { _MMIO(0x9888), 0x08310030 }, - { _MMIO(0x9888), 0x0c310031 }, - { _MMIO(0x9888), 0x10310046 }, - { _MMIO(0x9888), 0x04310000 }, - { _MMIO(0x9888), 0x00310000 }, - { _MMIO(0x9888), 0x00330444 }, - { _MMIO(0x9888), 0x038a0a00 }, - { _MMIO(0x9888), 0x018b0fff }, - { _MMIO(0x9888), 0x038b0a00 }, - { _MMIO(0x9888), 0x01855000 }, - { _MMIO(0x9888), 0x03850055 }, - { _MMIO(0x9888), 0x13830021 }, - { _MMIO(0x9888), 0x15830020 }, - { _MMIO(0x9888), 0x1783002f }, - { _MMIO(0x9888), 0x1983002e }, - { _MMIO(0x9888), 0x1b83002d }, - { _MMIO(0x9888), 0x1d83002c }, - { _MMIO(0x9888), 0x05830000 }, - { _MMIO(0x9888), 0x01840555 }, - { _MMIO(0x9888), 0x03840500 }, - { _MMIO(0x9888), 0x23800074 }, - { _MMIO(0x9888), 0x2580007d }, - { _MMIO(0x9888), 0x05800000 }, - { _MMIO(0x9888), 0x01805000 }, - { _MMIO(0x9888), 0x03800055 }, - { _MMIO(0x9888), 0x01865000 }, - { _MMIO(0x9888), 0x03860055 }, - { _MMIO(0x9888), 0x01875000 }, - { _MMIO(0x9888), 0x03870055 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x4380000a }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x4780000a }, - { _MMIO(0x9888), 0x49800000 }, - { _MMIO(0x9888), 0x4b800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x55800000 }, - { _MMIO(0x9888), 0x57800000 }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x2e5800e0 }, - { _MMIO(0x9888), 0x2e3800e0 }, - { _MMIO(0x9888), 0x3580024f }, - { _MMIO(0x9888), 0x3d800140 }, - { _MMIO(0x9888), 0x08580042 }, - { _MMIO(0x9888), 0x0c580040 }, - { _MMIO(0x9888), 0x1058004c }, - { _MMIO(0x9888), 0x1458004b }, - { _MMIO(0x9888), 0x04580000 }, - { _MMIO(0x9888), 0x00580000 }, - { _MMIO(0x9888), 0x00195555 }, - { _MMIO(0x9888), 0x06380042 }, - { _MMIO(0x9888), 0x0a380040 }, - { _MMIO(0x9888), 0x0e38004c }, - { _MMIO(0x9888), 0x1238004b }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x00384444 }, - { _MMIO(0x9888), 0x003a5555 }, - { _MMIO(0x9888), 0x018bffff }, - { _MMIO(0x9888), 0x01845555 }, - { _MMIO(0x9888), 0x17800074 }, - { _MMIO(0x9888), 0x1980007d }, - { _MMIO(0x9888), 0x1b80007c }, - { _MMIO(0x9888), 0x1d8000b6 }, - { _MMIO(0x9888), 0x1f8000b7 }, - { _MMIO(0x9888), 0x05800000 }, - { _MMIO(0x9888), 0x03800000 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x438000aa }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x4980012a }, - { _MMIO(0x9888), 0x4b80012a }, - { _MMIO(0x9888), 0x4d80012a }, - { _MMIO(0x9888), 0x4f80012a }, - { _MMIO(0x9888), 0x518001ce }, - { _MMIO(0x9888), 0x538001ce }, - { _MMIO(0x9888), 0x5580000e }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x59800000 }, - { _MMIO(0x9888), 0x59800001 }, - { _MMIO(0x9888), 0x261e0000 }, - { _MMIO(0x9888), 0x281f000f }, - { _MMIO(0x9888), 0x2817001a }, - { _MMIO(0x9888), 0x2791001f }, - { _MMIO(0x9888), 0x27880019 }, - { _MMIO(0x9888), 0x2d890000 }, - { _MMIO(0x9888), 0x278a0007 }, - { _MMIO(0x9888), 0x298d001f }, - { _MMIO(0x9888), 0x278e0020 }, - { _MMIO(0x9888), 0x2b8f0012 }, - { _MMIO(0x9888), 0x29900000 }, - { _MMIO(0x9888), 0x00184000 }, - { _MMIO(0x9888), 0x02181000 }, - { _MMIO(0x9888), 0x02194000 }, - { _MMIO(0x9888), 0x141e0002 }, - { _MMIO(0x9888), 0x041e0000 }, - { _MMIO(0x9888), 0x001e0000 }, - { _MMIO(0x9888), 0x221f0015 }, - { _MMIO(0x9888), 0x041f0000 }, - { _MMIO(0x9888), 0x001f4000 }, - { _MMIO(0x9888), 0x021f0000 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0213c000 }, - { _MMIO(0x9888), 0x02164000 }, - { _MMIO(0x9888), 0x24170012 }, - { _MMIO(0x9888), 0x04170000 }, - { _MMIO(0x9888), 0x07910005 }, - { _MMIO(0x9888), 0x05910000 }, - { _MMIO(0x9888), 0x01911500 }, - { _MMIO(0x9888), 0x03910501 }, - { _MMIO(0x9888), 0x0d880002 }, - { _MMIO(0x9888), 0x1d880003 }, - { _MMIO(0x9888), 0x05880000 }, - { _MMIO(0x9888), 0x0b890032 }, - { _MMIO(0x9888), 0x1b890031 }, - { _MMIO(0x9888), 0x05890000 }, - { _MMIO(0x9888), 0x01890040 }, - { _MMIO(0x9888), 0x03890040 }, - { _MMIO(0x9888), 0x098a0000 }, - { _MMIO(0x9888), 0x198a0004 }, - { _MMIO(0x9888), 0x058a0000 }, - { _MMIO(0x9888), 0x018a8050 }, - { _MMIO(0x9888), 0x038a2050 }, - { _MMIO(0x9888), 0x018b95a9 }, - { _MMIO(0x9888), 0x038be5a9 }, - { _MMIO(0x9888), 0x018c1500 }, - { _MMIO(0x9888), 0x038c0501 }, - { _MMIO(0x9888), 0x178d0015 }, - { _MMIO(0x9888), 0x058d0000 }, - { _MMIO(0x9888), 0x138e0004 }, - { _MMIO(0x9888), 0x218e000c }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x018e0500 }, - { _MMIO(0x9888), 0x038e0101 }, - { _MMIO(0x9888), 0x0f8f0027 }, - { _MMIO(0x9888), 0x058f0000 }, - { _MMIO(0x9888), 0x018f0000 }, - { _MMIO(0x9888), 0x038f0001 }, - { _MMIO(0x9888), 0x11900013 }, - { _MMIO(0x9888), 0x1f900017 }, - { _MMIO(0x9888), 0x05900000 }, - { _MMIO(0x9888), 0x01900100 }, - { _MMIO(0x9888), 0x03900001 }, - { _MMIO(0x9888), 0x01845555 }, - { _MMIO(0x9888), 0x03845555 }, - { _MMIO(0x9888), 0x418000aa }, - { _MMIO(0x9888), 0x438000aa }, - { _MMIO(0x9888), 0x458000aa }, - { _MMIO(0x9888), 0x478000aa }, - { _MMIO(0x9888), 0x4980018c }, - { _MMIO(0x9888), 0x4b80014b }, - { _MMIO(0x9888), 0x4d800128 }, - { _MMIO(0x9888), 0x4f80012a }, - { _MMIO(0x9888), 0x51800187 }, - { _MMIO(0x9888), 0x5380014b }, - { _MMIO(0x9888), 0x55800149 }, - { _MMIO(0x9888), 0x5780010a }, - { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fff7 }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x105c0232 }, - { _MMIO(0x9888), 0x10580232 }, - { _MMIO(0x9888), 0x10380232 }, - { _MMIO(0x9888), 0x10dc0232 }, - { _MMIO(0x9888), 0x10d80232 }, - { _MMIO(0x9888), 0x10b80232 }, - { _MMIO(0x9888), 0x118e4400 }, - { _MMIO(0x9888), 0x025c6080 }, - { _MMIO(0x9888), 0x045c004b }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x00582080 }, - { _MMIO(0x9888), 0x0258004b }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x04386080 }, - { _MMIO(0x9888), 0x0638404b }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a380000 }, - { _MMIO(0x9888), 0x0c380000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0cdc25c1 }, - { _MMIO(0x9888), 0x0adcc000 }, - { _MMIO(0x9888), 0x0ad825c1 }, - { _MMIO(0x9888), 0x18db4000 }, - { _MMIO(0x9888), 0x1adb0001 }, - { _MMIO(0x9888), 0x0e9f8000 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb825c1 }, - { _MMIO(0x9888), 0x18b80154 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x0d88c000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baa05 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c5400 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x098dc000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x098e05c0 }, - { _MMIO(0x9888), 0x058e0000 }, - { _MMIO(0x9888), 0x198f0020 }, - { _MMIO(0x9888), 0x2185aa0a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x19835000 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x19808000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x51800040 }, - { _MMIO(0x9888), 0x43800400 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800c62 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801042 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x418014a4 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x10bf03da }, - { _MMIO(0x9888), 0x14bf0001 }, - { _MMIO(0x9888), 0x12980340 }, - { _MMIO(0x9888), 0x12990340 }, - { _MMIO(0x9888), 0x0cbf1187 }, - { _MMIO(0x9888), 0x0ebf1205 }, - { _MMIO(0x9888), 0x00bf0500 }, - { _MMIO(0x9888), 0x02bf042b }, - { _MMIO(0x9888), 0x04bf002c }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x00da8000 }, - { _MMIO(0x9888), 0x02dac000 }, - { _MMIO(0x9888), 0x04da4000 }, - { _MMIO(0x9888), 0x04983400 }, - { _MMIO(0x9888), 0x10980000 }, - { _MMIO(0x9888), 0x06990034 }, - { _MMIO(0x9888), 0x10990000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x009d8000 }, - { _MMIO(0x9888), 0x029dc000 }, - { _MMIO(0x9888), 0x049d4000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00ba }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x00b94000 }, - { _MMIO(0x9888), 0x02b95000 }, - { _MMIO(0x9888), 0x04b91000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0cba4000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x258b800a }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x103f03da }, - { _MMIO(0x9888), 0x143f0001 }, - { _MMIO(0x9888), 0x12180340 }, - { _MMIO(0x9888), 0x12190340 }, - { _MMIO(0x9888), 0x0c3f1187 }, - { _MMIO(0x9888), 0x0e3f1205 }, - { _MMIO(0x9888), 0x003f0500 }, - { _MMIO(0x9888), 0x023f042b }, - { _MMIO(0x9888), 0x043f002c }, - { _MMIO(0x9888), 0x0c5ac000 }, - { _MMIO(0x9888), 0x0e5ac000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x04183400 }, - { _MMIO(0x9888), 0x10180000 }, - { _MMIO(0x9888), 0x06190034 }, - { _MMIO(0x9888), 0x10190000 }, - { _MMIO(0x9888), 0x0c1dc000 }, - { _MMIO(0x9888), 0x0e1dc000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x101f02a8 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00ba }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c395000 }, - { _MMIO(0x9888), 0x0e395000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x0c3a4000 }, - { _MMIO(0x9888), 0x1b8aa800 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258b4005 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800000 }, - { _MMIO(0x9888), 0x47800000 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800060 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x121b0340 }, - { _MMIO(0x9888), 0x103f0274 }, - { _MMIO(0x9888), 0x123f0000 }, - { _MMIO(0x9888), 0x129b0340 }, - { _MMIO(0x9888), 0x10bf0274 }, - { _MMIO(0x9888), 0x12bf0000 }, - { _MMIO(0x9888), 0x041b3400 }, - { _MMIO(0x9888), 0x101b0000 }, - { _MMIO(0x9888), 0x045c8000 }, - { _MMIO(0x9888), 0x0a3d4000 }, - { _MMIO(0x9888), 0x003f0080 }, - { _MMIO(0x9888), 0x023f0793 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f002a }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04399000 }, - { _MMIO(0x9888), 0x069b0034 }, - { _MMIO(0x9888), 0x109b0000 }, - { _MMIO(0x9888), 0x06dc4000 }, - { _MMIO(0x9888), 0x0cbd4000 }, - { _MMIO(0x9888), 0x0cbf0981 }, - { _MMIO(0x9888), 0x0ebf0a0f }, - { _MMIO(0x9888), 0x06d84000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0cdb4000 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0080 }, - { _MMIO(0x9888), 0x0cb84000 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800c00 }, - { _MMIO(0x9888), 0x47800c63 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a5 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800045 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_4[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_4[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_4[] = { - { _MMIO(0x9888), 0x121a0340 }, - { _MMIO(0x9888), 0x103f0017 }, - { _MMIO(0x9888), 0x123f0020 }, - { _MMIO(0x9888), 0x129a0340 }, - { _MMIO(0x9888), 0x10bf0017 }, - { _MMIO(0x9888), 0x12bf0020 }, - { _MMIO(0x9888), 0x041a3400 }, - { _MMIO(0x9888), 0x101a0000 }, - { _MMIO(0x9888), 0x043b8000 }, - { _MMIO(0x9888), 0x0a3e0010 }, - { _MMIO(0x9888), 0x003f0200 }, - { _MMIO(0x9888), 0x023f0113 }, - { _MMIO(0x9888), 0x043f0014 }, - { _MMIO(0x9888), 0x02592000 }, - { _MMIO(0x9888), 0x005a8000 }, - { _MMIO(0x9888), 0x025ac000 }, - { _MMIO(0x9888), 0x045a4000 }, - { _MMIO(0x9888), 0x0a1c8000 }, - { _MMIO(0x9888), 0x001d8000 }, - { _MMIO(0x9888), 0x021dc000 }, - { _MMIO(0x9888), 0x041d4000 }, - { _MMIO(0x9888), 0x0a1e8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f001a }, - { _MMIO(0x9888), 0x00394000 }, - { _MMIO(0x9888), 0x02395000 }, - { _MMIO(0x9888), 0x04391000 }, - { _MMIO(0x9888), 0x069a0034 }, - { _MMIO(0x9888), 0x109a0000 }, - { _MMIO(0x9888), 0x06bb4000 }, - { _MMIO(0x9888), 0x0abe0040 }, - { _MMIO(0x9888), 0x0cbf0984 }, - { _MMIO(0x9888), 0x0ebf0a02 }, - { _MMIO(0x9888), 0x02d94000 }, - { _MMIO(0x9888), 0x0cdac000 }, - { _MMIO(0x9888), 0x0edac000 }, - { _MMIO(0x9888), 0x0c9c0400 }, - { _MMIO(0x9888), 0x0c9dc000 }, - { _MMIO(0x9888), 0x0e9dc000 }, - { _MMIO(0x9888), 0x0c9e0400 }, - { _MMIO(0x9888), 0x109f02a8 }, - { _MMIO(0x9888), 0x0e9f0040 }, - { _MMIO(0x9888), 0x0cb95000 }, - { _MMIO(0x9888), 0x0eb95000 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x258b8009 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x198c4000 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185800a }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x1b830154 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x45800800 }, - { _MMIO(0x9888), 0x47800842 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f801084 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800044 }, -}; - -static int -get_l3_4_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_4; - lens[n] = ARRAY_SIZE(mux_config_l3_4); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00006000 }, - { _MMIO(0x2774), 0x0000f3ff }, - { _MMIO(0x2778), 0x00001800 }, - { _MMIO(0x277c), 0x0000fcff }, - { _MMIO(0x2780), 0x00000600 }, - { _MMIO(0x2784), 0x0000ff3f }, - { _MMIO(0x2788), 0x00000180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000060 }, - { _MMIO(0x2794), 0x0000fff3 }, - { _MMIO(0x2798), 0x00000018 }, - { _MMIO(0x279c), 0x0000fffc }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x143b000e }, - { _MMIO(0x9888), 0x043c55c0 }, - { _MMIO(0x9888), 0x0a1e0280 }, - { _MMIO(0x9888), 0x0c1e0408 }, - { _MMIO(0x9888), 0x10390000 }, - { _MMIO(0x9888), 0x12397a1f }, - { _MMIO(0x9888), 0x14bb000e }, - { _MMIO(0x9888), 0x04bc5000 }, - { _MMIO(0x9888), 0x0a9e0296 }, - { _MMIO(0x9888), 0x0c9e0008 }, - { _MMIO(0x9888), 0x10b90000 }, - { _MMIO(0x9888), 0x12b97a1f }, - { _MMIO(0x9888), 0x063b0042 }, - { _MMIO(0x9888), 0x103b0000 }, - { _MMIO(0x9888), 0x083c0000 }, - { _MMIO(0x9888), 0x0a3e0040 }, - { _MMIO(0x9888), 0x043f8000 }, - { _MMIO(0x9888), 0x02594000 }, - { _MMIO(0x9888), 0x045a8000 }, - { _MMIO(0x9888), 0x0c1c0400 }, - { _MMIO(0x9888), 0x041d8000 }, - { _MMIO(0x9888), 0x081e02c0 }, - { _MMIO(0x9888), 0x0e1e0000 }, - { _MMIO(0x9888), 0x0c1fa800 }, - { _MMIO(0x9888), 0x0e1f0260 }, - { _MMIO(0x9888), 0x101f0014 }, - { _MMIO(0x9888), 0x003905e0 }, - { _MMIO(0x9888), 0x06390bc0 }, - { _MMIO(0x9888), 0x02390018 }, - { _MMIO(0x9888), 0x04394000 }, - { _MMIO(0x9888), 0x04bb0042 }, - { _MMIO(0x9888), 0x10bb0000 }, - { _MMIO(0x9888), 0x02bc05c0 }, - { _MMIO(0x9888), 0x08bc0000 }, - { _MMIO(0x9888), 0x0abe0004 }, - { _MMIO(0x9888), 0x02bf8000 }, - { _MMIO(0x9888), 0x02d91000 }, - { _MMIO(0x9888), 0x02da8000 }, - { _MMIO(0x9888), 0x089c8000 }, - { _MMIO(0x9888), 0x029d8000 }, - { _MMIO(0x9888), 0x089e8000 }, - { _MMIO(0x9888), 0x0e9e0000 }, - { _MMIO(0x9888), 0x0e9fa806 }, - { _MMIO(0x9888), 0x109f0142 }, - { _MMIO(0x9888), 0x08b90617 }, - { _MMIO(0x9888), 0x0ab90be0 }, - { _MMIO(0x9888), 0x02b94000 }, - { _MMIO(0x9888), 0x0d88f000 }, - { _MMIO(0x9888), 0x0f88000c }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x018a8000 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x1b8a2800 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x238b52a0 }, - { _MMIO(0x9888), 0x258b6a95 }, - { _MMIO(0x9888), 0x278b0029 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c1500 }, - { _MMIO(0x9888), 0x1b8c0014 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x038d8000 }, - { _MMIO(0x9888), 0x058d2000 }, - { _MMIO(0x9888), 0x1f85aa80 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x01834000 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0184c000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1180c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4d800444 }, - { _MMIO(0x9888), 0x3d800000 }, - { _MMIO(0x9888), 0x4f804000 }, - { _MMIO(0x9888), 0x43801080 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800084 }, - { _MMIO(0x9888), 0x53800044 }, - { _MMIO(0x9888), 0x47801080 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x3f800000 }, - { _MMIO(0x9888), 0x41800840 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_1[] = { - { _MMIO(0x9888), 0x18921400 }, - { _MMIO(0x9888), 0x149500ab }, - { _MMIO(0x9888), 0x18b21400 }, - { _MMIO(0x9888), 0x14b500ab }, - { _MMIO(0x9888), 0x18d21400 }, - { _MMIO(0x9888), 0x14d500ab }, - { _MMIO(0x9888), 0x0cdc8000 }, - { _MMIO(0x9888), 0x0edc4000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dcc000 }, - { _MMIO(0x9888), 0x1abd00a0 }, - { _MMIO(0x9888), 0x0abd8000 }, - { _MMIO(0x9888), 0x0cd88000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x04d88000 }, - { _MMIO(0x9888), 0x1adb0050 }, - { _MMIO(0x9888), 0x04db8000 }, - { _MMIO(0x9888), 0x06db8000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0adb4000 }, - { _MMIO(0x9888), 0x109f02a0 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x18b82500 }, - { _MMIO(0x9888), 0x02b88000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab84000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x0cb98000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x1aba0200 }, - { _MMIO(0x9888), 0x02ba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04908000 }, - { _MMIO(0x9888), 0x04918000 }, - { _MMIO(0x9888), 0x04927300 }, - { _MMIO(0x9888), 0x10920000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a934000 }, - { _MMIO(0x9888), 0x0a946000 }, - { _MMIO(0x9888), 0x0c959000 }, - { _MMIO(0x9888), 0x0e950098 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x04b04000 }, - { _MMIO(0x9888), 0x04b14000 }, - { _MMIO(0x9888), 0x04b20073 }, - { _MMIO(0x9888), 0x10b20000 }, - { _MMIO(0x9888), 0x04b38000 }, - { _MMIO(0x9888), 0x06b38000 }, - { _MMIO(0x9888), 0x08b34000 }, - { _MMIO(0x9888), 0x04b4c000 }, - { _MMIO(0x9888), 0x02b59890 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x06d04000 }, - { _MMIO(0x9888), 0x06d14000 }, - { _MMIO(0x9888), 0x06d20073 }, - { _MMIO(0x9888), 0x10d20000 }, - { _MMIO(0x9888), 0x18d30020 }, - { _MMIO(0x9888), 0x02d38000 }, - { _MMIO(0x9888), 0x0cd34000 }, - { _MMIO(0x9888), 0x0ad48000 }, - { _MMIO(0x9888), 0x04d42000 }, - { _MMIO(0x9888), 0x0ed59000 }, - { _MMIO(0x9888), 0x00d59800 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0f88000e }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x258b000a }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x0d8d8000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_1; - lens[n] = ARRAY_SIZE(mux_config_sampler_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler_2[] = { - { _MMIO(0x9888), 0x18121400 }, - { _MMIO(0x9888), 0x141500ab }, - { _MMIO(0x9888), 0x18321400 }, - { _MMIO(0x9888), 0x143500ab }, - { _MMIO(0x9888), 0x18521400 }, - { _MMIO(0x9888), 0x145500ab }, - { _MMIO(0x9888), 0x0c5c8000 }, - { _MMIO(0x9888), 0x0e5c4000 }, - { _MMIO(0x9888), 0x025cc000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x1a3d00a0 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0c588000 }, - { _MMIO(0x9888), 0x0e584000 }, - { _MMIO(0x9888), 0x04588000 }, - { _MMIO(0x9888), 0x1a5b0050 }, - { _MMIO(0x9888), 0x045b8000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x101f02a0 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x18382500 }, - { _MMIO(0x9888), 0x02388000 }, - { _MMIO(0x9888), 0x04384000 }, - { _MMIO(0x9888), 0x06384000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c388000 }, - { _MMIO(0x9888), 0x0c398000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x1a3a0200 }, - { _MMIO(0x9888), 0x023a8000 }, - { _MMIO(0x9888), 0x0c3a8000 }, - { _MMIO(0x9888), 0x04108000 }, - { _MMIO(0x9888), 0x04118000 }, - { _MMIO(0x9888), 0x04127300 }, - { _MMIO(0x9888), 0x10120000 }, - { _MMIO(0x9888), 0x1813000a }, - { _MMIO(0x9888), 0x0a134000 }, - { _MMIO(0x9888), 0x0a146000 }, - { _MMIO(0x9888), 0x0c159000 }, - { _MMIO(0x9888), 0x0e150098 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04304000 }, - { _MMIO(0x9888), 0x04314000 }, - { _MMIO(0x9888), 0x04320073 }, - { _MMIO(0x9888), 0x10320000 }, - { _MMIO(0x9888), 0x04338000 }, - { _MMIO(0x9888), 0x06338000 }, - { _MMIO(0x9888), 0x08334000 }, - { _MMIO(0x9888), 0x0434c000 }, - { _MMIO(0x9888), 0x02359890 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x06504000 }, - { _MMIO(0x9888), 0x06514000 }, - { _MMIO(0x9888), 0x06520073 }, - { _MMIO(0x9888), 0x10520000 }, - { _MMIO(0x9888), 0x18530020 }, - { _MMIO(0x9888), 0x02538000 }, - { _MMIO(0x9888), 0x0c534000 }, - { _MMIO(0x9888), 0x0a548000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x0e559000 }, - { _MMIO(0x9888), 0x00559800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x1b8aa000 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x258b0005 }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x2185000a }, - { _MMIO(0x9888), 0x1b830150 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0d848000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x07844000 }, - { _MMIO(0x9888), 0x1d808000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x17804000 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47801021 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800c64 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x41800c02 }, -}; - -static int -get_sampler_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_2; - lens[n] = ARRAY_SIZE(mux_config_sampler_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000ffbf }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fff7 }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fff9 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x16154d60 }, - { _MMIO(0x9888), 0x16352e60 }, - { _MMIO(0x9888), 0x16554d60 }, - { _MMIO(0x9888), 0x16950000 }, - { _MMIO(0x9888), 0x16b50000 }, - { _MMIO(0x9888), 0x16d50000 }, - { _MMIO(0x9888), 0x005c8000 }, - { _MMIO(0x9888), 0x045cc000 }, - { _MMIO(0x9888), 0x065c4000 }, - { _MMIO(0x9888), 0x083d8000 }, - { _MMIO(0x9888), 0x0a3d8000 }, - { _MMIO(0x9888), 0x0458c000 }, - { _MMIO(0x9888), 0x025b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0c1fa000 }, - { _MMIO(0x9888), 0x0e1f00aa }, - { _MMIO(0x9888), 0x02384000 }, - { _MMIO(0x9888), 0x04388000 }, - { _MMIO(0x9888), 0x06388000 }, - { _MMIO(0x9888), 0x08384000 }, - { _MMIO(0x9888), 0x0a384000 }, - { _MMIO(0x9888), 0x0c384000 }, - { _MMIO(0x9888), 0x00398000 }, - { _MMIO(0x9888), 0x0239a000 }, - { _MMIO(0x9888), 0x0439a000 }, - { _MMIO(0x9888), 0x06392000 }, - { _MMIO(0x9888), 0x043a8000 }, - { _MMIO(0x9888), 0x063a8000 }, - { _MMIO(0x9888), 0x08138000 }, - { _MMIO(0x9888), 0x0a138000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x0415cfc7 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x02338000 }, - { _MMIO(0x9888), 0x0c338000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x0035c700 }, - { _MMIO(0x9888), 0x063500cf }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04538000 }, - { _MMIO(0x9888), 0x06538000 }, - { _MMIO(0x9888), 0x0454c000 }, - { _MMIO(0x9888), 0x0255cfc7 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06dc8000 }, - { _MMIO(0x9888), 0x08dc4000 }, - { _MMIO(0x9888), 0x0cdcc000 }, - { _MMIO(0x9888), 0x0edcc000 }, - { _MMIO(0x9888), 0x1abd00a8 }, - { _MMIO(0x9888), 0x0cd8c000 }, - { _MMIO(0x9888), 0x0ed84000 }, - { _MMIO(0x9888), 0x0edb8000 }, - { _MMIO(0x9888), 0x18db0800 }, - { _MMIO(0x9888), 0x1adb0254 }, - { _MMIO(0x9888), 0x0e9faa00 }, - { _MMIO(0x9888), 0x109f02aa }, - { _MMIO(0x9888), 0x0eb84000 }, - { _MMIO(0x9888), 0x16b84000 }, - { _MMIO(0x9888), 0x18b8156a }, - { _MMIO(0x9888), 0x06b98000 }, - { _MMIO(0x9888), 0x08b9a000 }, - { _MMIO(0x9888), 0x0ab9a000 }, - { _MMIO(0x9888), 0x0cb9a000 }, - { _MMIO(0x9888), 0x0eb9a000 }, - { _MMIO(0x9888), 0x18baa000 }, - { _MMIO(0x9888), 0x1aba0002 }, - { _MMIO(0x9888), 0x16934000 }, - { _MMIO(0x9888), 0x1893000a }, - { _MMIO(0x9888), 0x0a947000 }, - { _MMIO(0x9888), 0x0c95c5c1 }, - { _MMIO(0x9888), 0x0e9500c3 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x0eb38000 }, - { _MMIO(0x9888), 0x16b30040 }, - { _MMIO(0x9888), 0x18b30020 }, - { _MMIO(0x9888), 0x06b48000 }, - { _MMIO(0x9888), 0x08b41000 }, - { _MMIO(0x9888), 0x0ab48000 }, - { _MMIO(0x9888), 0x06b5c500 }, - { _MMIO(0x9888), 0x08b500c3 }, - { _MMIO(0x9888), 0x0eb5c100 }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x16d31500 }, - { _MMIO(0x9888), 0x08d4e000 }, - { _MMIO(0x9888), 0x08d5c100 }, - { _MMIO(0x9888), 0x0ad5c3c5 }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x0d88f800 }, - { _MMIO(0x9888), 0x0f88000f }, - { _MMIO(0x9888), 0x038a8000 }, - { _MMIO(0x9888), 0x058a8000 }, - { _MMIO(0x9888), 0x078a8000 }, - { _MMIO(0x9888), 0x098a8000 }, - { _MMIO(0x9888), 0x0b8a8000 }, - { _MMIO(0x9888), 0x0d8a8000 }, - { _MMIO(0x9888), 0x258baaa5 }, - { _MMIO(0x9888), 0x278b002a }, - { _MMIO(0x9888), 0x238b2a80 }, - { _MMIO(0x9888), 0x0f8c4000 }, - { _MMIO(0x9888), 0x178c2000 }, - { _MMIO(0x9888), 0x198c5500 }, - { _MMIO(0x9888), 0x1b8c0015 }, - { _MMIO(0x9888), 0x078d8000 }, - { _MMIO(0x9888), 0x098da000 }, - { _MMIO(0x9888), 0x0b8da000 }, - { _MMIO(0x9888), 0x0d8da000 }, - { _MMIO(0x9888), 0x0f8da000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800c42 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45800063 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x47800800 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f8014a4 }, - { _MMIO(0x9888), 0x41801042 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x0000fe7f }, - { _MMIO(0x2780), 0x00000000 }, - { _MMIO(0x2784), 0x0000ff9f }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000ffe7 }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fffb }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000fffd }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x16150000 }, - { _MMIO(0x9888), 0x16350000 }, - { _MMIO(0x9888), 0x16550000 }, - { _MMIO(0x9888), 0x16952e60 }, - { _MMIO(0x9888), 0x16b54d60 }, - { _MMIO(0x9888), 0x16d52e60 }, - { _MMIO(0x9888), 0x065c8000 }, - { _MMIO(0x9888), 0x085cc000 }, - { _MMIO(0x9888), 0x0a5cc000 }, - { _MMIO(0x9888), 0x0c5c4000 }, - { _MMIO(0x9888), 0x0e3d8000 }, - { _MMIO(0x9888), 0x183da000 }, - { _MMIO(0x9888), 0x06588000 }, - { _MMIO(0x9888), 0x08588000 }, - { _MMIO(0x9888), 0x0a584000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x185b5800 }, - { _MMIO(0x9888), 0x1a5b000a }, - { _MMIO(0x9888), 0x0e1faa00 }, - { _MMIO(0x9888), 0x101f02aa }, - { _MMIO(0x9888), 0x0e384000 }, - { _MMIO(0x9888), 0x16384000 }, - { _MMIO(0x9888), 0x18382a55 }, - { _MMIO(0x9888), 0x06398000 }, - { _MMIO(0x9888), 0x0839a000 }, - { _MMIO(0x9888), 0x0a39a000 }, - { _MMIO(0x9888), 0x0c39a000 }, - { _MMIO(0x9888), 0x0e39a000 }, - { _MMIO(0x9888), 0x1a3a02a0 }, - { _MMIO(0x9888), 0x0e138000 }, - { _MMIO(0x9888), 0x16130500 }, - { _MMIO(0x9888), 0x06148000 }, - { _MMIO(0x9888), 0x08146000 }, - { _MMIO(0x9888), 0x0615c100 }, - { _MMIO(0x9888), 0x0815c500 }, - { _MMIO(0x9888), 0x0a1500c3 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x16335040 }, - { _MMIO(0x9888), 0x08349000 }, - { _MMIO(0x9888), 0x0a341000 }, - { _MMIO(0x9888), 0x083500c1 }, - { _MMIO(0x9888), 0x0a35c500 }, - { _MMIO(0x9888), 0x0c3500c3 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x1853002a }, - { _MMIO(0x9888), 0x0a54e000 }, - { _MMIO(0x9888), 0x0c55c500 }, - { _MMIO(0x9888), 0x0e55c1c3 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x00dc8000 }, - { _MMIO(0x9888), 0x02dcc000 }, - { _MMIO(0x9888), 0x04dc4000 }, - { _MMIO(0x9888), 0x04bd8000 }, - { _MMIO(0x9888), 0x06bd8000 }, - { _MMIO(0x9888), 0x02d8c000 }, - { _MMIO(0x9888), 0x02db8000 }, - { _MMIO(0x9888), 0x04db4000 }, - { _MMIO(0x9888), 0x06db4000 }, - { _MMIO(0x9888), 0x08db8000 }, - { _MMIO(0x9888), 0x0c9fa000 }, - { _MMIO(0x9888), 0x0e9f00aa }, - { _MMIO(0x9888), 0x02b84000 }, - { _MMIO(0x9888), 0x04b84000 }, - { _MMIO(0x9888), 0x06b84000 }, - { _MMIO(0x9888), 0x08b84000 }, - { _MMIO(0x9888), 0x0ab88000 }, - { _MMIO(0x9888), 0x0cb88000 }, - { _MMIO(0x9888), 0x00b98000 }, - { _MMIO(0x9888), 0x02b9a000 }, - { _MMIO(0x9888), 0x04b9a000 }, - { _MMIO(0x9888), 0x06b92000 }, - { _MMIO(0x9888), 0x0aba8000 }, - { _MMIO(0x9888), 0x0cba8000 }, - { _MMIO(0x9888), 0x04938000 }, - { _MMIO(0x9888), 0x06938000 }, - { _MMIO(0x9888), 0x0494c000 }, - { _MMIO(0x9888), 0x0295cfc7 }, - { _MMIO(0x9888), 0x10950000 }, - { _MMIO(0x9888), 0x02b38000 }, - { _MMIO(0x9888), 0x08b38000 }, - { _MMIO(0x9888), 0x04b42000 }, - { _MMIO(0x9888), 0x06b41000 }, - { _MMIO(0x9888), 0x00b5c700 }, - { _MMIO(0x9888), 0x04b500cf }, - { _MMIO(0x9888), 0x10b50000 }, - { _MMIO(0x9888), 0x0ad38000 }, - { _MMIO(0x9888), 0x0cd38000 }, - { _MMIO(0x9888), 0x06d46000 }, - { _MMIO(0x9888), 0x04d5c700 }, - { _MMIO(0x9888), 0x06d500cf }, - { _MMIO(0x9888), 0x10d50000 }, - { _MMIO(0x9888), 0x03888000 }, - { _MMIO(0x9888), 0x05888000 }, - { _MMIO(0x9888), 0x07888000 }, - { _MMIO(0x9888), 0x09888000 }, - { _MMIO(0x9888), 0x0b888000 }, - { _MMIO(0x9888), 0x0d880400 }, - { _MMIO(0x9888), 0x0f8a8000 }, - { _MMIO(0x9888), 0x198a8000 }, - { _MMIO(0x9888), 0x1b8aaaa0 }, - { _MMIO(0x9888), 0x1d8a0002 }, - { _MMIO(0x9888), 0x258b555a }, - { _MMIO(0x9888), 0x278b0015 }, - { _MMIO(0x9888), 0x238b5500 }, - { _MMIO(0x9888), 0x038c4000 }, - { _MMIO(0x9888), 0x058c4000 }, - { _MMIO(0x9888), 0x078c4000 }, - { _MMIO(0x9888), 0x098c4000 }, - { _MMIO(0x9888), 0x0b8c4000 }, - { _MMIO(0x9888), 0x0d8c4000 }, - { _MMIO(0x9888), 0x018d8000 }, - { _MMIO(0x9888), 0x038da000 }, - { _MMIO(0x9888), 0x058da000 }, - { _MMIO(0x9888), 0x078d2000 }, - { _MMIO(0x9888), 0x2185aaaa }, - { _MMIO(0x9888), 0x2385002a }, - { _MMIO(0x9888), 0x1f85aa00 }, - { _MMIO(0x9888), 0x0f834000 }, - { _MMIO(0x9888), 0x19835400 }, - { _MMIO(0x9888), 0x1b830155 }, - { _MMIO(0x9888), 0x03834000 }, - { _MMIO(0x9888), 0x05834000 }, - { _MMIO(0x9888), 0x07834000 }, - { _MMIO(0x9888), 0x09834000 }, - { _MMIO(0x9888), 0x0b834000 }, - { _MMIO(0x9888), 0x0d834000 }, - { _MMIO(0x9888), 0x0784c000 }, - { _MMIO(0x9888), 0x0984c000 }, - { _MMIO(0x9888), 0x0b84c000 }, - { _MMIO(0x9888), 0x0d84c000 }, - { _MMIO(0x9888), 0x0f84c000 }, - { _MMIO(0x9888), 0x01848000 }, - { _MMIO(0x9888), 0x0384c000 }, - { _MMIO(0x9888), 0x0584c000 }, - { _MMIO(0x9888), 0x1780c000 }, - { _MMIO(0x9888), 0x1980c000 }, - { _MMIO(0x9888), 0x1b80c000 }, - { _MMIO(0x9888), 0x1d80c000 }, - { _MMIO(0x9888), 0x1f80c000 }, - { _MMIO(0x9888), 0x11808000 }, - { _MMIO(0x9888), 0x1380c000 }, - { _MMIO(0x9888), 0x1580c000 }, - { _MMIO(0x9888), 0x4f800000 }, - { _MMIO(0x9888), 0x43800882 }, - { _MMIO(0x9888), 0x51800000 }, - { _MMIO(0x9888), 0x45801082 }, - { _MMIO(0x9888), 0x53800000 }, - { _MMIO(0x9888), 0x478014a5 }, - { _MMIO(0x9888), 0x21800000 }, - { _MMIO(0x9888), 0x31800000 }, - { _MMIO(0x9888), 0x4d800000 }, - { _MMIO(0x9888), 0x3f800002 }, - { _MMIO(0x9888), 0x41800c62 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1997,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x000000a0 }, { _MMIO(0x9888), 0x59800000 }, { _MMIO(0x9888), 0x59800001 }, { _MMIO(0x9888), 0x338b0000 }, @@ -2008,866 +72,38 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x57800000 }, { _MMIO(0x1823a4), 0x00000000 }, { _MMIO(0x9888), 0x59800000 }, -}; - -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_L3_4: - dev_priv->perf.oa.n_mux_configs = - get_l3_4_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_4\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_4; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_4); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_4; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_4); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER_1: - dev_priv->perf.oa.n_mux_configs = - get_sampler_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_1); - - return 0; - case METRIC_SET_ID_SAMPLER_2: - dev_priv->perf.oa.n_mux_configs = - get_sampler_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_2); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "f522a89c-ecd1-4522-8331-3383c54af5f5", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "a9ccc03d-a943-4e6b-9cd6-13e063075927", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "78a87ff9-543a-49ce-95ea-26d86071ea93", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); -} - -static struct device_attribute dev_attr_l3_4_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_4_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_4[] = { - &dev_attr_l3_4_id.attr, - NULL, -}; - -static struct attribute_group group_l3_4 = { - .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", - .attrs = attrs_l3_4, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); -} - -static struct device_attribute dev_attr_sampler_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_1_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_1[] = { - &dev_attr_sampler_1_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_1 = { - .name = "71148d78-baf5-474f-878a-e23158d0265d", - .attrs = attrs_sampler_1, -}; - -static ssize_t -show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); -} - -static struct device_attribute dev_attr_sampler_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_2_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler_2[] = { - &dev_attr_sampler_2_id.attr, - NULL, -}; - -static struct attribute_group group_sampler_2 = { - .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84", - .attrs = attrs_sampler_2, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d", - .attrs = attrs_tdl_2, + { _MMIO(0x9840), 0x00000080 }, }; static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "4a534b07-cba3-414d-8d60-874830e883aa", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "4a534b07-cba3-414d-8d60-874830e883aa", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (ret) - goto error_l3_4; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (ret) - goto error_sampler_1; - } - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (ret) - goto error_sampler_2; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); -error_sampler_2: - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); -error_sampler_1: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); -error_l3_4: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_l3_4_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); - if (get_sampler_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_chv.h b/drivers/gpu/drm/i915/i915_oa_chv.h index 8b8bdc26d726..b9622496979e 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.h +++ b/drivers/gpu/drm/i915/i915_oa_chv.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_CHV_H__ #define __I915_OA_CHV_H__ -extern int i915_oa_n_builtin_metric_sets_chv; - -extern int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c b/drivers/gpu/drm/i915/i915_oa_glk.c index 2f356d51bff8..4ee527e4c926 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.c +++ b/drivers/gpu/drm/i915/i915_oa_glk.c @@ -31,1614 +31,6 @@ #include "i915_drv.h" #include "i915_oa_glk.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_glk = 15; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c00f0 }, - { _MMIO(0x9888), 0x12120280 }, - { _MMIO(0x9888), 0x12320280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x419000a0 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2e0800 }, - { _MMIO(0x9888), 0x0e2e5900 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x1c4f0010 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a0fcc00 }, - { _MMIO(0x9888), 0x1c0f0002 }, - { _MMIO(0x9888), 0x1c2c0040 }, - { _MMIO(0x9888), 0x00101000 }, - { _MMIO(0x9888), 0x04101000 }, - { _MMIO(0x9888), 0x00114000 }, - { _MMIO(0x9888), 0x08114000 }, - { _MMIO(0x9888), 0x00120020 }, - { _MMIO(0x9888), 0x08120021 }, - { _MMIO(0x9888), 0x00141000 }, - { _MMIO(0x9888), 0x08141000 }, - { _MMIO(0x9888), 0x02308000 }, - { _MMIO(0x9888), 0x04302000 }, - { _MMIO(0x9888), 0x06318000 }, - { _MMIO(0x9888), 0x08318000 }, - { _MMIO(0x9888), 0x06320800 }, - { _MMIO(0x9888), 0x08320840 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x06344000 }, - { _MMIO(0x9888), 0x08344000 }, - { _MMIO(0x9888), 0x0d931831 }, - { _MMIO(0x9888), 0x0f939f3f }, - { _MMIO(0x9888), 0x01939e80 }, - { _MMIO(0x9888), 0x039303bc }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1993002a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900187 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901110 }, - { _MMIO(0x9888), 0x43900423 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900c02 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900020 }, - { _MMIO(0x9888), 0x59901111 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900821 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d4000 }, - { _MMIO(0x9888), 0x0a2d1000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x0c2e1400 }, - { _MMIO(0x9888), 0x0e2e5100 }, - { _MMIO(0x9888), 0x102e0114 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4c8000 }, - { _MMIO(0x9888), 0x0e4c4000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e2000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004f6b42 }, - { _MMIO(0x9888), 0x064f6200 }, - { _MMIO(0x9888), 0x084f4100 }, - { _MMIO(0x9888), 0x0a4f0061 }, - { _MMIO(0x9888), 0x0c4f6c4c }, - { _MMIO(0x9888), 0x0e4f4b00 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0f8800 }, - { _MMIO(0x9888), 0x1c0f08a2 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c1451 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c0010 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x19938a28 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x19900177 }, - { _MMIO(0x9888), 0x1b900178 }, - { _MMIO(0x9888), 0x1d900125 }, - { _MMIO(0x9888), 0x1f900123 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c2e001f }, - { _MMIO(0x9888), 0x0a2f0000 }, - { _MMIO(0x9888), 0x10186800 }, - { _MMIO(0x9888), 0x11810019 }, - { _MMIO(0x9888), 0x15810013 }, - { _MMIO(0x9888), 0x13820020 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x17840000 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x21860000 }, - { _MMIO(0x9888), 0x178703e0 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x022e5400 }, - { _MMIO(0x9888), 0x002e0000 }, - { _MMIO(0x9888), 0x0e2e0080 }, - { _MMIO(0x9888), 0x082f0040 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x06143000 }, - { _MMIO(0x9888), 0x06174000 }, - { _MMIO(0x9888), 0x06180012 }, - { _MMIO(0x9888), 0x00180000 }, - { _MMIO(0x9888), 0x0d804000 }, - { _MMIO(0x9888), 0x0f804000 }, - { _MMIO(0x9888), 0x05804000 }, - { _MMIO(0x9888), 0x09810200 }, - { _MMIO(0x9888), 0x0b810030 }, - { _MMIO(0x9888), 0x03810003 }, - { _MMIO(0x9888), 0x21819140 }, - { _MMIO(0x9888), 0x23819050 }, - { _MMIO(0x9888), 0x25810018 }, - { _MMIO(0x9888), 0x0b820980 }, - { _MMIO(0x9888), 0x03820d80 }, - { _MMIO(0x9888), 0x11820000 }, - { _MMIO(0x9888), 0x0182c000 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x09824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0d830004 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x0f831000 }, - { _MMIO(0x9888), 0x01848072 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x07848000 }, - { _MMIO(0x9888), 0x09844000 }, - { _MMIO(0x9888), 0x0f848000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x09860092 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x01869100 }, - { _MMIO(0x9888), 0x0f870065 }, - { _MMIO(0x9888), 0x01870000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b952000 }, - { _MMIO(0x9888), 0x1d955055 }, - { _MMIO(0x9888), 0x1f951455 }, - { _MMIO(0x9888), 0x0992a000 }, - { _MMIO(0x9888), 0x0f928000 }, - { _MMIO(0x9888), 0x1192a800 }, - { _MMIO(0x9888), 0x1392028a }, - { _MMIO(0x9888), 0x0b92a000 }, - { _MMIO(0x9888), 0x0d922000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c01 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900863 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900c22 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x41900003 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900170 }, - { _MMIO(0x9888), 0x21900171 }, - { _MMIO(0x9888), 0x23900172 }, - { _MMIO(0x9888), 0x25900173 }, - { _MMIO(0x9888), 0x27900174 }, - { _MMIO(0x9888), 0x29900175 }, - { _MMIO(0x9888), 0x2b900176 }, - { _MMIO(0x9888), 0x2d900177 }, - { _MMIO(0x9888), 0x2f90017f }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x19800343 }, - { _MMIO(0x9888), 0x39900340 }, - { _MMIO(0x9888), 0x3f900000 }, - { _MMIO(0x9888), 0x41900080 }, - { _MMIO(0x9888), 0x03803180 }, - { _MMIO(0x9888), 0x058035e2 }, - { _MMIO(0x9888), 0x0780006a }, - { _MMIO(0x9888), 0x11800000 }, - { _MMIO(0x9888), 0x2181a000 }, - { _MMIO(0x9888), 0x2381000a }, - { _MMIO(0x9888), 0x1d950550 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d92a000 }, - { _MMIO(0x9888), 0x0f922000 }, - { _MMIO(0x9888), 0x13900180 }, - { _MMIO(0x9888), 0x21900181 }, - { _MMIO(0x9888), 0x23900182 }, - { _MMIO(0x9888), 0x25900183 }, - { _MMIO(0x9888), 0x27900184 }, - { _MMIO(0x9888), 0x29900185 }, - { _MMIO(0x9888), 0x2b900186 }, - { _MMIO(0x9888), 0x2d900187 }, - { _MMIO(0x9888), 0x2f900170 }, - { _MMIO(0x9888), 0x31900125 }, - { _MMIO(0x9888), 0x15900123 }, - { _MMIO(0x9888), 0x17900121 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47901080 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49901084 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b901084 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900004 }, - { _MMIO(0x9888), 0x45900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x141c0160 }, - { _MMIO(0x9888), 0x161c0015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x002d5000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0a2d5000 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x0c2e5400 }, - { _MMIO(0x9888), 0x0e2e5515 }, - { _MMIO(0x9888), 0x102e0155 }, - { _MMIO(0x9888), 0x044cc000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x0e4cc000 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x004ea000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0a4ea000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x0e4f4b41 }, - { _MMIO(0x9888), 0x004f4200 }, - { _MMIO(0x9888), 0x024f404c }, - { _MMIO(0x9888), 0x1c4f0000 }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0a1bc000 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x001c0031 }, - { _MMIO(0x9888), 0x061c1900 }, - { _MMIO(0x9888), 0x081c1a33 }, - { _MMIO(0x9888), 0x0a1c1b35 }, - { _MMIO(0x9888), 0x0c1c3337 }, - { _MMIO(0x9888), 0x041c31c7 }, - { _MMIO(0x9888), 0x180f5000 }, - { _MMIO(0x9888), 0x1a0fa8aa }, - { _MMIO(0x9888), 0x1c0f0aaa }, - { _MMIO(0x9888), 0x182c8000 }, - { _MMIO(0x9888), 0x1c2c6aaa }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c2950 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993aaaa }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29904000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900400 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x45900001 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c03b0 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900c00 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x002d1000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x082d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x0c2e0400 }, - { _MMIO(0x9888), 0x0e2e1500 }, - { _MMIO(0x9888), 0x102e0140 }, - { _MMIO(0x9888), 0x044c4000 }, - { _MMIO(0x9888), 0x0a4c8000 }, - { _MMIO(0x9888), 0x0c4cc000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x004e2000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x1a4f4001 }, - { _MMIO(0x9888), 0x1c4f5005 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x180f1000 }, - { _MMIO(0x9888), 0x1a0fa800 }, - { _MMIO(0x9888), 0x1c0f0a00 }, - { _MMIO(0x9888), 0x182c4000 }, - { _MMIO(0x9888), 0x1c2c4015 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x03931980 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x01938000 }, - { _MMIO(0x9888), 0x0f938000 }, - { _MMIO(0x9888), 0x1993a00a }, - { _MMIO(0x9888), 0x07930000 }, - { _MMIO(0x9888), 0x09930000 }, - { _MMIO(0x9888), 0x1d900177 }, - { _MMIO(0x9888), 0x1f900178 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x53901000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x45900400 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x022d4000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x064c8000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x024f6100 }, - { _MMIO(0x9888), 0x044f416b }, - { _MMIO(0x9888), 0x064f004b }, - { _MMIO(0x9888), 0x1a4f0000 }, - { _MMIO(0x9888), 0x1a0f02a8 }, - { _MMIO(0x9888), 0x1a2c5500 }, - { _MMIO(0x9888), 0x0f808000 }, - { _MMIO(0x9888), 0x25810020 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1f951000 }, - { _MMIO(0x9888), 0x13920200 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4d900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x12643400 }, - { _MMIO(0x9888), 0x12653400 }, - { _MMIO(0x9888), 0x106c6800 }, - { _MMIO(0x9888), 0x126c001e }, - { _MMIO(0x9888), 0x166c0010 }, - { _MMIO(0x9888), 0x0c2d5000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0154 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0055 }, - { _MMIO(0x9888), 0x104c8000 }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4ea000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c4f5500 }, - { _MMIO(0x9888), 0x1a4f1554 }, - { _MMIO(0x9888), 0x0a640024 }, - { _MMIO(0x9888), 0x10640000 }, - { _MMIO(0x9888), 0x04640000 }, - { _MMIO(0x9888), 0x0c650024 }, - { _MMIO(0x9888), 0x10650000 }, - { _MMIO(0x9888), 0x06650000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0900 }, - { _MMIO(0x9888), 0x1c0f0aa0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f02aa }, - { _MMIO(0x9888), 0x1c2c5400 }, - { _MMIO(0x9888), 0x1e2c0001 }, - { _MMIO(0x9888), 0x1a2c5550 }, - { _MMIO(0x9888), 0x1993aa00 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900421 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900420 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102d7800 }, - { _MMIO(0x9888), 0x122d79e0 }, - { _MMIO(0x9888), 0x0c2f0004 }, - { _MMIO(0x9888), 0x100e3800 }, - { _MMIO(0x9888), 0x180f0005 }, - { _MMIO(0x9888), 0x002d0940 }, - { _MMIO(0x9888), 0x022d802f }, - { _MMIO(0x9888), 0x042d4013 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0050 }, - { _MMIO(0x9888), 0x022f0010 }, - { _MMIO(0x9888), 0x002f0000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x040e0480 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x060f0027 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x1a0f0040 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x439014a0 }, - { _MMIO(0x9888), 0x459000a4 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x121300a0 }, - { _MMIO(0x9888), 0x141600ab }, - { _MMIO(0x9888), 0x123300a0 }, - { _MMIO(0x9888), 0x143600ab }, - { _MMIO(0x9888), 0x125300a0 }, - { _MMIO(0x9888), 0x145600ab }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e01a0 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0065 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x084c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x044e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0800 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f023f }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2cc030 }, - { _MMIO(0x9888), 0x04132180 }, - { _MMIO(0x9888), 0x02130000 }, - { _MMIO(0x9888), 0x0c148000 }, - { _MMIO(0x9888), 0x0e142000 }, - { _MMIO(0x9888), 0x04148000 }, - { _MMIO(0x9888), 0x1e150140 }, - { _MMIO(0x9888), 0x1c150040 }, - { _MMIO(0x9888), 0x0c163000 }, - { _MMIO(0x9888), 0x0e160068 }, - { _MMIO(0x9888), 0x10160000 }, - { _MMIO(0x9888), 0x18160000 }, - { _MMIO(0x9888), 0x0a164000 }, - { _MMIO(0x9888), 0x04330043 }, - { _MMIO(0x9888), 0x02330000 }, - { _MMIO(0x9888), 0x0234a000 }, - { _MMIO(0x9888), 0x04342000 }, - { _MMIO(0x9888), 0x1c350015 }, - { _MMIO(0x9888), 0x02363460 }, - { _MMIO(0x9888), 0x10360000 }, - { _MMIO(0x9888), 0x04360000 }, - { _MMIO(0x9888), 0x06360000 }, - { _MMIO(0x9888), 0x08364000 }, - { _MMIO(0x9888), 0x06530043 }, - { _MMIO(0x9888), 0x02530000 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x06542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550100 }, - { _MMIO(0x9888), 0x0e563000 }, - { _MMIO(0x9888), 0x00563400 }, - { _MMIO(0x9888), 0x10560000 }, - { _MMIO(0x9888), 0x18560000 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x0c564000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9014a0 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900001 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900820 }, - { _MMIO(0x9888), 0x45901022 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900000 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x141a0000 }, - { _MMIO(0x9888), 0x143a0000 }, - { _MMIO(0x9888), 0x145a0000 }, - { _MMIO(0x9888), 0x0c2d4000 }, - { _MMIO(0x9888), 0x0e2d5000 }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x102e0150 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e006a }, - { _MMIO(0x9888), 0x124c8000 }, - { _MMIO(0x9888), 0x144c8000 }, - { _MMIO(0x9888), 0x164c2000 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064c4000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x0e4ea000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024e2000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x1c0f0bc0 }, - { _MMIO(0x9888), 0x180f4000 }, - { _MMIO(0x9888), 0x1a0f0302 }, - { _MMIO(0x9888), 0x1e2c0003 }, - { _MMIO(0x9888), 0x1a2c00f0 }, - { _MMIO(0x9888), 0x021a3080 }, - { _MMIO(0x9888), 0x041a31e5 }, - { _MMIO(0x9888), 0x02148000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150054 }, - { _MMIO(0x9888), 0x06168000 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x0c3a3280 }, - { _MMIO(0x9888), 0x0e3a0063 }, - { _MMIO(0x9888), 0x063a0061 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x0c348000 }, - { _MMIO(0x9888), 0x0e342000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1e350140 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x18360028 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x0e5a3080 }, - { _MMIO(0x9888), 0x005a3280 }, - { _MMIO(0x9888), 0x025a0063 }, - { _MMIO(0x9888), 0x0e548000 }, - { _MMIO(0x9888), 0x00548000 }, - { _MMIO(0x9888), 0x02542000 }, - { _MMIO(0x9888), 0x1e550400 }, - { _MMIO(0x9888), 0x1a552000 }, - { _MMIO(0x9888), 0x1c550001 }, - { _MMIO(0x9888), 0x18560080 }, - { _MMIO(0x9888), 0x02568000 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x1993a800 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x2d904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4d900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x45901084 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x141a026b }, - { _MMIO(0x9888), 0x143a0173 }, - { _MMIO(0x9888), 0x145a026b }, - { _MMIO(0x9888), 0x002d4000 }, - { _MMIO(0x9888), 0x022d5000 }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0c2e5000 }, - { _MMIO(0x9888), 0x0e2e0069 }, - { _MMIO(0x9888), 0x044c8000 }, - { _MMIO(0x9888), 0x064cc000 }, - { _MMIO(0x9888), 0x0a4c4000 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x024ea000 }, - { _MMIO(0x9888), 0x064e2000 }, - { _MMIO(0x9888), 0x180f6000 }, - { _MMIO(0x9888), 0x1a0f030a }, - { _MMIO(0x9888), 0x1a2c03c0 }, - { _MMIO(0x9888), 0x041a37e7 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x0414a000 }, - { _MMIO(0x9888), 0x1c150050 }, - { _MMIO(0x9888), 0x08168000 }, - { _MMIO(0x9888), 0x0a168000 }, - { _MMIO(0x9888), 0x003a3380 }, - { _MMIO(0x9888), 0x063a006f }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x00348000 }, - { _MMIO(0x9888), 0x06342000 }, - { _MMIO(0x9888), 0x1a352000 }, - { _MMIO(0x9888), 0x1c350100 }, - { _MMIO(0x9888), 0x02368000 }, - { _MMIO(0x9888), 0x0c368000 }, - { _MMIO(0x9888), 0x025a37e7 }, - { _MMIO(0x9888), 0x0254a000 }, - { _MMIO(0x9888), 0x1c550005 }, - { _MMIO(0x9888), 0x04568000 }, - { _MMIO(0x9888), 0x06568000 }, - { _MMIO(0x9888), 0x03938000 }, - { _MMIO(0x9888), 0x05938000 }, - { _MMIO(0x9888), 0x07938000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17904000 }, - { _MMIO(0x9888), 0x19904000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900020 }, - { _MMIO(0x9888), 0x45901080 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x47900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x141a001f }, - { _MMIO(0x9888), 0x143a001f }, - { _MMIO(0x9888), 0x145a001f }, - { _MMIO(0x9888), 0x042d5000 }, - { _MMIO(0x9888), 0x062d1000 }, - { _MMIO(0x9888), 0x0e2e0094 }, - { _MMIO(0x9888), 0x084cc000 }, - { _MMIO(0x9888), 0x044ea000 }, - { _MMIO(0x9888), 0x1a0f00e0 }, - { _MMIO(0x9888), 0x1a2c0c00 }, - { _MMIO(0x9888), 0x061a0063 }, - { _MMIO(0x9888), 0x021a0000 }, - { _MMIO(0x9888), 0x06142000 }, - { _MMIO(0x9888), 0x1c150100 }, - { _MMIO(0x9888), 0x0c168000 }, - { _MMIO(0x9888), 0x043a3180 }, - { _MMIO(0x9888), 0x023a0000 }, - { _MMIO(0x9888), 0x04348000 }, - { _MMIO(0x9888), 0x1c350040 }, - { _MMIO(0x9888), 0x0a368000 }, - { _MMIO(0x9888), 0x045a0063 }, - { _MMIO(0x9888), 0x025a0000 }, - { _MMIO(0x9888), 0x04542000 }, - { _MMIO(0x9888), 0x1c550010 }, - { _MMIO(0x9888), 0x08568000 }, - { _MMIO(0x9888), 0x09938000 }, - { _MMIO(0x9888), 0x0b938000 }, - { _MMIO(0x9888), 0x0d938000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1d904000 }, - { _MMIO(0x9888), 0x1f904000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900004 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1668,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x19800000 }, { _MMIO(0x9888), 0x07800063 }, { _MMIO(0x9888), 0x11800000 }, @@ -1681,922 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "814285f6-354d-41d2-ba49-e24e622714a0", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "07d397a6-b3e6-49f6-9433-a4f293d55978", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "1a356946-5428-450b-a2f0-89f8783a302d", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "bc9bcff2-459a-4cbc-986d-a84b077153f3", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "88ec931f-5b4a-453a-9db6-a61232b6143d", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "530d176d-2a18-4014-adf8-1500c6c60835", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "fdee5a5a-f23c-43d1-aa73-f6257c71671d", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "6617623e-ca73-4791-b2b7-ddedd0846a0c", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "f3b2ea63-e82e-4234-b418-44dd20dd34d0", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "14411d35-cbf6-4f5e-b68b-190faf9a1a83", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "15274c82-27d2-4819-876a-7cb1a2c59ba4", - .attrs = attrs_compute_extra, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "dd3fd789-e783-4204-8cd0-b671bbccb0cf", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_glk.h b/drivers/gpu/drm/i915/i915_oa_glk.h index 5511bb1cecf7..63bd113f4bc9 100644 --- a/drivers/gpu/drm/i915/i915_oa_glk.h +++ b/drivers/gpu/drm/i915/i915_oa_glk.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_GLK_H__ #define __I915_OA_GLK_H__ -extern int i915_oa_n_builtin_metric_sets_glk; - -extern int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c index 10f169f683b7..56b03773bb9d 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.c +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -31,17 +31,6 @@ #include "i915_drv.h" #include "i915_oa_hsw.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_SAMPLER_BALANCE, -}; - -int i915_oa_n_builtin_metric_sets_hsw = 6; - static const struct i915_oa_reg b_counter_config_render_basic[] = { { _MMIO(0x2724), 0x00800000 }, { _MMIO(0x2720), 0x00000000 }, @@ -53,6 +42,7 @@ static const struct i915_oa_reg flex_eu_config_render_basic[] = { }; static const struct i915_oa_reg mux_config_render_basic[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x253a4), 0x01600000 }, { _MMIO(0x25440), 0x00100000 }, { _MMIO(0x25128), 0x00000000 }, @@ -114,750 +104,35 @@ static const struct i915_oa_reg mux_config_render_basic[] = { { _MMIO(0x25428), 0x00042049 }, }; -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2718), 0xaaaaaaaa }, - { _MMIO(0x271c), 0xaaaaaaaa }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2728), 0xaaaaaaaa }, - { _MMIO(0x272c), 0xaaaaaaaa }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00000000 }, - { _MMIO(0x2748), 0x00000000 }, - { _MMIO(0x274c), 0x00000000 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2754), 0x00000000 }, - { _MMIO(0x2758), 0x00000000 }, - { _MMIO(0x275c), 0x00000000 }, - { _MMIO(0x236c), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x253a4), 0x00000000 }, - { _MMIO(0x2681c), 0x01f00800 }, - { _MMIO(0x26820), 0x00001000 }, - { _MMIO(0x2781c), 0x01f00800 }, - { _MMIO(0x26520), 0x00000007 }, - { _MMIO(0x265a0), 0x00000007 }, - { _MMIO(0x25380), 0x00000010 }, - { _MMIO(0x2538c), 0x00300000 }, - { _MMIO(0x25384), 0xaa8aaaaa }, - { _MMIO(0x25404), 0xffffffff }, - { _MMIO(0x26800), 0x00004202 }, - { _MMIO(0x26808), 0x00605817 }, - { _MMIO(0x2680c), 0x10001005 }, - { _MMIO(0x26804), 0x00000000 }, - { _MMIO(0x27800), 0x00000102 }, - { _MMIO(0x27808), 0x0c0701e0 }, - { _MMIO(0x2780c), 0x000200a0 }, - { _MMIO(0x27804), 0x00000000 }, - { _MMIO(0x26484), 0x44000000 }, - { _MMIO(0x26704), 0x44000000 }, - { _MMIO(0x26500), 0x00000006 }, - { _MMIO(0x26510), 0x00000001 }, - { _MMIO(0x26504), 0x88000000 }, - { _MMIO(0x26580), 0x00000006 }, - { _MMIO(0x26590), 0x00000020 }, - { _MMIO(0x26584), 0x00000000 }, - { _MMIO(0x26104), 0x55822222 }, - { _MMIO(0x26184), 0xaa866666 }, - { _MMIO(0x25420), 0x08320c83 }, - { _MMIO(0x25424), 0x06820c83 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000c03 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2770), 0x0007fe2a }, - { _MMIO(0x2774), 0x0000ff00 }, - { _MMIO(0x2778), 0x0007fe6a }, - { _MMIO(0x277c), 0x0000ff00 }, - { _MMIO(0x2780), 0x0007fe92 }, - { _MMIO(0x2784), 0x0000ff00 }, - { _MMIO(0x2788), 0x0007fea2 }, - { _MMIO(0x278c), 0x0000ff00 }, - { _MMIO(0x2790), 0x0007fe32 }, - { _MMIO(0x2794), 0x0000ff00 }, - { _MMIO(0x2798), 0x0007fe9a }, - { _MMIO(0x279c), 0x0000ff00 }, - { _MMIO(0x27a0), 0x0007ff23 }, - { _MMIO(0x27a4), 0x0000ff00 }, - { _MMIO(0x27a8), 0x0007fff3 }, - { _MMIO(0x27ac), 0x0000fffe }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x2681c), 0x3eb00800 }, - { _MMIO(0x26820), 0x00900000 }, - { _MMIO(0x25384), 0x02aaaaaa }, - { _MMIO(0x25404), 0x03ffffff }, - { _MMIO(0x26800), 0x00142284 }, - { _MMIO(0x26808), 0x0e629062 }, - { _MMIO(0x2680c), 0x3f6f55cb }, - { _MMIO(0x26810), 0x00000014 }, - { _MMIO(0x26804), 0x00000000 }, - { _MMIO(0x26104), 0x02aaaaaa }, - { _MMIO(0x26184), 0x02aaaaaa }, - { _MMIO(0x25420), 0x00000000 }, - { _MMIO(0x25424), 0x00000000 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x76543298 }, - { _MMIO(0x2748), 0x98989898 }, - { _MMIO(0x2744), 0x000000e4 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x98a98a98 }, - { _MMIO(0x2758), 0x88888888 }, - { _MMIO(0x2754), 0x000c5500 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fc00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fc00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fc00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fc00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fc00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fc00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fc00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fc00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x253a4), 0x34300000 }, - { _MMIO(0x25440), 0x2d800000 }, - { _MMIO(0x25444), 0x00000008 }, - { _MMIO(0x25128), 0x0e600000 }, - { _MMIO(0x25380), 0x00000450 }, - { _MMIO(0x25390), 0x00052c43 }, - { _MMIO(0x25384), 0x00000000 }, - { _MMIO(0x25400), 0x00006144 }, - { _MMIO(0x25408), 0x0a418820 }, - { _MMIO(0x2540c), 0x000820e6 }, - { _MMIO(0x25404), 0xff500000 }, - { _MMIO(0x25100), 0x000005d6 }, - { _MMIO(0x2510c), 0x0ef00000 }, - { _MMIO(0x25104), 0x00000000 }, - { _MMIO(0x25420), 0x02108421 }, - { _MMIO(0x25424), 0x00008421 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x76543298 }, - { _MMIO(0x2748), 0x98989898 }, - { _MMIO(0x2744), 0x000000e4 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0xbabababa }, - { _MMIO(0x2758), 0x88888888 }, - { _MMIO(0x2754), 0x000c5500 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fc00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fc00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fc00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fc00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fc00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fc00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fc00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fc00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x253a4), 0x34300000 }, - { _MMIO(0x25440), 0x01500000 }, - { _MMIO(0x25444), 0x00000120 }, - { _MMIO(0x25128), 0x0c200000 }, - { _MMIO(0x25380), 0x00000450 }, - { _MMIO(0x25390), 0x00052c43 }, - { _MMIO(0x25384), 0x00000000 }, - { _MMIO(0x25400), 0x00007184 }, - { _MMIO(0x25408), 0x0a418820 }, - { _MMIO(0x2540c), 0x000820e6 }, - { _MMIO(0x25404), 0xff500000 }, - { _MMIO(0x25100), 0x000005d6 }, - { _MMIO(0x2510c), 0x1e700000 }, - { _MMIO(0x25104), 0x00000000 }, - { _MMIO(0x25420), 0x02108421 }, - { _MMIO(0x25424), 0x00008421 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x00000000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler_balance[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler_balance[] = { -}; - -static const struct i915_oa_reg mux_config_sampler_balance[] = { - { _MMIO(0x2eb9c), 0x01906400 }, - { _MMIO(0x2fb9c), 0x01906400 }, - { _MMIO(0x253a4), 0x00000000 }, - { _MMIO(0x26b9c), 0x01906400 }, - { _MMIO(0x27b9c), 0x01906400 }, - { _MMIO(0x27104), 0x00a00000 }, - { _MMIO(0x27184), 0x00a50000 }, - { _MMIO(0x2e804), 0x00500000 }, - { _MMIO(0x2e984), 0x00500000 }, - { _MMIO(0x2eb04), 0x00500000 }, - { _MMIO(0x2eb80), 0x00000084 }, - { _MMIO(0x2eb8c), 0x14200000 }, - { _MMIO(0x2eb84), 0x00000000 }, - { _MMIO(0x2f804), 0x00050000 }, - { _MMIO(0x2f984), 0x00050000 }, - { _MMIO(0x2fb04), 0x00050000 }, - { _MMIO(0x2fb80), 0x00000084 }, - { _MMIO(0x2fb8c), 0x00050800 }, - { _MMIO(0x2fb84), 0x00000000 }, - { _MMIO(0x25380), 0x00000010 }, - { _MMIO(0x2538c), 0x000000c0 }, - { _MMIO(0x25384), 0xaa550000 }, - { _MMIO(0x25404), 0xffffc000 }, - { _MMIO(0x26804), 0x50000000 }, - { _MMIO(0x26984), 0x50000000 }, - { _MMIO(0x26b04), 0x50000000 }, - { _MMIO(0x26b80), 0x00000084 }, - { _MMIO(0x26b90), 0x00050800 }, - { _MMIO(0x26b84), 0x00000000 }, - { _MMIO(0x27804), 0x05000000 }, - { _MMIO(0x27984), 0x05000000 }, - { _MMIO(0x27b04), 0x05000000 }, - { _MMIO(0x27b80), 0x00000084 }, - { _MMIO(0x27b90), 0x00000142 }, - { _MMIO(0x27b84), 0x00000000 }, - { _MMIO(0x26104), 0xa0000000 }, - { _MMIO(0x26184), 0xa5000000 }, - { _MMIO(0x25424), 0x00008620 }, - { _MMIO(0x2541c), 0x00000000 }, - { _MMIO(0x25428), 0x0004a54a }, -}; - -static int -get_sampler_balance_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler_balance; - lens[n] = ARRAY_SIZE(mux_config_sampler_balance); - n++; - - return n; -} - -int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_SAMPLER_BALANCE: - dev_priv->perf.oa.n_mux_configs = - get_sampler_balance_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER_BALANCE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler_balance; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler_balance); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler_balance; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler_balance); - - return 0; - default: - return -ENODEV; - } -} - static ssize_t show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "403d8832-1a27-4aa6-a64e-f5389ce7b212", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "3865be28-6982-49fe-9494-e4d1b4795413", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "bb5ed49b-2497-4095-94f6-26ba294db88a", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "3358d639-9b5f-45ab-976d-9b08cbfc6240", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf) +void +i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv) { - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE); -} - -static struct device_attribute dev_attr_sampler_balance_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_balance_id, - .store = NULL, -}; + strncpy(dev_priv->perf.oa.test_config.uuid, + "403d8832-1a27-4aa6-a64e-f5389ce7b212", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; -static struct attribute *attrs_sampler_balance[] = { - &dev_attr_sampler_balance_id.attr, - NULL, -}; + dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic); -static struct attribute_group group_sampler_balance = { - .name = "bc274488-b4b6-40c7-90da-b77d7ad16189", - .attrs = attrs_sampler_balance, -}; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic); -int -i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic); - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); - if (ret) - goto error_sampler_balance; - } + dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; - return 0; - -error_sampler_balance: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} - -void -i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_sampler_balance_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.h b/drivers/gpu/drm/i915/i915_oa_hsw.h index 6fe7e0690ef3..74d03439c157 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.h +++ b/drivers/gpu/drm/i915/i915_oa_hsw.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_HSW_H__ #define __I915_OA_HSW_H__ -extern int i915_oa_n_builtin_metric_sets_hsw; - -extern int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_hsw(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_hsw(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c b/drivers/gpu/drm/i915/i915_oa_kblgt2.c index 87dbd0a0b076..b6e7cc774136 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c @@ -31,1828 +31,6 @@ #include "i915_drv.h" #include "i915_oa_kblgt2.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_kblgt2 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0080 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0d2000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162c2200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190001f }, - { _MMIO(0x9888), 0x51904400 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c21 }, - { _MMIO(0x9888), 0x47900061 }, - { _MMIO(0x9888), 0x57904440 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900004 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57900400 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53904444 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0e0f006c }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1190e000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c00 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x143a5800 }, - { _MMIO(0x9888), 0x163a00c0 }, - { _MMIO(0x9888), 0x12380240 }, - { _MMIO(0x9888), 0x14380002 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c1500 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f9500 }, - { _MMIO(0x9888), 0x100f002a }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x0a2dc000 }, - { _MMIO(0x9888), 0x0c2dc000 }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x06393000 }, - { _MMIO(0x9888), 0x0c3a28c1 }, - { _MMIO(0x9888), 0x003a0000 }, - { _MMIO(0x9888), 0x0a33f000 }, - { _MMIO(0x9888), 0x0c33f000 }, - { _MMIO(0x9888), 0x0a37a000 }, - { _MMIO(0x9888), 0x0c37a000 }, - { _MMIO(0x9888), 0x0a380977 }, - { _MMIO(0x9888), 0x08380000 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06383000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900800 }, - { _MMIO(0x9888), 0x47901000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900844 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1882,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1896,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "f8d677e9-ff6f-4df1-9310-0334c6efacce", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "e17fc42a-e614-41b6-90c4-1074841a6c77", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "d7a17a3a-ca71-40d2-a919-ace80d50633f", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "57b59202-172b-477a-87de-33f85572c589", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "4af0400a-81c3-47db-a6b6-deddbd75680e", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "0e22f995-79ca-4f67-83ab-e9d9772488d8", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "2f8e32e4-5956-46e2-af31-c8ea95887332", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "ca046aad-b5fb-4101-adce-6473ee6e5b14", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "105db928-5542-466b-9128-e1f3c91426cb", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "03db94d2-b37f-4c58-a791-0d2067b013bb", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "baa3c7e4-52b6-4b85-801e-465a94b746dd", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "baa3c7e4-52b6-4b85-801e-465a94b746dd", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.h b/drivers/gpu/drm/i915/i915_oa_kblgt2.h index 7e61bfc4f9f5..25b803546dc1 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt2.h +++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_KBLGT2_H__ #define __I915_OA_KBLGT2_H__ -extern int i915_oa_n_builtin_metric_sets_kblgt2; - -extern int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c b/drivers/gpu/drm/i915/i915_oa_kblgt3.c index 6ed092566a32..5576afdd9a7e 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c @@ -31,1877 +31,6 @@ #include "i915_drv.h" #include "i915_oa_kblgt3.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_kblgt3 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0380 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162ca200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0200 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x51902240 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900242 }, - { _MMIO(0x9888), 0x45900084 }, - { _MMIO(0x9888), 0x47901400 }, - { _MMIO(0x9888), 0x57902220 }, - { _MMIO(0x9888), 0x49900c60 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900002 }, - { _MMIO(0x9888), 0x43900c63 }, - { _MMIO(0x9888), 0x53902222 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57900400 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53904444 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900002 }, - { _MMIO(0x9888), 0x53900420 }, - { _MMIO(0x9888), 0x459000a1 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900040 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900004 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x479008a5 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1931,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1945,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "0286c920-2f6d-493b-b22d-7a5280df43de", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "9823aaa1-b06f-40ce-884b-cd798c79f0c2", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "c7c735f3-ce58-45cf-aa04-30b183f1faff", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "96ec2219-040b-428a-856a-6bc03363a057", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "03372b64-4996-4d3b-aa18-790e75eeb9c2", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "2ce0911a-27fc-4887-96f0-11084fa807c3", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "546c4c1d-99b8-42fb-a107-5aaabb5314a8", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "4e93d156-9b39-4268-8544-a8e0480806d7", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "de1bec86-ca92-4b43-89fa-147653221cc0", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "469a05e5-e299-46f7-9598-7b05f3c34991", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "52f925c6-786a-4ec6-86ce-cba85c83453a", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "efc497ac-884e-4ee4-a4a8-15fba22aaf21", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "f1792f32-6db2-4b50-b4b2-557128f1688d", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "f1792f32-6db2-4b50-b4b2-557128f1688d", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.h b/drivers/gpu/drm/i915/i915_oa_kblgt3.h index b0ca7f3114d3..d5b5b5c1923e 100644 --- a/drivers/gpu/drm/i915/i915_oa_kblgt3.h +++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_KBLGT3_H__ #define __I915_OA_KBLGT3_H__ -extern int i915_oa_n_builtin_metric_sets_kblgt3; - -extern int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.c b/drivers/gpu/drm/i915/i915_oa_sklgt2.c index 1268beda212c..890d55879946 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.c @@ -31,2317 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt2.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt2 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic_1_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0080 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0d2000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162c2200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190001f }, - { _MMIO(0x9888), 0x51904400 }, - { _MMIO(0x9888), 0x41900020 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c21 }, - { _MMIO(0x9888), 0x47900061 }, - { _MMIO(0x9888), 0x57904440 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900004 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53904444 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (dev_priv->drm.pdev->revision >= 0x02) { - regs[n] = mux_config_render_basic_1_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_basic_1_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8200 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x004f0db2 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f1880 }, - { _MMIO(0x9888), 0x0a4f0011 }, - { _MMIO(0x9888), 0x0c4f0e3c }, - { _MMIO(0x9888), 0x0e4f1d80 }, - { _MMIO(0x9888), 0x086c0002 }, - { _MMIO(0x9888), 0x0a6c0100 }, - { _MMIO(0x9888), 0x0e6c000c }, - { _MMIO(0x9888), 0x026c000b }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x081b4000 }, - { _MMIO(0x9888), 0x0a1b8000 }, - { _MMIO(0x9888), 0x0e1b4000 }, - { _MMIO(0x9888), 0x021b4000 }, - { _MMIO(0x9888), 0x1a1c4000 }, - { _MMIO(0x9888), 0x1c1c0012 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x005bc000 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b8000 }, - { _MMIO(0x9888), 0x0a5b4000 }, - { _MMIO(0x9888), 0x0c5bc000 }, - { _MMIO(0x9888), 0x0e5b8000 }, - { _MMIO(0x9888), 0x105c8000 }, - { _MMIO(0x9888), 0x1a5ca000 }, - { _MMIO(0x9888), 0x1c5c002d }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x0a4c0800 }, - { _MMIO(0x9888), 0x0c4c0082 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002cc000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cbe00 }, - { _MMIO(0x9888), 0x182c00ef }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900167 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900840 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900842 }, - { _MMIO(0x9888), 0x47900840 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900840 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900840 }, - { _MMIO(0x9888), 0x53901111 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1810 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0000 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900167 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900842 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53901111 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_compute_basic_0_slices_0x01_and_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x15968000 }, - { _MMIO(0x9888), 0x17968000 }, - { _MMIO(0x9888), 0x0f96c000 }, - { _MMIO(0x9888), 0x1f950011 }, - { _MMIO(0x9888), 0x1d950014 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x0b978000 }, - { _MMIO(0x9888), 0x0f974000 }, - { _MMIO(0x9888), 0x11974000 }, - { _MMIO(0x9888), 0x13978000 }, - { _MMIO(0x9888), 0x09974000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x419010a0 }, - { _MMIO(0x9888), 0x55904000 }, - { _MMIO(0x9888), 0x45901000 }, - { _MMIO(0x9888), 0x47900084 }, - { _MMIO(0x9888), 0x57904400 }, - { _MMIO(0x9888), 0x499000a5 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900081 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x439014a4 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile_0_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x05e5a000 }, - { _MMIO(0x9888), 0x01e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x419010a0 }, - { _MMIO(0x9888), 0x55904000 }, - { _MMIO(0x9888), 0x45901000 }, - { _MMIO(0x9888), 0x47900084 }, - { _MMIO(0x9888), 0x57904400 }, - { _MMIO(0x9888), 0x499000a5 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900081 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x439014a4 }, - { _MMIO(0x9888), 0x53900400 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 2); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 2); - - if (dev_priv->drm.pdev->revision < 0x02) { - regs[n] = mux_config_render_pipe_profile_0_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_lt_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x02) { - regs[n] = mux_config_render_pipe_profile_0_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile_0_sku_gte_0x02); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13946000 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x0f968000 }, - { _MMIO(0x9888), 0x1196c000 }, - { _MMIO(0x9888), 0x13964000 }, - { _MMIO(0x9888), 0x11938000 }, - { _MMIO(0x9888), 0x1b93fe00 }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x19940000 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x1d940000 }, - { _MMIO(0x9888), 0x1b954000 }, - { _MMIO(0x9888), 0x1d95a550 }, - { _MMIO(0x9888), 0x1f9502aa }, - { _MMIO(0x9888), 0x2f900157 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13946000 }, - { _MMIO(0x9888), 0x15940016 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x1b93aa55 }, - { _MMIO(0x9888), 0x1d9300aa }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x0f940018 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x01e58000 }, - { _MMIO(0x9888), 0x03e57000 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c20 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900421 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900421 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900061 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads_0_sku_gte_0x05[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((dev_priv->drm.pdev->revision < 0x05) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_lt_0x05_and_sku_gte_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x05) { - regs[n] = mux_config_memory_reads_0_sku_gte_0x05; - lens[n] = ARRAY_SIZE(mux_config_memory_reads_0_sku_gte_0x05); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13945400 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901400 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x0f968000 }, - { _MMIO(0x9888), 0x1196c000 }, - { _MMIO(0x9888), 0x13964000 }, - { _MMIO(0x9888), 0x11938000 }, - { _MMIO(0x9888), 0x1b93fe00 }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x19940000 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x1d940000 }, - { _MMIO(0x9888), 0x1b954000 }, - { _MMIO(0x9888), 0x1d95a550 }, - { _MMIO(0x9888), 0x1f9502aa }, - { _MMIO(0x9888), 0x2f900167 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x13945400 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901400 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x19930800 }, - { _MMIO(0x9888), 0x1b93aa55 }, - { _MMIO(0x9888), 0x1d93002a }, - { _MMIO(0x9888), 0x01940010 }, - { _MMIO(0x9888), 0x07941100 }, - { _MMIO(0x9888), 0x09941312 }, - { _MMIO(0x9888), 0x0b941514 }, - { _MMIO(0x9888), 0x0d941716 }, - { _MMIO(0x9888), 0x1b940000 }, - { _MMIO(0x9888), 0x11940000 }, - { _MMIO(0x9888), 0x01e58000 }, - { _MMIO(0x9888), 0x03e57000 }, - { _MMIO(0x9888), 0x2f900167 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x13908000 }, - { _MMIO(0x9888), 0x21908000 }, - { _MMIO(0x9888), 0x23908000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27908000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c20 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900421 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900421 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes_0_sku_gte_0x05[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 3); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 3); - - if ((INTEL_INFO(dev_priv)->sseu.slice_mask & 0x01) && - (dev_priv->drm.pdev->revision < 0x02)) { - regs[n] = mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_slices_0x01_and_sku_lt_0x02); - n++; - } - if ((dev_priv->drm.pdev->revision < 0x05) && - (dev_priv->drm.pdev->revision >= 0x02)) { - regs[n] = mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_lt_0x05_and_sku_gte_0x02); - n++; - } - if (dev_priv->drm.pdev->revision >= 0x05) { - regs[n] = mux_config_memory_writes_0_sku_gte_0x05; - lens[n] = ARRAY_SIZE(mux_config_memory_writes_0_sku_gte_0x05); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended_0_subslices_0x01[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0xd28), 0x00000000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - if (INTEL_INFO(dev_priv)->sseu.subslice_mask & 0x01) { - regs[n] = mux_config_compute_extended_0_subslices_0x01; - lens[n] = ARRAY_SIZE(mux_config_compute_extended_0_subslices_0x01); - n++; - } - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f901403 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900167 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900042 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53901111 }, - { _MMIO(0x9888), 0x43900420 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x4b9000a0 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { - { _MMIO(0xe458), 0x00001000 }, - { _MMIO(0xe558), 0x00003002 }, - { _MMIO(0xe658), 0x00005004 }, - { _MMIO(0xe758), 0x00011010 }, - { _MMIO(0xe45c), 0x00050012 }, - { _MMIO(0xe55c), 0x00052051 }, - { _MMIO(0xe65c), 0x00000008 }, -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0e0f006c }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1190e000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x43900c00 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x143a5800 }, - { _MMIO(0x9888), 0x163a00c0 }, - { _MMIO(0x9888), 0x12380240 }, - { _MMIO(0x9888), 0x14380002 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c1500 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f9500 }, - { _MMIO(0x9888), 0x100f002a }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x0a2dc000 }, - { _MMIO(0x9888), 0x0c2dc000 }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x06393000 }, - { _MMIO(0x9888), 0x0c3a28c1 }, - { _MMIO(0x9888), 0x003a0000 }, - { _MMIO(0x9888), 0x0a33f000 }, - { _MMIO(0x9888), 0x0c33f000 }, - { _MMIO(0x9888), 0x0a37a000 }, - { _MMIO(0x9888), 0x0c37a000 }, - { _MMIO(0x9888), 0x0a380977 }, - { _MMIO(0x9888), 0x08380000 }, - { _MMIO(0x9888), 0x04380000 }, - { _MMIO(0x9888), 0x06383000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900800 }, - { _MMIO(0x9888), 0x47901000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900844 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2714), 0xf0800000 }, @@ -2370,6 +59,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810016 }, { _MMIO(0x9888), 0x1f810000 }, @@ -2384,1096 +74,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "f519e481-24d2-4d42-87c9-3fdd12c00202", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "fe47b29d-ae51-423e-bff4-27d965a95b60", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "e0ad5ae0-84ba-4f29-a723-1906c12cb774", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "9bc436dd-6130-4add-affc-283eb6eaa864", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "2ea0da8f-3527-4669-9d9d-13099a7435bf", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "d97d16af-028b-4cd1-a672-6210cb5513dd", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "9fb22842-e708-43f7-9752-e0e41670c39e", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "5378e2a1-4248-4188-a4ae-da25a794c603", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "f42cdd6a-b000-42cb-870f-5eb423a7f514", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "b9bf2423-d88c-4a7b-a051-627611d00dcc", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "2414a93d-d84f-406e-99c0-472161194b40", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "b4cff514-a91e-4798-a0b3-426ca13fc9c1", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "7821d13b-9b8b-4405-9618-78cd56b62cce", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "893f1a4d-919d-4388-8cb7-746d73ea7259", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "41a24047-7484-4ead-ae37-de907e5ff2b2", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "95910492-943f-44bd-9461-390240f243fd", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "1651949f-0ac0-4cb1-a06f-dafd74a407d1", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt2.h b/drivers/gpu/drm/i915/i915_oa_sklgt2.h index f4397baf3328..fe1aa2c03958 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt2.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt2.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT2_H__ #define __I915_OA_SKLGT2_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt2; - -extern int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.c b/drivers/gpu/drm/i915/i915_oa_sklgt3.c index 7765e22dfa17..85e51addf86a 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.c @@ -31,1876 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt3.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt3 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e0380 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c8400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f6600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162ca200 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x082d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x0833c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x08370840 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0200 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8000 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x51907710 }, - { _MMIO(0x9888), 0x419020a0 }, - { _MMIO(0x9888), 0x55901515 }, - { _MMIO(0x9888), 0x45900529 }, - { _MMIO(0x9888), 0x47901025 }, - { _MMIO(0x9888), 0x57907770 }, - { _MMIO(0x9888), 0x49902100 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900108 }, - { _MMIO(0x9888), 0x59900007 }, - { _MMIO(0x9888), 0x43902108 }, - { _MMIO(0x9888), 0x53907777 }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900863 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900c62 }, - { _MMIO(0x9888), 0x53903333 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51901150 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x55905111 }, - { _MMIO(0x9888), 0x45901400 }, - { _MMIO(0x9888), 0x479004a5 }, - { _MMIO(0x9888), 0x57903455 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b9000a0 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x43900005 }, - { _MMIO(0x9888), 0x53900455 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900063 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53903333 }, - { _MMIO(0x9888), 0x43900840 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900005 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900402 }, - { _MMIO(0x9888), 0x53901550 }, - { _MMIO(0x9888), 0x45900080 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900050 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900115 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x47900884 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1930,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1944,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "4616d450-2393-4836-8146-53c5ed84d359", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "4320492b-fd03-42ac-922f-dbe1ef3b7b58", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "4ca0f3fe-7fd3-4924-98cb-1807d9879767", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "a0c0172c-ee13-403d-99ff-2bdf6936cf14", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "52435e0b-f188-42ea-8680-21a56ee20dee", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "27076eeb-49f3-4fed-8423-c66506005c63", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "8071b409-c39a-4674-94d7-32962ecfb512", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "25dc828e-1d2d-426e-9546-a1d4233cdf16", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "3dba9405-2d7e-4d70-8199-e734e82fd6bf", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "b375c985-9953-455b-bda2-b03f7594e9db", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "cfae9232-6ffc-42cc-a703-9790016925f0", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "2b985803-d3c9-4629-8a4f-634bfecba0e8", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "2b985803-d3c9-4629-8a4f-634bfecba0e8", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt3.h b/drivers/gpu/drm/i915/i915_oa_sklgt3.h index c0accb1f9b74..06746b2616c8 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt3.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt3.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT3_H__ #define __I915_OA_SKLGT3_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt3; - -extern int i915_oa_select_metric_set_sklgt3(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt3(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt3(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.c b/drivers/gpu/drm/i915/i915_oa_sklgt4.c index 9ddab43a2176..bce031ee4445 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.c +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.c @@ -31,1930 +31,6 @@ #include "i915_drv.h" #include "i915_oa_sklgt4.h" -enum metric_set_id { - METRIC_SET_ID_RENDER_BASIC = 1, - METRIC_SET_ID_COMPUTE_BASIC, - METRIC_SET_ID_RENDER_PIPE_PROFILE, - METRIC_SET_ID_MEMORY_READS, - METRIC_SET_ID_MEMORY_WRITES, - METRIC_SET_ID_COMPUTE_EXTENDED, - METRIC_SET_ID_COMPUTE_L3_CACHE, - METRIC_SET_ID_HDC_AND_SF, - METRIC_SET_ID_L3_1, - METRIC_SET_ID_L3_2, - METRIC_SET_ID_L3_3, - METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, - METRIC_SET_ID_SAMPLER, - METRIC_SET_ID_TDL_1, - METRIC_SET_ID_TDL_2, - METRIC_SET_ID_COMPUTE_EXTRA, - METRIC_SET_ID_VME_PIPE, - METRIC_SET_ID_TEST_OA, -}; - -int i915_oa_n_builtin_metric_sets_sklgt4 = 18; - -static const struct i915_oa_reg b_counter_config_render_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_render_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_render_basic[] = { - { _MMIO(0x9888), 0x166c01e0 }, - { _MMIO(0x9888), 0x12170280 }, - { _MMIO(0x9888), 0x12370280 }, - { _MMIO(0x9888), 0x16ec01e0 }, - { _MMIO(0x9888), 0x176c01e0 }, - { _MMIO(0x9888), 0x11930317 }, - { _MMIO(0x9888), 0x159303df }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x1a4e03b0 }, - { _MMIO(0x9888), 0x0a6c0053 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x0a1b4000 }, - { _MMIO(0x9888), 0x1c1c0001 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x042f1000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4ca400 }, - { _MMIO(0x9888), 0x0c4c0002 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5600 }, - { _MMIO(0x9888), 0x100f0001 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x062d8000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x08133000 }, - { _MMIO(0x9888), 0x00170020 }, - { _MMIO(0x9888), 0x08170021 }, - { _MMIO(0x9888), 0x10170000 }, - { _MMIO(0x9888), 0x0633c000 }, - { _MMIO(0x9888), 0x06370800 }, - { _MMIO(0x9888), 0x10370000 }, - { _MMIO(0x9888), 0x1ace0230 }, - { _MMIO(0x9888), 0x0aec5300 }, - { _MMIO(0x9888), 0x10ec0000 }, - { _MMIO(0x9888), 0x1cec0000 }, - { _MMIO(0x9888), 0x0a9b8000 }, - { _MMIO(0x9888), 0x1c9c0002 }, - { _MMIO(0x9888), 0x0acc2000 }, - { _MMIO(0x9888), 0x0ccc0002 }, - { _MMIO(0x9888), 0x088d8000 }, - { _MMIO(0x9888), 0x0a8d8000 }, - { _MMIO(0x9888), 0x0e8f1000 }, - { _MMIO(0x9888), 0x108f0001 }, - { _MMIO(0x9888), 0x16ac8800 }, - { _MMIO(0x9888), 0x1b4e0020 }, - { _MMIO(0x9888), 0x096c5300 }, - { _MMIO(0x9888), 0x116c0000 }, - { _MMIO(0x9888), 0x1d6c0000 }, - { _MMIO(0x9888), 0x091b8000 }, - { _MMIO(0x9888), 0x1b1c8000 }, - { _MMIO(0x9888), 0x0b4c2000 }, - { _MMIO(0x9888), 0x090d8000 }, - { _MMIO(0x9888), 0x0f0f1000 }, - { _MMIO(0x9888), 0x172c0800 }, - { _MMIO(0x9888), 0x0d933031 }, - { _MMIO(0x9888), 0x0f933e3f }, - { _MMIO(0x9888), 0x01933d00 }, - { _MMIO(0x9888), 0x0393073c }, - { _MMIO(0x9888), 0x0593000e }, - { _MMIO(0x9888), 0x1d930000 }, - { _MMIO(0x9888), 0x19930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x2b908000 }, - { _MMIO(0x9888), 0x2d908000 }, - { _MMIO(0x9888), 0x2f908000 }, - { _MMIO(0x9888), 0x31908000 }, - { _MMIO(0x9888), 0x15908000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190003f }, - { _MMIO(0x9888), 0x5190ff30 }, - { _MMIO(0x9888), 0x41900060 }, - { _MMIO(0x9888), 0x55903033 }, - { _MMIO(0x9888), 0x45901421 }, - { _MMIO(0x9888), 0x47900803 }, - { _MMIO(0x9888), 0x5790fff1 }, - { _MMIO(0x9888), 0x49900001 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x5990000f }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x5390ffff }, -}; - -static int -get_render_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_basic; - lens[n] = ARRAY_SIZE(mux_config_render_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_basic[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2740), 0x00000000 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_basic[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_basic[] = { - { _MMIO(0x9888), 0x104f00e0 }, - { _MMIO(0x9888), 0x124f1c00 }, - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x1a4e0820 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x064f0900 }, - { _MMIO(0x9888), 0x084f0032 }, - { _MMIO(0x9888), 0x0a4f1891 }, - { _MMIO(0x9888), 0x0c4f0e00 }, - { _MMIO(0x9888), 0x0e4f003c }, - { _MMIO(0x9888), 0x004f0d80 }, - { _MMIO(0x9888), 0x024f003b }, - { _MMIO(0x9888), 0x006c0002 }, - { _MMIO(0x9888), 0x086c0100 }, - { _MMIO(0x9888), 0x0c6c000c }, - { _MMIO(0x9888), 0x0e6c0b00 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x081b8000 }, - { _MMIO(0x9888), 0x0c1b4000 }, - { _MMIO(0x9888), 0x0e1b8000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1c8000 }, - { _MMIO(0x9888), 0x1c1c0024 }, - { _MMIO(0x9888), 0x065b8000 }, - { _MMIO(0x9888), 0x085b4000 }, - { _MMIO(0x9888), 0x0a5bc000 }, - { _MMIO(0x9888), 0x0c5b8000 }, - { _MMIO(0x9888), 0x0e5b4000 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025b4000 }, - { _MMIO(0x9888), 0x1a5c6000 }, - { _MMIO(0x9888), 0x1c5c001b }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2000 }, - { _MMIO(0x9888), 0x0c4c0208 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020d2000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2cc000 }, - { _MMIO(0x9888), 0x162cfb00 }, - { _MMIO(0x9888), 0x182c00be }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x19900157 }, - { _MMIO(0x9888), 0x1b900158 }, - { _MMIO(0x9888), 0x1d900105 }, - { _MMIO(0x9888), 0x1f900103 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x11900fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900821 }, - { _MMIO(0x9888), 0x47900802 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900802 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900422 }, - { _MMIO(0x9888), 0x53905555 }, -}; - -static int -get_compute_basic_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_basic; - lens[n] = ARRAY_SIZE(mux_config_compute_basic); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007ffea }, - { _MMIO(0x2774), 0x00007ffc }, - { _MMIO(0x2778), 0x0007affa }, - { _MMIO(0x277c), 0x0000f5fd }, - { _MMIO(0x2780), 0x00079ffa }, - { _MMIO(0x2784), 0x0000f3fb }, - { _MMIO(0x2788), 0x0007bf7a }, - { _MMIO(0x278c), 0x0000f7e7 }, - { _MMIO(0x2790), 0x0007fefa }, - { _MMIO(0x2794), 0x0000f7cf }, - { _MMIO(0x2798), 0x00077ffa }, - { _MMIO(0x279c), 0x0000efdf }, - { _MMIO(0x27a0), 0x0006fffa }, - { _MMIO(0x27a4), 0x0000cfbf }, - { _MMIO(0x27a8), 0x0003fffa }, - { _MMIO(0x27ac), 0x00005f7f }, -}; - -static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_render_pipe_profile[] = { - { _MMIO(0x9888), 0x0c0e001f }, - { _MMIO(0x9888), 0x0a0f0000 }, - { _MMIO(0x9888), 0x10116800 }, - { _MMIO(0x9888), 0x178a03e0 }, - { _MMIO(0x9888), 0x11824c00 }, - { _MMIO(0x9888), 0x11830020 }, - { _MMIO(0x9888), 0x13840020 }, - { _MMIO(0x9888), 0x11850019 }, - { _MMIO(0x9888), 0x11860007 }, - { _MMIO(0x9888), 0x01870c40 }, - { _MMIO(0x9888), 0x17880000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0a4c0040 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x040d4000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020e5400 }, - { _MMIO(0x9888), 0x000e0000 }, - { _MMIO(0x9888), 0x080f0040 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x100f0000 }, - { _MMIO(0x9888), 0x0e0f0040 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06110012 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x01898000 }, - { _MMIO(0x9888), 0x0d890100 }, - { _MMIO(0x9888), 0x03898000 }, - { _MMIO(0x9888), 0x09808000 }, - { _MMIO(0x9888), 0x0b808000 }, - { _MMIO(0x9888), 0x0380c000 }, - { _MMIO(0x9888), 0x0f8a0075 }, - { _MMIO(0x9888), 0x1d8a0000 }, - { _MMIO(0x9888), 0x118a8000 }, - { _MMIO(0x9888), 0x1b8a4000 }, - { _MMIO(0x9888), 0x138a8000 }, - { _MMIO(0x9888), 0x1d81a000 }, - { _MMIO(0x9888), 0x15818000 }, - { _MMIO(0x9888), 0x17818000 }, - { _MMIO(0x9888), 0x0b820030 }, - { _MMIO(0x9888), 0x07828000 }, - { _MMIO(0x9888), 0x0d824000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x05824000 }, - { _MMIO(0x9888), 0x0d830003 }, - { _MMIO(0x9888), 0x0583000c }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x03838000 }, - { _MMIO(0x9888), 0x07838000 }, - { _MMIO(0x9888), 0x0b840980 }, - { _MMIO(0x9888), 0x03844d80 }, - { _MMIO(0x9888), 0x11840000 }, - { _MMIO(0x9888), 0x09848000 }, - { _MMIO(0x9888), 0x09850080 }, - { _MMIO(0x9888), 0x03850003 }, - { _MMIO(0x9888), 0x01850000 }, - { _MMIO(0x9888), 0x07860000 }, - { _MMIO(0x9888), 0x0f860400 }, - { _MMIO(0x9888), 0x09870032 }, - { _MMIO(0x9888), 0x01888052 }, - { _MMIO(0x9888), 0x11880000 }, - { _MMIO(0x9888), 0x09884000 }, - { _MMIO(0x9888), 0x1b931001 }, - { _MMIO(0x9888), 0x1d930001 }, - { _MMIO(0x9888), 0x19934000 }, - { _MMIO(0x9888), 0x1b958000 }, - { _MMIO(0x9888), 0x1d950094 }, - { _MMIO(0x9888), 0x19958000 }, - { _MMIO(0x9888), 0x09e58000 }, - { _MMIO(0x9888), 0x0be58000 }, - { _MMIO(0x9888), 0x03e5c000 }, - { _MMIO(0x9888), 0x0592c000 }, - { _MMIO(0x9888), 0x0b928000 }, - { _MMIO(0x9888), 0x0d924000 }, - { _MMIO(0x9888), 0x0f924000 }, - { _MMIO(0x9888), 0x11928000 }, - { _MMIO(0x9888), 0x1392c000 }, - { _MMIO(0x9888), 0x09924000 }, - { _MMIO(0x9888), 0x01985000 }, - { _MMIO(0x9888), 0x07988000 }, - { _MMIO(0x9888), 0x09981000 }, - { _MMIO(0x9888), 0x0b982000 }, - { _MMIO(0x9888), 0x0d982000 }, - { _MMIO(0x9888), 0x0f989000 }, - { _MMIO(0x9888), 0x05982000 }, - { _MMIO(0x9888), 0x13904000 }, - { _MMIO(0x9888), 0x21904000 }, - { _MMIO(0x9888), 0x23904000 }, - { _MMIO(0x9888), 0x25908000 }, - { _MMIO(0x9888), 0x27904000 }, - { _MMIO(0x9888), 0x29908000 }, - { _MMIO(0x9888), 0x2b904000 }, - { _MMIO(0x9888), 0x2f904000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x15904000 }, - { _MMIO(0x9888), 0x17908000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b904000 }, - { _MMIO(0x9888), 0x1190c080 }, - { _MMIO(0x9888), 0x51901110 }, - { _MMIO(0x9888), 0x41900440 }, - { _MMIO(0x9888), 0x55901111 }, - { _MMIO(0x9888), 0x45900400 }, - { _MMIO(0x9888), 0x47900c21 }, - { _MMIO(0x9888), 0x57901411 }, - { _MMIO(0x9888), 0x49900042 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900024 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x43900841 }, - { _MMIO(0x9888), 0x53900411 }, -}; - -static int -get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_render_pipe_profile; - lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_reads[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f872 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_reads[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_reads[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f900064 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900150 }, - { _MMIO(0x9888), 0x21900151 }, - { _MMIO(0x9888), 0x23900152 }, - { _MMIO(0x9888), 0x25900153 }, - { _MMIO(0x9888), 0x27900154 }, - { _MMIO(0x9888), 0x29900155 }, - { _MMIO(0x9888), 0x2b900156 }, - { _MMIO(0x9888), 0x2d900157 }, - { _MMIO(0x9888), 0x2f90015f }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_reads_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_reads; - lens[n] = ARRAY_SIZE(mux_config_memory_reads); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_memory_writes[] = { - { _MMIO(0x272c), 0xffffffff }, - { _MMIO(0x2728), 0xffffffff }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x271c), 0xffffffff }, - { _MMIO(0x2718), 0xffffffff }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x274c), 0x86543210 }, - { _MMIO(0x2748), 0x86543210 }, - { _MMIO(0x2744), 0x00006667 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x275c), 0x86543210 }, - { _MMIO(0x2758), 0x86543210 }, - { _MMIO(0x2754), 0x00006465 }, - { _MMIO(0x2750), 0x00000000 }, - { _MMIO(0x2770), 0x0007f81a }, - { _MMIO(0x2774), 0x0000fe00 }, - { _MMIO(0x2778), 0x0007f82a }, - { _MMIO(0x277c), 0x0000fe00 }, - { _MMIO(0x2780), 0x0007f822 }, - { _MMIO(0x2784), 0x0000fe00 }, - { _MMIO(0x2788), 0x0007f8ba }, - { _MMIO(0x278c), 0x0000fe00 }, - { _MMIO(0x2790), 0x0007f87a }, - { _MMIO(0x2794), 0x0000fe00 }, - { _MMIO(0x2798), 0x0007f8ea }, - { _MMIO(0x279c), 0x0000fe00 }, - { _MMIO(0x27a0), 0x0007f8e2 }, - { _MMIO(0x27a4), 0x0000fe00 }, - { _MMIO(0x27a8), 0x0007f8f2 }, - { _MMIO(0x27ac), 0x0000fe00 }, -}; - -static const struct i915_oa_reg flex_eu_config_memory_writes[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00015014 }, - { _MMIO(0xe658), 0x00025024 }, - { _MMIO(0xe758), 0x00035034 }, - { _MMIO(0xe45c), 0x00045044 }, - { _MMIO(0xe55c), 0x00055054 }, - { _MMIO(0xe65c), 0x00065064 }, -}; - -static const struct i915_oa_reg mux_config_memory_writes[] = { - { _MMIO(0x9888), 0x11810c00 }, - { _MMIO(0x9888), 0x1381001a }, - { _MMIO(0x9888), 0x37906800 }, - { _MMIO(0x9888), 0x3f901000 }, - { _MMIO(0x9888), 0x03811300 }, - { _MMIO(0x9888), 0x05811b12 }, - { _MMIO(0x9888), 0x0781001a }, - { _MMIO(0x9888), 0x1f810000 }, - { _MMIO(0x9888), 0x17810000 }, - { _MMIO(0x9888), 0x19810000 }, - { _MMIO(0x9888), 0x1b810000 }, - { _MMIO(0x9888), 0x1d810000 }, - { _MMIO(0x9888), 0x1b930055 }, - { _MMIO(0x9888), 0x03e58000 }, - { _MMIO(0x9888), 0x05e5c000 }, - { _MMIO(0x9888), 0x07e54000 }, - { _MMIO(0x9888), 0x13900160 }, - { _MMIO(0x9888), 0x21900161 }, - { _MMIO(0x9888), 0x23900162 }, - { _MMIO(0x9888), 0x25900163 }, - { _MMIO(0x9888), 0x27900164 }, - { _MMIO(0x9888), 0x29900165 }, - { _MMIO(0x9888), 0x2b900166 }, - { _MMIO(0x9888), 0x2d900167 }, - { _MMIO(0x9888), 0x2f900150 }, - { _MMIO(0x9888), 0x31900105 }, - { _MMIO(0x9888), 0x15900103 }, - { _MMIO(0x9888), 0x17900101 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1d908000 }, - { _MMIO(0x9888), 0x1f908000 }, - { _MMIO(0x9888), 0x11900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c60 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900c63 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c63 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900063 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_memory_writes_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_memory_writes; - lens[n] = ARRAY_SIZE(mux_config_memory_writes); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extended[] = { - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fc2a }, - { _MMIO(0x2774), 0x0000bf00 }, - { _MMIO(0x2778), 0x0007fc6a }, - { _MMIO(0x277c), 0x0000bf00 }, - { _MMIO(0x2780), 0x0007fc92 }, - { _MMIO(0x2784), 0x0000bf00 }, - { _MMIO(0x2788), 0x0007fca2 }, - { _MMIO(0x278c), 0x0000bf00 }, - { _MMIO(0x2790), 0x0007fc32 }, - { _MMIO(0x2794), 0x0000bf00 }, - { _MMIO(0x2798), 0x0007fc9a }, - { _MMIO(0x279c), 0x0000bf00 }, - { _MMIO(0x27a0), 0x0007fe6a }, - { _MMIO(0x27a4), 0x0000bf00 }, - { _MMIO(0x27a8), 0x0007fe7a }, - { _MMIO(0x27ac), 0x0000bf00 }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_extended[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00778008 }, - { _MMIO(0xe45c), 0x00088078 }, - { _MMIO(0xe55c), 0x00808708 }, - { _MMIO(0xe65c), 0x00a08908 }, -}; - -static const struct i915_oa_reg mux_config_compute_extended[] = { - { _MMIO(0x9888), 0x106c00e0 }, - { _MMIO(0x9888), 0x141c8160 }, - { _MMIO(0x9888), 0x161c8015 }, - { _MMIO(0x9888), 0x181c0120 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4eaaa0 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0e6c0b01 }, - { _MMIO(0x9888), 0x006c0200 }, - { _MMIO(0x9888), 0x026c000c }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x001c0041 }, - { _MMIO(0x9888), 0x061c4200 }, - { _MMIO(0x9888), 0x081c4443 }, - { _MMIO(0x9888), 0x0a1c4645 }, - { _MMIO(0x9888), 0x0c1c7647 }, - { _MMIO(0x9888), 0x041c7357 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x101c0000 }, - { _MMIO(0x9888), 0x1a1c0000 }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4caa2a }, - { _MMIO(0x9888), 0x0c4c02aa }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x000da000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x0c0f5400 }, - { _MMIO(0x9888), 0x0e0f5515 }, - { _MMIO(0x9888), 0x100f0155 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x11907fff }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900040 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900802 }, - { _MMIO(0x9888), 0x47900842 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900842 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x43900800 }, - { _MMIO(0x9888), 0x53900000 }, -}; - -static int -get_compute_extended_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extended; - lens[n] = ARRAY_SIZE(mux_config_compute_extended); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2770), 0x0007fffa }, - { _MMIO(0x2774), 0x0000fefe }, - { _MMIO(0x2778), 0x0007fffa }, - { _MMIO(0x277c), 0x0000fefd }, - { _MMIO(0x2790), 0x0007fffa }, - { _MMIO(0x2794), 0x0000fbef }, - { _MMIO(0x2798), 0x0007fffa }, - { _MMIO(0x279c), 0x0000fbdf }, -}; - -static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00000003 }, - { _MMIO(0xe658), 0x00002001 }, - { _MMIO(0xe758), 0x00101100 }, - { _MMIO(0xe45c), 0x00201200 }, - { _MMIO(0xe55c), 0x00301300 }, - { _MMIO(0xe65c), 0x00401400 }, -}; - -static const struct i915_oa_reg mux_config_compute_l3_cache[] = { - { _MMIO(0x9888), 0x166c0760 }, - { _MMIO(0x9888), 0x1593001e }, - { _MMIO(0x9888), 0x3f900003 }, - { _MMIO(0x9888), 0x004e8000 }, - { _MMIO(0x9888), 0x0e4e8000 }, - { _MMIO(0x9888), 0x184e8000 }, - { _MMIO(0x9888), 0x1a4e8020 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x006c0051 }, - { _MMIO(0x9888), 0x066c5000 }, - { _MMIO(0x9888), 0x086c5c5d }, - { _MMIO(0x9888), 0x0e6c5e5f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x186c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x001b4000 }, - { _MMIO(0x9888), 0x061b8000 }, - { _MMIO(0x9888), 0x081bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x101c8000 }, - { _MMIO(0x9888), 0x1a1ce000 }, - { _MMIO(0x9888), 0x1c1c0030 }, - { _MMIO(0x9888), 0x004c8000 }, - { _MMIO(0x9888), 0x0a4c2a00 }, - { _MMIO(0x9888), 0x0c4c0280 }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f1500 }, - { _MMIO(0x9888), 0x100f0140 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162c0a00 }, - { _MMIO(0x9888), 0x182c00a0 }, - { _MMIO(0x9888), 0x03933300 }, - { _MMIO(0x9888), 0x05930032 }, - { _MMIO(0x9888), 0x11930000 }, - { _MMIO(0x9888), 0x1b930000 }, - { _MMIO(0x9888), 0x1d900157 }, - { _MMIO(0x9888), 0x1f900158 }, - { _MMIO(0x9888), 0x35900000 }, - { _MMIO(0x9888), 0x19908000 }, - { _MMIO(0x9888), 0x1b908000 }, - { _MMIO(0x9888), 0x1190030f }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900000 }, - { _MMIO(0x9888), 0x55900000 }, - { _MMIO(0x9888), 0x45900021 }, - { _MMIO(0x9888), 0x47900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x4b900000 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x53905555 }, - { _MMIO(0x9888), 0x43900000 }, -}; - -static int -get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_l3_cache; - lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x10800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000fdff }, -}; - -static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_hdc_and_sf[] = { - { _MMIO(0x9888), 0x104f0232 }, - { _MMIO(0x9888), 0x124f4640 }, - { _MMIO(0x9888), 0x106c0232 }, - { _MMIO(0x9888), 0x11834400 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x004f1880 }, - { _MMIO(0x9888), 0x024f08bb }, - { _MMIO(0x9888), 0x044f001b }, - { _MMIO(0x9888), 0x046c0100 }, - { _MMIO(0x9888), 0x066c000b }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x041b8000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x005b8000 }, - { _MMIO(0x9888), 0x025bc000 }, - { _MMIO(0x9888), 0x045b4000 }, - { _MMIO(0x9888), 0x125c8000 }, - { _MMIO(0x9888), 0x145c8000 }, - { _MMIO(0x9888), 0x165c8000 }, - { _MMIO(0x9888), 0x185c8000 }, - { _MMIO(0x9888), 0x0a4c00a0 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x022cc000 }, - { _MMIO(0x9888), 0x042cc000 }, - { _MMIO(0x9888), 0x062cc000 }, - { _MMIO(0x9888), 0x082cc000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x0f828000 }, - { _MMIO(0x9888), 0x0f8305c0 }, - { _MMIO(0x9888), 0x09830000 }, - { _MMIO(0x9888), 0x07830000 }, - { _MMIO(0x9888), 0x1d950080 }, - { _MMIO(0x9888), 0x13928000 }, - { _MMIO(0x9888), 0x0f988000 }, - { _MMIO(0x9888), 0x31904000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x59900001 }, - { _MMIO(0x9888), 0x4b900040 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_hdc_and_sf; - lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0xf0800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00014002 }, - { _MMIO(0x277c), 0x0000c3ff }, - { _MMIO(0x2780), 0x00010002 }, - { _MMIO(0x2784), 0x0000c7ff }, - { _MMIO(0x2788), 0x00004002 }, - { _MMIO(0x278c), 0x0000d3ff }, - { _MMIO(0x2790), 0x00100700 }, - { _MMIO(0x2794), 0x0000ff1f }, - { _MMIO(0x2798), 0x00001402 }, - { _MMIO(0x279c), 0x0000fc3f }, - { _MMIO(0x27a0), 0x00001002 }, - { _MMIO(0x27a4), 0x0000fc7f }, - { _MMIO(0x27a8), 0x00000402 }, - { _MMIO(0x27ac), 0x0000fd3f }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_1[] = { - { _MMIO(0x9888), 0x126c7b40 }, - { _MMIO(0x9888), 0x166c0020 }, - { _MMIO(0x9888), 0x0a603444 }, - { _MMIO(0x9888), 0x0a613400 }, - { _MMIO(0x9888), 0x1a4ea800 }, - { _MMIO(0x9888), 0x1c4e0002 }, - { _MMIO(0x9888), 0x024e8000 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x0c6c5327 }, - { _MMIO(0x9888), 0x0e6c5425 }, - { _MMIO(0x9888), 0x006c2a00 }, - { _MMIO(0x9888), 0x026c285b }, - { _MMIO(0x9888), 0x046c005c }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1c6c0000 }, - { _MMIO(0x9888), 0x1e6c0000 }, - { _MMIO(0x9888), 0x1a6c0800 }, - { _MMIO(0x9888), 0x0c1bc000 }, - { _MMIO(0x9888), 0x0e1bc000 }, - { _MMIO(0x9888), 0x001b8000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x1c1c003c }, - { _MMIO(0x9888), 0x121c8000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x10600000 }, - { _MMIO(0x9888), 0x04600000 }, - { _MMIO(0x9888), 0x0c610044 }, - { _MMIO(0x9888), 0x10610000 }, - { _MMIO(0x9888), 0x06610000 }, - { _MMIO(0x9888), 0x0c4c02a8 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0154 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x182c00aa }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190ffc0 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900420 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900021 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900400 }, - { _MMIO(0x9888), 0x43900421 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_l3_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_1; - lens[n] = ARRAY_SIZE(mux_config_l3_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_2[] = { - { _MMIO(0x9888), 0x126c02e0 }, - { _MMIO(0x9888), 0x146c0001 }, - { _MMIO(0x9888), 0x0a623400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x064f4000 }, - { _MMIO(0x9888), 0x026c3324 }, - { _MMIO(0x9888), 0x046c3422 }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c0000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c0800 }, - { _MMIO(0x9888), 0x065b4000 }, - { _MMIO(0x9888), 0x1a5c1000 }, - { _MMIO(0x9888), 0x06614000 }, - { _MMIO(0x9888), 0x0c620044 }, - { _MMIO(0x9888), 0x10620000 }, - { _MMIO(0x9888), 0x06620000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c002a }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2cc000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900000 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_2; - lens[n] = ARRAY_SIZE(mux_config_l3_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_l3_3[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00100070 }, - { _MMIO(0x2774), 0x0000fff1 }, - { _MMIO(0x2778), 0x00028002 }, - { _MMIO(0x277c), 0x000087ff }, - { _MMIO(0x2780), 0x00020002 }, - { _MMIO(0x2784), 0x00008fff }, - { _MMIO(0x2788), 0x00008002 }, - { _MMIO(0x278c), 0x0000a7ff }, -}; - -static const struct i915_oa_reg flex_eu_config_l3_3[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_l3_3[] = { - { _MMIO(0x9888), 0x126c4e80 }, - { _MMIO(0x9888), 0x146c0000 }, - { _MMIO(0x9888), 0x0a633400 }, - { _MMIO(0x9888), 0x044e8000 }, - { _MMIO(0x9888), 0x064e8000 }, - { _MMIO(0x9888), 0x084e8000 }, - { _MMIO(0x9888), 0x0a4e8000 }, - { _MMIO(0x9888), 0x0c4e8000 }, - { _MMIO(0x9888), 0x026c3321 }, - { _MMIO(0x9888), 0x046c342f }, - { _MMIO(0x9888), 0x106c0000 }, - { _MMIO(0x9888), 0x1a6c2000 }, - { _MMIO(0x9888), 0x021bc000 }, - { _MMIO(0x9888), 0x041bc000 }, - { _MMIO(0x9888), 0x061b4000 }, - { _MMIO(0x9888), 0x141c8000 }, - { _MMIO(0x9888), 0x161c8000 }, - { _MMIO(0x9888), 0x181c8000 }, - { _MMIO(0x9888), 0x1a1c1800 }, - { _MMIO(0x9888), 0x06604000 }, - { _MMIO(0x9888), 0x0c630044 }, - { _MMIO(0x9888), 0x10630000 }, - { _MMIO(0x9888), 0x06630000 }, - { _MMIO(0x9888), 0x084c8000 }, - { _MMIO(0x9888), 0x0a4c00aa }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0f4000 }, - { _MMIO(0x9888), 0x0e0f0055 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190f800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900002 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_l3_3_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_l3_3; - lens[n] = ARRAY_SIZE(mux_config_l3_3); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x30800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x0000efff }, - { _MMIO(0x2778), 0x00006000 }, - { _MMIO(0x277c), 0x0000f3ff }, -}; - -static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { - { _MMIO(0x9888), 0x102f3800 }, - { _MMIO(0x9888), 0x144d0500 }, - { _MMIO(0x9888), 0x120d03c0 }, - { _MMIO(0x9888), 0x140d03cf }, - { _MMIO(0x9888), 0x0c0f0004 }, - { _MMIO(0x9888), 0x0c4e4000 }, - { _MMIO(0x9888), 0x042f0480 }, - { _MMIO(0x9888), 0x082f0000 }, - { _MMIO(0x9888), 0x022f0000 }, - { _MMIO(0x9888), 0x0a4c0090 }, - { _MMIO(0x9888), 0x064d0027 }, - { _MMIO(0x9888), 0x004d0000 }, - { _MMIO(0x9888), 0x000d0d40 }, - { _MMIO(0x9888), 0x020d803f }, - { _MMIO(0x9888), 0x040d8023 }, - { _MMIO(0x9888), 0x100d0000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x020f0010 }, - { _MMIO(0x9888), 0x000f0000 }, - { _MMIO(0x9888), 0x0e0f0050 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41901400 }, - { _MMIO(0x9888), 0x43901485 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900001 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_rasterizer_and_pixel_backend; - lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_sampler[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x70800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, - { _MMIO(0x2770), 0x0000c000 }, - { _MMIO(0x2774), 0x0000e7ff }, - { _MMIO(0x2778), 0x00003000 }, - { _MMIO(0x277c), 0x0000f9ff }, - { _MMIO(0x2780), 0x00000c00 }, - { _MMIO(0x2784), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_sampler[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_sampler[] = { - { _MMIO(0x9888), 0x14152c00 }, - { _MMIO(0x9888), 0x16150005 }, - { _MMIO(0x9888), 0x121600a0 }, - { _MMIO(0x9888), 0x14352c00 }, - { _MMIO(0x9888), 0x16350005 }, - { _MMIO(0x9888), 0x123600a0 }, - { _MMIO(0x9888), 0x14552c00 }, - { _MMIO(0x9888), 0x16550005 }, - { _MMIO(0x9888), 0x125600a0 }, - { _MMIO(0x9888), 0x062f6000 }, - { _MMIO(0x9888), 0x022f2000 }, - { _MMIO(0x9888), 0x0c4c0050 }, - { _MMIO(0x9888), 0x0a4c0010 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0350 }, - { _MMIO(0x9888), 0x0c0fb000 }, - { _MMIO(0x9888), 0x0e0f00da }, - { _MMIO(0x9888), 0x182c0028 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x022dc000 }, - { _MMIO(0x9888), 0x042d4000 }, - { _MMIO(0x9888), 0x0c138000 }, - { _MMIO(0x9888), 0x0e132000 }, - { _MMIO(0x9888), 0x0413c000 }, - { _MMIO(0x9888), 0x1c140018 }, - { _MMIO(0x9888), 0x0c157000 }, - { _MMIO(0x9888), 0x0e150078 }, - { _MMIO(0x9888), 0x10150000 }, - { _MMIO(0x9888), 0x04162180 }, - { _MMIO(0x9888), 0x02160000 }, - { _MMIO(0x9888), 0x04174000 }, - { _MMIO(0x9888), 0x0233a000 }, - { _MMIO(0x9888), 0x04333000 }, - { _MMIO(0x9888), 0x14348000 }, - { _MMIO(0x9888), 0x16348000 }, - { _MMIO(0x9888), 0x02357870 }, - { _MMIO(0x9888), 0x10350000 }, - { _MMIO(0x9888), 0x04360043 }, - { _MMIO(0x9888), 0x02360000 }, - { _MMIO(0x9888), 0x04371000 }, - { _MMIO(0x9888), 0x0e538000 }, - { _MMIO(0x9888), 0x00538000 }, - { _MMIO(0x9888), 0x06533000 }, - { _MMIO(0x9888), 0x1c540020 }, - { _MMIO(0x9888), 0x12548000 }, - { _MMIO(0x9888), 0x0e557000 }, - { _MMIO(0x9888), 0x00557800 }, - { _MMIO(0x9888), 0x10550000 }, - { _MMIO(0x9888), 0x06560043 }, - { _MMIO(0x9888), 0x02560000 }, - { _MMIO(0x9888), 0x06571000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900000 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900060 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900842 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900060 }, -}; - -static int -get_sampler_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_sampler; - lens[n] = ARRAY_SIZE(mux_config_sampler); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_1[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00000002 }, - { _MMIO(0x2774), 0x00007fff }, - { _MMIO(0x2778), 0x00000000 }, - { _MMIO(0x277c), 0x00009fff }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000efff }, - { _MMIO(0x2788), 0x00000000 }, - { _MMIO(0x278c), 0x0000f3ff }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000fdff }, - { _MMIO(0x2798), 0x00000000 }, - { _MMIO(0x279c), 0x0000fe7f }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_1[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_1[] = { - { _MMIO(0x9888), 0x12120000 }, - { _MMIO(0x9888), 0x12320000 }, - { _MMIO(0x9888), 0x12520000 }, - { _MMIO(0x9888), 0x002f8000 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0015 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f03a0 }, - { _MMIO(0x9888), 0x0c0ff000 }, - { _MMIO(0x9888), 0x0e0f0095 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x0c2d8000 }, - { _MMIO(0x9888), 0x0e2d4000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x02108000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x02118000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x02121880 }, - { _MMIO(0x9888), 0x041219b5 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x02134000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x0c308000 }, - { _MMIO(0x9888), 0x0e304000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x0c318000 }, - { _MMIO(0x9888), 0x0e314000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x0c321a80 }, - { _MMIO(0x9888), 0x0e320033 }, - { _MMIO(0x9888), 0x06320031 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x0c334000 }, - { _MMIO(0x9888), 0x0e331000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0e508000 }, - { _MMIO(0x9888), 0x00508000 }, - { _MMIO(0x9888), 0x02504000 }, - { _MMIO(0x9888), 0x0e518000 }, - { _MMIO(0x9888), 0x00518000 }, - { _MMIO(0x9888), 0x02514000 }, - { _MMIO(0x9888), 0x0e521880 }, - { _MMIO(0x9888), 0x00521a80 }, - { _MMIO(0x9888), 0x02520033 }, - { _MMIO(0x9888), 0x0e534000 }, - { _MMIO(0x9888), 0x00534000 }, - { _MMIO(0x9888), 0x02531000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900800 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900062 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900c00 }, - { _MMIO(0x9888), 0x43900003 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, -}; - -static int -get_tdl_1_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_1; - lens[n] = ARRAY_SIZE(mux_config_tdl_1); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_tdl_2[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2744), 0x00800000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0x00800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x00800000 }, -}; - -static const struct i915_oa_reg flex_eu_config_tdl_2[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00010003 }, - { _MMIO(0xe658), 0x00012011 }, - { _MMIO(0xe758), 0x00015014 }, - { _MMIO(0xe45c), 0x00051050 }, - { _MMIO(0xe55c), 0x00053052 }, - { _MMIO(0xe65c), 0x00055054 }, -}; - -static const struct i915_oa_reg mux_config_tdl_2[] = { - { _MMIO(0x9888), 0x12124d60 }, - { _MMIO(0x9888), 0x12322e60 }, - { _MMIO(0x9888), 0x12524d60 }, - { _MMIO(0x9888), 0x022f3000 }, - { _MMIO(0x9888), 0x0a4c0014 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x0c0fe000 }, - { _MMIO(0x9888), 0x0e0f0097 }, - { _MMIO(0x9888), 0x082c8000 }, - { _MMIO(0x9888), 0x0a2c8000 }, - { _MMIO(0x9888), 0x002d8000 }, - { _MMIO(0x9888), 0x062d4000 }, - { _MMIO(0x9888), 0x0410c000 }, - { _MMIO(0x9888), 0x0411c000 }, - { _MMIO(0x9888), 0x04121fb7 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x04135000 }, - { _MMIO(0x9888), 0x00308000 }, - { _MMIO(0x9888), 0x06304000 }, - { _MMIO(0x9888), 0x00318000 }, - { _MMIO(0x9888), 0x06314000 }, - { _MMIO(0x9888), 0x00321b80 }, - { _MMIO(0x9888), 0x0632003f }, - { _MMIO(0x9888), 0x00334000 }, - { _MMIO(0x9888), 0x06331000 }, - { _MMIO(0x9888), 0x0250c000 }, - { _MMIO(0x9888), 0x0251c000 }, - { _MMIO(0x9888), 0x02521fb7 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x02535000 }, - { _MMIO(0x9888), 0x1190fc00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x51900000 }, - { _MMIO(0x9888), 0x41900800 }, - { _MMIO(0x9888), 0x43900063 }, - { _MMIO(0x9888), 0x53900000 }, - { _MMIO(0x9888), 0x45900040 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_tdl_2_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_tdl_2; - lens[n] = ARRAY_SIZE(mux_config_tdl_2); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_compute_extra[] = { -}; - -static const struct i915_oa_reg flex_eu_config_compute_extra[] = { -}; - -static const struct i915_oa_reg mux_config_compute_extra[] = { - { _MMIO(0x9888), 0x121203e0 }, - { _MMIO(0x9888), 0x123203e0 }, - { _MMIO(0x9888), 0x125203e0 }, - { _MMIO(0x9888), 0x129203e0 }, - { _MMIO(0x9888), 0x12b203e0 }, - { _MMIO(0x9888), 0x12d203e0 }, - { _MMIO(0x9888), 0x131203e0 }, - { _MMIO(0x9888), 0x133203e0 }, - { _MMIO(0x9888), 0x135203e0 }, - { _MMIO(0x9888), 0x1a4ef000 }, - { _MMIO(0x9888), 0x1c4e0003 }, - { _MMIO(0x9888), 0x024ec000 }, - { _MMIO(0x9888), 0x044ec000 }, - { _MMIO(0x9888), 0x064ec000 }, - { _MMIO(0x9888), 0x022f4000 }, - { _MMIO(0x9888), 0x0c4c02a0 }, - { _MMIO(0x9888), 0x084ca000 }, - { _MMIO(0x9888), 0x0a4c0042 }, - { _MMIO(0x9888), 0x0c0d8000 }, - { _MMIO(0x9888), 0x0e0da000 }, - { _MMIO(0x9888), 0x000d8000 }, - { _MMIO(0x9888), 0x020da000 }, - { _MMIO(0x9888), 0x040da000 }, - { _MMIO(0x9888), 0x060d2000 }, - { _MMIO(0x9888), 0x100f0150 }, - { _MMIO(0x9888), 0x0c0f5000 }, - { _MMIO(0x9888), 0x0e0f006d }, - { _MMIO(0x9888), 0x182c00a8 }, - { _MMIO(0x9888), 0x022c8000 }, - { _MMIO(0x9888), 0x042c8000 }, - { _MMIO(0x9888), 0x062c8000 }, - { _MMIO(0x9888), 0x0c2c8000 }, - { _MMIO(0x9888), 0x042d8000 }, - { _MMIO(0x9888), 0x06104000 }, - { _MMIO(0x9888), 0x06114000 }, - { _MMIO(0x9888), 0x06120033 }, - { _MMIO(0x9888), 0x00120000 }, - { _MMIO(0x9888), 0x06131000 }, - { _MMIO(0x9888), 0x04308000 }, - { _MMIO(0x9888), 0x04318000 }, - { _MMIO(0x9888), 0x04321980 }, - { _MMIO(0x9888), 0x00320000 }, - { _MMIO(0x9888), 0x04334000 }, - { _MMIO(0x9888), 0x04504000 }, - { _MMIO(0x9888), 0x04514000 }, - { _MMIO(0x9888), 0x04520033 }, - { _MMIO(0x9888), 0x00520000 }, - { _MMIO(0x9888), 0x04531000 }, - { _MMIO(0x9888), 0x1acef000 }, - { _MMIO(0x9888), 0x1cce0003 }, - { _MMIO(0x9888), 0x00af8000 }, - { _MMIO(0x9888), 0x0ccc02a0 }, - { _MMIO(0x9888), 0x0acc0001 }, - { _MMIO(0x9888), 0x0c8d8000 }, - { _MMIO(0x9888), 0x0e8da000 }, - { _MMIO(0x9888), 0x008d8000 }, - { _MMIO(0x9888), 0x028da000 }, - { _MMIO(0x9888), 0x108f0150 }, - { _MMIO(0x9888), 0x0c8fb000 }, - { _MMIO(0x9888), 0x0e8f0001 }, - { _MMIO(0x9888), 0x18ac00a8 }, - { _MMIO(0x9888), 0x06ac8000 }, - { _MMIO(0x9888), 0x02ad4000 }, - { _MMIO(0x9888), 0x02908000 }, - { _MMIO(0x9888), 0x02918000 }, - { _MMIO(0x9888), 0x02921980 }, - { _MMIO(0x9888), 0x00920000 }, - { _MMIO(0x9888), 0x02934000 }, - { _MMIO(0x9888), 0x02b04000 }, - { _MMIO(0x9888), 0x02b14000 }, - { _MMIO(0x9888), 0x02b20033 }, - { _MMIO(0x9888), 0x00b20000 }, - { _MMIO(0x9888), 0x02b31000 }, - { _MMIO(0x9888), 0x00d08000 }, - { _MMIO(0x9888), 0x00d18000 }, - { _MMIO(0x9888), 0x00d21980 }, - { _MMIO(0x9888), 0x00d34000 }, - { _MMIO(0x9888), 0x072f8000 }, - { _MMIO(0x9888), 0x0d4c0100 }, - { _MMIO(0x9888), 0x0d0d8000 }, - { _MMIO(0x9888), 0x0f0da000 }, - { _MMIO(0x9888), 0x110f01b0 }, - { _MMIO(0x9888), 0x192c0080 }, - { _MMIO(0x9888), 0x0f2d4000 }, - { _MMIO(0x9888), 0x0f108000 }, - { _MMIO(0x9888), 0x0f118000 }, - { _MMIO(0x9888), 0x0f121980 }, - { _MMIO(0x9888), 0x01120000 }, - { _MMIO(0x9888), 0x0f134000 }, - { _MMIO(0x9888), 0x0f304000 }, - { _MMIO(0x9888), 0x0f314000 }, - { _MMIO(0x9888), 0x0f320033 }, - { _MMIO(0x9888), 0x01320000 }, - { _MMIO(0x9888), 0x0f331000 }, - { _MMIO(0x9888), 0x0d508000 }, - { _MMIO(0x9888), 0x0d518000 }, - { _MMIO(0x9888), 0x0d521980 }, - { _MMIO(0x9888), 0x01520000 }, - { _MMIO(0x9888), 0x0d534000 }, - { _MMIO(0x9888), 0x1190ff80 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900c00 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, - { _MMIO(0x9888), 0x4b900002 }, - { _MMIO(0x9888), 0x59900000 }, - { _MMIO(0x9888), 0x51901100 }, - { _MMIO(0x9888), 0x41901000 }, - { _MMIO(0x9888), 0x43901423 }, - { _MMIO(0x9888), 0x53903331 }, - { _MMIO(0x9888), 0x45900044 }, -}; - -static int -get_compute_extra_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_compute_extra; - lens[n] = ARRAY_SIZE(mux_config_compute_extra); - n++; - - return n; -} - -static const struct i915_oa_reg b_counter_config_vme_pipe[] = { - { _MMIO(0x2740), 0x00000000 }, - { _MMIO(0x2710), 0x00000000 }, - { _MMIO(0x2714), 0xf0800000 }, - { _MMIO(0x2720), 0x00000000 }, - { _MMIO(0x2724), 0x30800000 }, - { _MMIO(0x2770), 0x00100030 }, - { _MMIO(0x2774), 0x0000fff9 }, - { _MMIO(0x2778), 0x00000002 }, - { _MMIO(0x277c), 0x0000fffc }, - { _MMIO(0x2780), 0x00000002 }, - { _MMIO(0x2784), 0x0000fff3 }, - { _MMIO(0x2788), 0x00100180 }, - { _MMIO(0x278c), 0x0000ffcf }, - { _MMIO(0x2790), 0x00000002 }, - { _MMIO(0x2794), 0x0000ffcf }, - { _MMIO(0x2798), 0x00000002 }, - { _MMIO(0x279c), 0x0000ff3f }, -}; - -static const struct i915_oa_reg flex_eu_config_vme_pipe[] = { - { _MMIO(0xe458), 0x00005004 }, - { _MMIO(0xe558), 0x00008003 }, -}; - -static const struct i915_oa_reg mux_config_vme_pipe[] = { - { _MMIO(0x9888), 0x141a5800 }, - { _MMIO(0x9888), 0x161a00c0 }, - { _MMIO(0x9888), 0x12180240 }, - { _MMIO(0x9888), 0x14180002 }, - { _MMIO(0x9888), 0x149a5800 }, - { _MMIO(0x9888), 0x169a00c0 }, - { _MMIO(0x9888), 0x12980240 }, - { _MMIO(0x9888), 0x14980002 }, - { _MMIO(0x9888), 0x1a4e3fc0 }, - { _MMIO(0x9888), 0x002f1000 }, - { _MMIO(0x9888), 0x022f8000 }, - { _MMIO(0x9888), 0x042f3000 }, - { _MMIO(0x9888), 0x004c4000 }, - { _MMIO(0x9888), 0x0a4c9500 }, - { _MMIO(0x9888), 0x0c4c002a }, - { _MMIO(0x9888), 0x000d2000 }, - { _MMIO(0x9888), 0x060d8000 }, - { _MMIO(0x9888), 0x080da000 }, - { _MMIO(0x9888), 0x0a0da000 }, - { _MMIO(0x9888), 0x0c0da000 }, - { _MMIO(0x9888), 0x0c0f0400 }, - { _MMIO(0x9888), 0x0e0f5500 }, - { _MMIO(0x9888), 0x100f0015 }, - { _MMIO(0x9888), 0x002c8000 }, - { _MMIO(0x9888), 0x0e2c8000 }, - { _MMIO(0x9888), 0x162caa00 }, - { _MMIO(0x9888), 0x182c000a }, - { _MMIO(0x9888), 0x04193000 }, - { _MMIO(0x9888), 0x081a28c1 }, - { _MMIO(0x9888), 0x001a0000 }, - { _MMIO(0x9888), 0x00133000 }, - { _MMIO(0x9888), 0x0613c000 }, - { _MMIO(0x9888), 0x0813f000 }, - { _MMIO(0x9888), 0x00172000 }, - { _MMIO(0x9888), 0x06178000 }, - { _MMIO(0x9888), 0x0817a000 }, - { _MMIO(0x9888), 0x00180037 }, - { _MMIO(0x9888), 0x06180940 }, - { _MMIO(0x9888), 0x08180000 }, - { _MMIO(0x9888), 0x02180000 }, - { _MMIO(0x9888), 0x04183000 }, - { _MMIO(0x9888), 0x04afc000 }, - { _MMIO(0x9888), 0x06af3000 }, - { _MMIO(0x9888), 0x0acc4000 }, - { _MMIO(0x9888), 0x0ccc0015 }, - { _MMIO(0x9888), 0x0a8da000 }, - { _MMIO(0x9888), 0x0c8da000 }, - { _MMIO(0x9888), 0x0e8f4000 }, - { _MMIO(0x9888), 0x108f0015 }, - { _MMIO(0x9888), 0x16aca000 }, - { _MMIO(0x9888), 0x18ac000a }, - { _MMIO(0x9888), 0x06993000 }, - { _MMIO(0x9888), 0x0c9a28c1 }, - { _MMIO(0x9888), 0x009a0000 }, - { _MMIO(0x9888), 0x0a93f000 }, - { _MMIO(0x9888), 0x0c93f000 }, - { _MMIO(0x9888), 0x0a97a000 }, - { _MMIO(0x9888), 0x0c97a000 }, - { _MMIO(0x9888), 0x0a980977 }, - { _MMIO(0x9888), 0x08980000 }, - { _MMIO(0x9888), 0x04980000 }, - { _MMIO(0x9888), 0x06983000 }, - { _MMIO(0x9888), 0x119000ff }, - { _MMIO(0x9888), 0x51900010 }, - { _MMIO(0x9888), 0x41900060 }, - { _MMIO(0x9888), 0x55900111 }, - { _MMIO(0x9888), 0x45900c00 }, - { _MMIO(0x9888), 0x47900821 }, - { _MMIO(0x9888), 0x57900000 }, - { _MMIO(0x9888), 0x49900002 }, - { _MMIO(0x9888), 0x37900000 }, - { _MMIO(0x9888), 0x33900000 }, -}; - -static int -get_vme_pipe_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_vme_pipe; - lens[n] = ARRAY_SIZE(mux_config_vme_pipe); - n++; - - return n; -} - static const struct i915_oa_reg b_counter_config_test_oa[] = { { _MMIO(0x2740), 0x00000000 }, { _MMIO(0x2744), 0x00800000 }, @@ -1984,6 +60,7 @@ static const struct i915_oa_reg flex_eu_config_test_oa[] = { }; static const struct i915_oa_reg mux_config_test_oa[] = { + { _MMIO(0x9840), 0x00000080 }, { _MMIO(0x9888), 0x11810000 }, { _MMIO(0x9888), 0x07810013 }, { _MMIO(0x9888), 0x1f810000 }, @@ -1998,1096 +75,35 @@ static const struct i915_oa_reg mux_config_test_oa[] = { { _MMIO(0x9888), 0x33900000 }, }; -static int -get_test_oa_mux_config(struct drm_i915_private *dev_priv, - const struct i915_oa_reg **regs, - int *lens) -{ - int n = 0; - - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1); - BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1); - - regs[n] = mux_config_test_oa; - lens[n] = ARRAY_SIZE(mux_config_test_oa); - n++; - - return n; -} - -int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv) -{ - dev_priv->perf.oa.n_mux_configs = 0; - dev_priv->perf.oa.b_counter_regs = NULL; - dev_priv->perf.oa.b_counter_regs_len = 0; - dev_priv->perf.oa.flex_regs = NULL; - dev_priv->perf.oa.flex_regs_len = 0; - - switch (dev_priv->perf.oa.metrics_set) { - case METRIC_SET_ID_RENDER_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_render_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_basic); - - return 0; - case METRIC_SET_ID_COMPUTE_BASIC: - dev_priv->perf.oa.n_mux_configs = - get_compute_basic_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_basic; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_basic); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_basic; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_basic); - - return 0; - case METRIC_SET_ID_RENDER_PIPE_PROFILE: - dev_priv->perf.oa.n_mux_configs = - get_render_pipe_profile_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_render_pipe_profile; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_render_pipe_profile); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_render_pipe_profile; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_render_pipe_profile); - - return 0; - case METRIC_SET_ID_MEMORY_READS: - dev_priv->perf.oa.n_mux_configs = - get_memory_reads_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_reads; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_reads); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_reads; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_reads); - - return 0; - case METRIC_SET_ID_MEMORY_WRITES: - dev_priv->perf.oa.n_mux_configs = - get_memory_writes_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_memory_writes; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_memory_writes); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_memory_writes; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_memory_writes); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTENDED: - dev_priv->perf.oa.n_mux_configs = - get_compute_extended_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extended; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extended); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extended; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extended); - - return 0; - case METRIC_SET_ID_COMPUTE_L3_CACHE: - dev_priv->perf.oa.n_mux_configs = - get_compute_l3_cache_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_l3_cache; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_l3_cache); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_l3_cache; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_l3_cache); - - return 0; - case METRIC_SET_ID_HDC_AND_SF: - dev_priv->perf.oa.n_mux_configs = - get_hdc_and_sf_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_hdc_and_sf; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_hdc_and_sf); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_hdc_and_sf; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_hdc_and_sf); - - return 0; - case METRIC_SET_ID_L3_1: - dev_priv->perf.oa.n_mux_configs = - get_l3_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_1); - - return 0; - case METRIC_SET_ID_L3_2: - dev_priv->perf.oa.n_mux_configs = - get_l3_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_2); - - return 0; - case METRIC_SET_ID_L3_3: - dev_priv->perf.oa.n_mux_configs = - get_l3_3_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_l3_3; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_l3_3); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_l3_3; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_l3_3); - - return 0; - case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: - dev_priv->perf.oa.n_mux_configs = - get_rasterizer_and_pixel_backend_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_rasterizer_and_pixel_backend; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); - - return 0; - case METRIC_SET_ID_SAMPLER: - dev_priv->perf.oa.n_mux_configs = - get_sampler_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_sampler; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_sampler); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_sampler; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_sampler); - - return 0; - case METRIC_SET_ID_TDL_1: - dev_priv->perf.oa.n_mux_configs = - get_tdl_1_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_1; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_1); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_1; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_1); - - return 0; - case METRIC_SET_ID_TDL_2: - dev_priv->perf.oa.n_mux_configs = - get_tdl_2_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_tdl_2; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_tdl_2); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_tdl_2; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_tdl_2); - - return 0; - case METRIC_SET_ID_COMPUTE_EXTRA: - dev_priv->perf.oa.n_mux_configs = - get_compute_extra_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_compute_extra; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_compute_extra); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_compute_extra; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_compute_extra); - - return 0; - case METRIC_SET_ID_VME_PIPE: - dev_priv->perf.oa.n_mux_configs = - get_vme_pipe_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_vme_pipe; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_vme_pipe); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_vme_pipe; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_vme_pipe); - - return 0; - case METRIC_SET_ID_TEST_OA: - dev_priv->perf.oa.n_mux_configs = - get_test_oa_mux_config(dev_priv, - dev_priv->perf.oa.mux_regs, - dev_priv->perf.oa.mux_regs_lens); - if (dev_priv->perf.oa.n_mux_configs == 0) { - DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n"); - - /* EINVAL because *_register_sysfs already checked this - * and so it wouldn't have been advertised to userspace and - * so shouldn't have been requested - */ - return -EINVAL; - } - - dev_priv->perf.oa.b_counter_regs = - b_counter_config_test_oa; - dev_priv->perf.oa.b_counter_regs_len = - ARRAY_SIZE(b_counter_config_test_oa); - - dev_priv->perf.oa.flex_regs = - flex_eu_config_test_oa; - dev_priv->perf.oa.flex_regs_len = - ARRAY_SIZE(flex_eu_config_test_oa); - - return 0; - default: - return -ENODEV; - } -} - -static ssize_t -show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); -} - -static struct device_attribute dev_attr_render_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_render_basic[] = { - &dev_attr_render_basic_id.attr, - NULL, -}; - -static struct attribute_group group_render_basic = { - .name = "bad77c24-cc64-480d-99bf-e7b740713800", - .attrs = attrs_render_basic, -}; - -static ssize_t -show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); -} - -static struct device_attribute dev_attr_compute_basic_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_basic_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_basic[] = { - &dev_attr_compute_basic_id.attr, - NULL, -}; - -static struct attribute_group group_compute_basic = { - .name = "7277228f-e7f3-4743-945a-6a2049d11377", - .attrs = attrs_compute_basic, -}; - -static ssize_t -show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); -} - -static struct device_attribute dev_attr_render_pipe_profile_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_render_pipe_profile_id, - .store = NULL, -}; - -static struct attribute *attrs_render_pipe_profile[] = { - &dev_attr_render_pipe_profile_id.attr, - NULL, -}; - -static struct attribute_group group_render_pipe_profile = { - .name = "463c668c-3f60-49b6-8f85-d995b635b3b2", - .attrs = attrs_render_pipe_profile, -}; - -static ssize_t -show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); -} - -static struct device_attribute dev_attr_memory_reads_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_reads_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_reads[] = { - &dev_attr_memory_reads_id.attr, - NULL, -}; - -static struct attribute_group group_memory_reads = { - .name = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8", - .attrs = attrs_memory_reads, -}; - -static ssize_t -show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); -} - -static struct device_attribute dev_attr_memory_writes_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_memory_writes_id, - .store = NULL, -}; - -static struct attribute *attrs_memory_writes[] = { - &dev_attr_memory_writes_id.attr, - NULL, -}; - -static struct attribute_group group_memory_writes = { - .name = "055f256d-4052-467c-8dec-6064a4806433", - .attrs = attrs_memory_writes, -}; - -static ssize_t -show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); -} - -static struct device_attribute dev_attr_compute_extended_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extended_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extended[] = { - &dev_attr_compute_extended_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extended = { - .name = "753972d4-87cd-4460-824d-754463ac5054", - .attrs = attrs_compute_extended, -}; - -static ssize_t -show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); -} - -static struct device_attribute dev_attr_compute_l3_cache_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_l3_cache_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_l3_cache[] = { - &dev_attr_compute_l3_cache_id.attr, - NULL, -}; - -static struct attribute_group group_compute_l3_cache = { - .name = "4e4392e9-8f73-457b-ab44-b49f7a0c733b", - .attrs = attrs_compute_l3_cache, -}; - -static ssize_t -show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); -} - -static struct device_attribute dev_attr_hdc_and_sf_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_hdc_and_sf_id, - .store = NULL, -}; - -static struct attribute *attrs_hdc_and_sf[] = { - &dev_attr_hdc_and_sf_id.attr, - NULL, -}; - -static struct attribute_group group_hdc_and_sf = { - .name = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805", - .attrs = attrs_hdc_and_sf, -}; - -static ssize_t -show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); -} - -static struct device_attribute dev_attr_l3_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_1_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_1[] = { - &dev_attr_l3_1_id.attr, - NULL, -}; - -static struct attribute_group group_l3_1 = { - .name = "d9e86d70-462b-462a-851e-fd63e8c13d63", - .attrs = attrs_l3_1, -}; - -static ssize_t -show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); -} - -static struct device_attribute dev_attr_l3_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_2_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_2[] = { - &dev_attr_l3_2_id.attr, - NULL, -}; - -static struct attribute_group group_l3_2 = { - .name = "52200424-6ee9-48b3-b7fa-0afcf1975e4d", - .attrs = attrs_l3_2, -}; - -static ssize_t -show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); -} - -static struct device_attribute dev_attr_l3_3_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_l3_3_id, - .store = NULL, -}; - -static struct attribute *attrs_l3_3[] = { - &dev_attr_l3_3_id.attr, - NULL, -}; - -static struct attribute_group group_l3_3 = { - .name = "1988315f-0a26-44df-acb0-df7ec86b1456", - .attrs = attrs_l3_3, -}; - -static ssize_t -show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); -} - -static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_rasterizer_and_pixel_backend_id, - .store = NULL, -}; - -static struct attribute *attrs_rasterizer_and_pixel_backend[] = { - &dev_attr_rasterizer_and_pixel_backend_id.attr, - NULL, -}; - -static struct attribute_group group_rasterizer_and_pixel_backend = { - .name = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d", - .attrs = attrs_rasterizer_and_pixel_backend, -}; - -static ssize_t -show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); -} - -static struct device_attribute dev_attr_sampler_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_sampler_id, - .store = NULL, -}; - -static struct attribute *attrs_sampler[] = { - &dev_attr_sampler_id.attr, - NULL, -}; - -static struct attribute_group group_sampler = { - .name = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b", - .attrs = attrs_sampler, -}; - -static ssize_t -show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); -} - -static struct device_attribute dev_attr_tdl_1_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_1_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_1[] = { - &dev_attr_tdl_1_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_1 = { - .name = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3", - .attrs = attrs_tdl_1, -}; - -static ssize_t -show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); -} - -static struct device_attribute dev_attr_tdl_2_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_tdl_2_id, - .store = NULL, -}; - -static struct attribute *attrs_tdl_2[] = { - &dev_attr_tdl_2_id.attr, - NULL, -}; - -static struct attribute_group group_tdl_2 = { - .name = "97875e21-6624-4aee-9191-682feb3eae21", - .attrs = attrs_tdl_2, -}; - -static ssize_t -show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA); -} - -static struct device_attribute dev_attr_compute_extra_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_compute_extra_id, - .store = NULL, -}; - -static struct attribute *attrs_compute_extra[] = { - &dev_attr_compute_extra_id.attr, - NULL, -}; - -static struct attribute_group group_compute_extra = { - .name = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd", - .attrs = attrs_compute_extra, -}; - -static ssize_t -show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf) -{ - return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE); -} - -static struct device_attribute dev_attr_vme_pipe_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_vme_pipe_id, - .store = NULL, -}; - -static struct attribute *attrs_vme_pipe[] = { - &dev_attr_vme_pipe_id.attr, - NULL, -}; - -static struct attribute_group group_vme_pipe = { - .name = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e", - .attrs = attrs_vme_pipe, -}; - static ssize_t show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA); + return sprintf(buf, "1\n"); } -static struct device_attribute dev_attr_test_oa_id = { - .attr = { .name = "id", .mode = 0444 }, - .show = show_test_oa_id, - .store = NULL, -}; - -static struct attribute *attrs_test_oa[] = { - &dev_attr_test_oa_id.attr, - NULL, -}; - -static struct attribute_group group_test_oa = { - .name = "882fa433-1f4a-4a67-a962-c741888fe5f5", - .attrs = attrs_test_oa, -}; - -int -i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv) +void +i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv) { - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; - int ret = 0; + strncpy(dev_priv->perf.oa.test_config.uuid, + "882fa433-1f4a-4a67-a962-c741888fe5f5", + UUID_STRING_LEN); + dev_priv->perf.oa.test_config.id = 1; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (ret) - goto error_render_basic; - } - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (ret) - goto error_compute_basic; - } - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (ret) - goto error_render_pipe_profile; - } - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (ret) - goto error_memory_reads; - } - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (ret) - goto error_memory_writes; - } - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (ret) - goto error_compute_extended; - } - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (ret) - goto error_compute_l3_cache; - } - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (ret) - goto error_hdc_and_sf; - } - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (ret) - goto error_l3_1; - } - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (ret) - goto error_l3_2; - } - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (ret) - goto error_l3_3; - } - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (ret) - goto error_rasterizer_and_pixel_backend; - } - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (ret) - goto error_sampler; - } - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (ret) - goto error_tdl_1; - } - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (ret) - goto error_tdl_2; - } - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (ret) - goto error_compute_extra; - } - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (ret) - goto error_vme_pipe; - } - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) { - ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa); - if (ret) - goto error_test_oa; - } + dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa; + dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa); - return 0; + dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa; + dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa); -error_test_oa: - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); -error_vme_pipe: - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); -error_compute_extra: - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); -error_tdl_2: - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); -error_tdl_1: - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); -error_sampler: - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); -error_rasterizer_and_pixel_backend: - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); -error_l3_3: - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); -error_l3_2: - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); -error_l3_1: - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); -error_hdc_and_sf: - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); -error_compute_l3_cache: - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); -error_compute_extended: - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); -error_memory_writes: - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); -error_memory_reads: - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); -error_render_pipe_profile: - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); -error_compute_basic: - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); -error_render_basic: - return ret; -} + dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa; + dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa); -void -i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv) -{ - const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)]; - int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)]; + dev_priv->perf.oa.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5"; + dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs; + + dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr; - if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); - if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); - if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); - if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); - if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); - if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); - if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); - if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); - if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); - if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); - if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); - if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); - if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); - if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); - if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); - if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra); - if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe); - if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) - sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa); + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id"; + dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444; + dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id; } diff --git a/drivers/gpu/drm/i915/i915_oa_sklgt4.h b/drivers/gpu/drm/i915/i915_oa_sklgt4.h index 1b718f15f62e..944fd525c8b1 100644 --- a/drivers/gpu/drm/i915/i915_oa_sklgt4.h +++ b/drivers/gpu/drm/i915/i915_oa_sklgt4.h @@ -29,12 +29,6 @@ #ifndef __I915_OA_SKLGT4_H__ #define __I915_OA_SKLGT4_H__ -extern int i915_oa_n_builtin_metric_sets_sklgt4; - -extern int i915_oa_select_metric_set_sklgt4(struct drm_i915_private *dev_priv); - -extern int i915_perf_register_sysfs_sklgt4(struct drm_i915_private *dev_priv); - -extern void i915_perf_unregister_sysfs_sklgt4(struct drm_i915_private *dev_priv); +extern void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv); #endif diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 88b9d3e6713a..8ab003dca113 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -63,9 +63,8 @@ struct i915_params i915 __read_mostly = { .huc_firmware_path = NULL, .enable_dp_mst = true, .inject_load_failure = 0, - .enable_dpcd_backlight = -1, + .enable_dpcd_backlight = false, .enable_gvt = false, - .enable_dbc = true, }; module_param_named(modeset, i915.modeset, int, 0400); @@ -119,6 +118,10 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type, module_param_named_unsafe(reset, i915.reset, int, 0600); MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); +module_param_named_unsafe(vbt_firmware, i915.vbt_firmware, charp, 0400); +MODULE_PARM_DESC(vbt_firmware, + "Load VBT from specified file under /lib/firmware"); + #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) module_param_named(error_capture, i915.error_capture, bool, 0600); MODULE_PARM_DESC(error_capture, @@ -247,15 +250,10 @@ MODULE_PARM_DESC(enable_dp_mst, module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); MODULE_PARM_DESC(inject_load_failure, "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); -module_param_named_unsafe(enable_dpcd_backlight, i915.enable_dpcd_backlight, int, 0600); +module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600); MODULE_PARM_DESC(enable_dpcd_backlight, - "Enable support for DPCD backlight control " - "(-1:auto (default), 0:force disable, 1:force enabled if supported"); + "Enable support for DPCD backlight control (default:false)"); module_param_named(enable_gvt, i915.enable_gvt, bool, 0400); MODULE_PARM_DESC(enable_gvt, "Enable support for Intel GVT-g graphics virtualization host support(default:false)"); - -module_param_named_unsafe(enable_dbc, i915.enable_dbc, bool, 0600); -MODULE_PARM_DESC(enable_dbc, - "Enable support for dynamic backlight control (default:true)"); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 057e203e6bda..ac844709c97e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -28,6 +28,7 @@ #include <linux/cache.h> /* for __read_mostly */ #define I915_PARAMS_FOR_EACH(func) \ + func(char *, vbt_firmware); \ func(int, modeset); \ func(int, panel_ignore_lid); \ func(int, semaphores); \ @@ -53,7 +54,6 @@ func(int, edp_vswing); \ func(int, reset); \ func(unsigned int, inject_load_failure); \ - func(int, enable_dpcd_backlight); \ /* leave bools at the end to not create holes */ \ func(bool, alpha_support); \ func(bool, enable_cmd_parser); \ @@ -67,8 +67,8 @@ func(bool, verbose_state_checks); \ func(bool, nuclear_pageflip); \ func(bool, enable_dp_mst); \ - func(bool, enable_gvt); \ - func(bool, enable_dbc) + func(bool, enable_dpcd_backlight); \ + func(bool, enable_gvt) #define MEMBER(T, member) T member struct i915_params { diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a1e6b696bcfa..09d97e0990b7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -398,6 +398,7 @@ static const struct intel_device_info intel_broxton_info = { GEN9_LP_FEATURES, .platform = INTEL_BROXTON, .ddb_size = 512, + .has_reset_engine = false, }; static const struct intel_device_info intel_geminilake_info = { diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index ed396f7b7dca..94185d610673 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -193,6 +193,7 @@ #include <linux/anon_inodes.h> #include <linux/sizes.h> +#include <linux/uuid.h> #include "i915_drv.h" #include "i915_oa_hsw.h" @@ -357,6 +358,54 @@ struct perf_open_properties { int oa_period_exponent; }; +static void free_oa_config(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + if (!PTR_ERR(oa_config->flex_regs)) + kfree(oa_config->flex_regs); + if (!PTR_ERR(oa_config->b_counter_regs)) + kfree(oa_config->b_counter_regs); + if (!PTR_ERR(oa_config->mux_regs)) + kfree(oa_config->mux_regs); + kfree(oa_config); +} + +static void put_oa_config(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + if (!atomic_dec_and_test(&oa_config->ref_count)) + return; + + free_oa_config(dev_priv, oa_config); +} + +static int get_oa_config(struct drm_i915_private *dev_priv, + int metrics_set, + struct i915_oa_config **out_config) +{ + int ret; + + if (metrics_set == 1) { + *out_config = &dev_priv->perf.oa.test_config; + atomic_inc(&dev_priv->perf.oa.test_config.ref_count); + return 0; + } + + ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (ret) + return ret; + + *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set); + if (!*out_config) + ret = -EINVAL; + else + atomic_inc(&(*out_config)->ref_count); + + mutex_unlock(&dev_priv->perf.metrics_lock); + + return ret; +} + static u32 gen8_oa_hw_tail_read(struct drm_i915_private *dev_priv) { return I915_READ(GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK; @@ -1246,10 +1295,12 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) BUG_ON(stream != dev_priv->perf.oa.exclusive_stream); /* - * Unset exclusive_stream first, it might be checked while - * disabling the metric set on gen8+. + * Unset exclusive_stream first, it will be checked while disabling + * the metric set on gen8+. */ + mutex_lock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.exclusive_stream = NULL; + mutex_unlock(&dev_priv->drm.struct_mutex); dev_priv->perf.oa.ops.disable_metric_set(dev_priv); @@ -1261,6 +1312,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) if (stream->ctx) oa_put_render_ctx_id(stream); + put_oa_config(dev_priv, stream->oa_config); + if (dev_priv->perf.oa.spurious_report_rs.missed) { DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n", dev_priv->perf.oa.spurious_report_rs.missed); @@ -1440,9 +1493,9 @@ unlock: static void config_oa_regs(struct drm_i915_private *dev_priv, const struct i915_oa_reg *regs, - int n_regs) + u32 n_regs) { - int i; + u32 i; for (i = 0; i < n_regs; i++) { const struct i915_oa_reg *reg = regs + i; @@ -1451,17 +1504,9 @@ static void config_oa_regs(struct drm_i915_private *dev_priv, } } -static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) +static int hsw_enable_metric_set(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { - int ret = i915_oa_select_metric_set_hsw(dev_priv); - int i; - - if (ret) - return ret; - - I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) | - GT_NOA_ENABLE)); - /* PRM: * * OA unit is using “crclk” for its functionality. When trunk @@ -1476,10 +1521,7 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | GEN6_CSUNIT_CLOCK_GATE_DISABLE)); - for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) { - config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i], - dev_priv->perf.oa.mux_regs_lens[i]); - } + config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); /* It apparently takes a fairly long time for a new MUX * configuration to be be applied after these register writes. @@ -1504,8 +1546,8 @@ static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) */ usleep_range(15000, 20000); - config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, - dev_priv->perf.oa.b_counter_regs_len); + config_oa_regs(dev_priv, oa_config->b_counter_regs, + oa_config->b_counter_regs_len); return 0; } @@ -1529,11 +1571,10 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv) * in the case that the OA unit has been disabled. */ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, - u32 *reg_state) + u32 *reg_state, + const struct i915_oa_config *oa_config) { struct drm_i915_private *dev_priv = ctx->i915; - const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; - int n_flex_regs = dev_priv->perf.oa.flex_regs_len; u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset; /* The MMIO offsets for Flex EU registers aren't contiguous */ @@ -1565,12 +1606,15 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, * will be an explicit 'No Event' we can select, but not yet... */ u32 value = 0; - int j; - for (j = 0; j < n_flex_regs; j++) { - if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) { - value = flex_regs[j].value; - break; + if (oa_config) { + u32 j; + + for (j = 0; j < oa_config->flex_regs_len; j++) { + if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { + value = oa_config->flex_regs[j].value; + break; + } } } @@ -1583,11 +1627,10 @@ static void gen8_update_reg_state_unlocked(struct i915_gem_context *ctx, * Same as gen8_update_reg_state_unlocked only through the batchbuffer. This * is only used by the kernel context. */ -static int gen8_emit_oa_config(struct drm_i915_gem_request *req) +static int gen8_emit_oa_config(struct drm_i915_gem_request *req, + const struct i915_oa_config *oa_config) { struct drm_i915_private *dev_priv = req->i915; - const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; - int n_flex_regs = dev_priv->perf.oa.flex_regs_len; /* The MMIO offsets for Flex EU registers aren't contiguous */ u32 flex_mmio[] = { i915_mmio_reg_offset(EU_PERF_CNTL0), @@ -1622,12 +1665,15 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) * yet... */ u32 value = 0; - int j; - for (j = 0; j < n_flex_regs; j++) { - if (i915_mmio_reg_offset(flex_regs[j].addr) == mmio) { - value = flex_regs[j].value; - break; + if (oa_config) { + u32 j; + + for (j = 0; j < oa_config->flex_regs_len; j++) { + if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) { + value = oa_config->flex_regs[j].value; + break; + } } } @@ -1641,7 +1687,8 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) return 0; } -static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv) +static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { struct intel_engine_cs *engine = dev_priv->engine[RCS]; struct i915_gem_timeline *timeline; @@ -1656,7 +1703,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr if (IS_ERR(req)) return PTR_ERR(req); - ret = gen8_emit_oa_config(req); + ret = gen8_emit_oa_config(req, oa_config); if (ret) { i915_add_request(req); return ret; @@ -1707,6 +1754,7 @@ static int gen8_switch_to_updated_kernel_context(struct drm_i915_private *dev_pr * Note: it's only the RCS/Render context that has any OA state. */ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config, bool interruptible) { struct i915_gem_context *ctx; @@ -1724,7 +1772,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, } /* Switch away from any user context. */ - ret = gen8_switch_to_updated_kernel_context(dev_priv); + ret = gen8_switch_to_updated_kernel_context(dev_priv, oa_config); if (ret) goto out; @@ -1763,7 +1811,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, ce->state->obj->mm.dirty = true; regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs); - gen8_update_reg_state_unlocked(ctx, regs); + gen8_update_reg_state_unlocked(ctx, regs, oa_config); i915_gem_object_unpin_map(ce->state->obj); } @@ -1774,13 +1822,10 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv, return ret; } -static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) +static int gen8_enable_metric_set(struct drm_i915_private *dev_priv, + const struct i915_oa_config *oa_config) { - int ret = dev_priv->perf.oa.ops.select_metric_set(dev_priv); - int i; - - if (ret) - return ret; + int ret; /* * We disable slice/unslice clock ratio change reports on SKL since @@ -1817,19 +1862,14 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) * to make sure all slices/subslices are ON before writing to NOA * registers. */ - ret = gen8_configure_all_contexts(dev_priv, true); + ret = gen8_configure_all_contexts(dev_priv, oa_config, true); if (ret) return ret; - I915_WRITE(GDT_CHICKEN_BITS, 0xA0); - for (i = 0; i < dev_priv->perf.oa.n_mux_configs; i++) { - config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs[i], - dev_priv->perf.oa.mux_regs_lens[i]); - } - I915_WRITE(GDT_CHICKEN_BITS, 0x80); + config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); - config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, - dev_priv->perf.oa.b_counter_regs_len); + config_oa_regs(dev_priv, oa_config->b_counter_regs, + oa_config->b_counter_regs_len); return 0; } @@ -1837,7 +1877,11 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv) static void gen8_disable_metric_set(struct drm_i915_private *dev_priv) { /* Reset all contexts' slices/subslices configurations. */ - gen8_configure_all_contexts(dev_priv, false); + gen8_configure_all_contexts(dev_priv, NULL, false); + + I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & + ~GT_NOA_ENABLE)); + } static void gen7_oa_enable(struct drm_i915_private *dev_priv) @@ -2011,11 +2055,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return -EBUSY; } - if (!props->metrics_set) { - DRM_DEBUG("OA metric set not specified\n"); - return -EINVAL; - } - if (!props->oa_format) { DRM_DEBUG("OA report format not specified\n"); return -EINVAL; @@ -2055,8 +2094,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, dev_priv->perf.oa.oa_buffer.format = dev_priv->perf.oa.oa_formats[props->oa_format].format; - dev_priv->perf.oa.metrics_set = props->metrics_set; - dev_priv->perf.oa.periodic = props->oa_periodic; if (dev_priv->perf.oa.periodic) dev_priv->perf.oa.period_exponent = props->oa_period_exponent; @@ -2067,6 +2104,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, return ret; } + ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config); + if (ret) + goto err_config; + /* PRM - observability performance counters: * * OACONTROL, performance counter enable, note: @@ -2086,22 +2127,39 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, if (ret) goto err_oa_buf_alloc; - ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv); + ret = dev_priv->perf.oa.ops.enable_metric_set(dev_priv, + stream->oa_config); if (ret) goto err_enable; stream->ops = &i915_oa_stream_ops; + /* Lock device for exclusive_stream access late because + * enable_metric_set() might lock as well on gen8+. + */ + ret = i915_mutex_lock_interruptible(&dev_priv->drm); + if (ret) + goto err_lock; + dev_priv->perf.oa.exclusive_stream = stream; + mutex_unlock(&dev_priv->drm.struct_mutex); + return 0; +err_lock: + dev_priv->perf.oa.ops.disable_metric_set(dev_priv); + err_enable: free_oa_buffer(dev_priv); err_oa_buf_alloc: + put_oa_config(dev_priv, stream->oa_config); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); intel_runtime_pm_put(dev_priv); + +err_config: if (stream->ctx) oa_put_render_ctx_id(stream); @@ -2112,15 +2170,14 @@ void i915_oa_init_reg_state(struct intel_engine_cs *engine, struct i915_gem_context *ctx, u32 *reg_state) { - struct drm_i915_private *dev_priv = engine->i915; + struct i915_perf_stream *stream; if (engine->id != RCS) return; - if (!dev_priv->perf.initialized) - return; - - gen8_update_reg_state_unlocked(ctx, reg_state); + stream = engine->i915->perf.oa.exclusive_stream; + if (stream) + gen8_update_reg_state_unlocked(ctx, reg_state, stream->oa_config); } /** @@ -2483,27 +2540,6 @@ static const struct file_operations fops = { }; -static struct i915_gem_context * -lookup_context(struct drm_i915_private *dev_priv, - struct drm_i915_file_private *file_priv, - u32 ctx_user_handle) -{ - struct i915_gem_context *ctx; - int ret; - - ret = i915_mutex_lock_interruptible(&dev_priv->drm); - if (ret) - return ERR_PTR(ret); - - ctx = i915_gem_context_lookup(file_priv, ctx_user_handle); - if (!IS_ERR(ctx)) - i915_gem_context_get(ctx); - - mutex_unlock(&dev_priv->drm.struct_mutex); - - return ctx; -} - /** * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD * @dev_priv: i915 device instance @@ -2545,12 +2581,11 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, u32 ctx_handle = props->ctx_handle; struct drm_i915_file_private *file_priv = file->driver_priv; - specific_ctx = lookup_context(dev_priv, file_priv, ctx_handle); - if (IS_ERR(specific_ctx)) { - ret = PTR_ERR(specific_ctx); - if (ret != -EINTR) - DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", - ctx_handle); + specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle); + if (!specific_ctx) { + DRM_DEBUG("Failed to look up context with ID %u for opening perf stream\n", + ctx_handle); + ret = -ENOENT; goto err; } } @@ -2665,7 +2700,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, struct perf_open_properties *props) { u64 __user *uprop = uprops; - int i; + u32 i; memset(props, 0, sizeof(struct perf_open_properties)); @@ -2712,8 +2747,7 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, props->sample_flags |= SAMPLE_OA_REPORT; break; case DRM_I915_PERF_PROP_OA_METRICS_SET: - if (value == 0 || - value > dev_priv->perf.oa.n_builtin_sets) { + if (value == 0) { DRM_DEBUG("Unknown OA metric set ID\n"); return -EINVAL; } @@ -2852,6 +2886,8 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data, */ void i915_perf_register(struct drm_i915_private *dev_priv) { + int ret; + if (!dev_priv->perf.initialized) return; @@ -2867,44 +2903,42 @@ void i915_perf_register(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) goto exit; + sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr); + if (IS_HASWELL(dev_priv)) { - if (i915_perf_register_sysfs_hsw(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_hsw(dev_priv); } else if (IS_BROADWELL(dev_priv)) { - if (i915_perf_register_sysfs_bdw(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_bdw(dev_priv); } else if (IS_CHERRYVIEW(dev_priv)) { - if (i915_perf_register_sysfs_chv(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_chv(dev_priv); } else if (IS_SKYLAKE(dev_priv)) { - if (IS_SKL_GT2(dev_priv)) { - if (i915_perf_register_sysfs_sklgt2(dev_priv)) - goto sysfs_error; - } else if (IS_SKL_GT3(dev_priv)) { - if (i915_perf_register_sysfs_sklgt3(dev_priv)) - goto sysfs_error; - } else if (IS_SKL_GT4(dev_priv)) { - if (i915_perf_register_sysfs_sklgt4(dev_priv)) - goto sysfs_error; - } else - goto sysfs_error; + if (IS_SKL_GT2(dev_priv)) + i915_perf_load_test_config_sklgt2(dev_priv); + else if (IS_SKL_GT3(dev_priv)) + i915_perf_load_test_config_sklgt3(dev_priv); + else if (IS_SKL_GT4(dev_priv)) + i915_perf_load_test_config_sklgt4(dev_priv); } else if (IS_BROXTON(dev_priv)) { - if (i915_perf_register_sysfs_bxt(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_bxt(dev_priv); } else if (IS_KABYLAKE(dev_priv)) { - if (IS_KBL_GT2(dev_priv)) { - if (i915_perf_register_sysfs_kblgt2(dev_priv)) - goto sysfs_error; - } else if (IS_KBL_GT3(dev_priv)) { - if (i915_perf_register_sysfs_kblgt3(dev_priv)) - goto sysfs_error; - } else - goto sysfs_error; + if (IS_KBL_GT2(dev_priv)) + i915_perf_load_test_config_kblgt2(dev_priv); + else if (IS_KBL_GT3(dev_priv)) + i915_perf_load_test_config_kblgt3(dev_priv); } else if (IS_GEMINILAKE(dev_priv)) { - if (i915_perf_register_sysfs_glk(dev_priv)) - goto sysfs_error; + i915_perf_load_test_config_glk(dev_priv); } + if (dev_priv->perf.oa.test_config.id == 0) + goto sysfs_error; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, + &dev_priv->perf.oa.test_config.sysfs_metric); + if (ret) + goto sysfs_error; + + atomic_set(&dev_priv->perf.oa.test_config.ref_count, 1); + goto exit; sysfs_error: @@ -2929,34 +2963,375 @@ void i915_perf_unregister(struct drm_i915_private *dev_priv) if (!dev_priv->perf.metrics_kobj) return; - if (IS_HASWELL(dev_priv)) - i915_perf_unregister_sysfs_hsw(dev_priv); - else if (IS_BROADWELL(dev_priv)) - i915_perf_unregister_sysfs_bdw(dev_priv); - else if (IS_CHERRYVIEW(dev_priv)) - i915_perf_unregister_sysfs_chv(dev_priv); - else if (IS_SKYLAKE(dev_priv)) { - if (IS_SKL_GT2(dev_priv)) - i915_perf_unregister_sysfs_sklgt2(dev_priv); - else if (IS_SKL_GT3(dev_priv)) - i915_perf_unregister_sysfs_sklgt3(dev_priv); - else if (IS_SKL_GT4(dev_priv)) - i915_perf_unregister_sysfs_sklgt4(dev_priv); - } else if (IS_BROXTON(dev_priv)) - i915_perf_unregister_sysfs_bxt(dev_priv); - else if (IS_KABYLAKE(dev_priv)) { - if (IS_KBL_GT2(dev_priv)) - i915_perf_unregister_sysfs_kblgt2(dev_priv); - else if (IS_KBL_GT3(dev_priv)) - i915_perf_unregister_sysfs_kblgt3(dev_priv); - } else if (IS_GEMINILAKE(dev_priv)) - i915_perf_unregister_sysfs_glk(dev_priv); - + sysfs_remove_group(dev_priv->perf.metrics_kobj, + &dev_priv->perf.oa.test_config.sysfs_metric); kobject_put(dev_priv->perf.metrics_kobj); dev_priv->perf.metrics_kobj = NULL; } +static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + static const i915_reg_t flex_eu_regs[] = { + EU_PERF_CNTL0, + EU_PERF_CNTL1, + EU_PERF_CNTL2, + EU_PERF_CNTL3, + EU_PERF_CNTL4, + EU_PERF_CNTL5, + EU_PERF_CNTL6, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) { + if (flex_eu_regs[i].reg == addr) + return true; + } + return false; +} + +static bool gen7_is_valid_b_counter_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return (addr >= OASTARTTRIG1.reg && addr <= OASTARTTRIG8.reg) || + (addr >= OAREPORTTRIG1.reg && addr <= OAREPORTTRIG8.reg) || + (addr >= OACEC0_0.reg && addr <= OACEC7_1.reg); +} + +static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return addr == HALF_SLICE_CHICKEN2.reg || + (addr >= MICRO_BP0_0.reg && addr <= NOA_WRITE.reg) || + (addr >= OA_PERFCNT1_LO.reg && addr <= OA_PERFCNT2_HI.reg) || + (addr >= OA_PERFMATRIX_LO.reg && addr <= OA_PERFMATRIX_HI.reg); +} + +static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + addr == WAIT_FOR_RC6_EXIT.reg || + (addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg); +} + +static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + (addr >= 0x25100 && addr <= 0x2FF90) || + addr == 0x9ec0; +} + +static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) +{ + return gen7_is_valid_mux_addr(dev_priv, addr) || + (addr >= 0x182300 && addr <= 0x1823A4); +} + +static uint32_t mask_reg_value(u32 reg, u32 val) +{ + /* HALF_SLICE_CHICKEN2 is programmed with a the + * WaDisableSTUnitPowerOptimization workaround. Make sure the value + * programmed by userspace doesn't change this. + */ + if (HALF_SLICE_CHICKEN2.reg == reg) + val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); + + /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function + * indicated by its name and a bunch of selection fields used by OA + * configs. + */ + if (WAIT_FOR_RC6_EXIT.reg == reg) + val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE); + + return val; +} + +static struct i915_oa_reg *alloc_oa_regs(struct drm_i915_private *dev_priv, + bool (*is_valid)(struct drm_i915_private *dev_priv, u32 addr), + u32 __user *regs, + u32 n_regs) +{ + struct i915_oa_reg *oa_regs; + int err; + u32 i; + + if (!n_regs) + return NULL; + + if (!access_ok(VERIFY_READ, regs, n_regs * sizeof(u32) * 2)) + return ERR_PTR(-EFAULT); + + /* No is_valid function means we're not allowing any register to be programmed. */ + GEM_BUG_ON(!is_valid); + if (!is_valid) + return ERR_PTR(-EINVAL); + + oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL); + if (!oa_regs) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < n_regs; i++) { + u32 addr, value; + + err = get_user(addr, regs); + if (err) + goto addr_err; + + if (!is_valid(dev_priv, addr)) { + DRM_DEBUG("Invalid oa_reg address: %X\n", addr); + err = -EINVAL; + goto addr_err; + } + + err = get_user(value, regs + 1); + if (err) + goto addr_err; + + oa_regs[i].addr = _MMIO(addr); + oa_regs[i].value = mask_reg_value(addr, value); + + regs += 2; + } + + return oa_regs; + +addr_err: + kfree(oa_regs); + return ERR_PTR(err); +} + +static ssize_t show_dynamic_id(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i915_oa_config *oa_config = + container_of(attr, typeof(*oa_config), sysfs_metric_id); + + return sprintf(buf, "%d\n", oa_config->id); +} + +static int create_dynamic_oa_sysfs_entry(struct drm_i915_private *dev_priv, + struct i915_oa_config *oa_config) +{ + sysfs_attr_init(&oa_config->sysfs_metric_id.attr); + oa_config->sysfs_metric_id.attr.name = "id"; + oa_config->sysfs_metric_id.attr.mode = S_IRUGO; + oa_config->sysfs_metric_id.show = show_dynamic_id; + oa_config->sysfs_metric_id.store = NULL; + + oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr; + oa_config->attrs[1] = NULL; + + oa_config->sysfs_metric.name = oa_config->uuid; + oa_config->sysfs_metric.attrs = oa_config->attrs; + + return sysfs_create_group(dev_priv->perf.metrics_kobj, + &oa_config->sysfs_metric); +} + +/** + * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config + * @dev: drm device + * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from + * userspace (unvalidated) + * @file: drm file + * + * Validates the submitted OA register to be saved into a new OA config that + * can then be used for programming the OA unit and its NOA network. + * + * Returns: A new allocated config number to be used with the perf open ioctl + * or a negative error code on failure. + */ +int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_perf_oa_config *args = data; + struct i915_oa_config *oa_config, *tmp; + int err, id; + + if (!dev_priv->perf.initialized) { + DRM_DEBUG("i915 perf interface not available for this system\n"); + return -ENOTSUPP; + } + + if (!dev_priv->perf.metrics_kobj) { + DRM_DEBUG("OA metrics weren't advertised via sysfs\n"); + return -EINVAL; + } + + if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { + DRM_DEBUG("Insufficient privileges to add i915 OA config\n"); + return -EACCES; + } + + if ((!args->mux_regs_ptr || !args->n_mux_regs) && + (!args->boolean_regs_ptr || !args->n_boolean_regs) && + (!args->flex_regs_ptr || !args->n_flex_regs)) { + DRM_DEBUG("No OA registers given\n"); + return -EINVAL; + } + + oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL); + if (!oa_config) { + DRM_DEBUG("Failed to allocate memory for the OA config\n"); + return -ENOMEM; + } + + atomic_set(&oa_config->ref_count, 1); + + if (!uuid_is_valid(args->uuid)) { + DRM_DEBUG("Invalid uuid format for OA config\n"); + err = -EINVAL; + goto reg_err; + } + + /* Last character in oa_config->uuid will be 0 because oa_config is + * kzalloc. + */ + memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid)); + + oa_config->mux_regs_len = args->n_mux_regs; + oa_config->mux_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_mux_reg, + u64_to_user_ptr(args->mux_regs_ptr), + args->n_mux_regs); + + if (IS_ERR(oa_config->mux_regs)) { + DRM_DEBUG("Failed to create OA config for mux_regs\n"); + err = PTR_ERR(oa_config->mux_regs); + goto reg_err; + } + + oa_config->b_counter_regs_len = args->n_boolean_regs; + oa_config->b_counter_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_b_counter_reg, + u64_to_user_ptr(args->boolean_regs_ptr), + args->n_boolean_regs); + + if (IS_ERR(oa_config->b_counter_regs)) { + DRM_DEBUG("Failed to create OA config for b_counter_regs\n"); + err = PTR_ERR(oa_config->b_counter_regs); + goto reg_err; + } + + if (INTEL_GEN(dev_priv) < 8) { + if (args->n_flex_regs != 0) { + err = -EINVAL; + goto reg_err; + } + } else { + oa_config->flex_regs_len = args->n_flex_regs; + oa_config->flex_regs = + alloc_oa_regs(dev_priv, + dev_priv->perf.oa.ops.is_valid_flex_reg, + u64_to_user_ptr(args->flex_regs_ptr), + args->n_flex_regs); + + if (IS_ERR(oa_config->flex_regs)) { + DRM_DEBUG("Failed to create OA config for flex_regs\n"); + err = PTR_ERR(oa_config->flex_regs); + goto reg_err; + } + } + + err = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (err) + goto reg_err; + + /* We shouldn't have too many configs, so this iteration shouldn't be + * too costly. + */ + idr_for_each_entry(&dev_priv->perf.metrics_idr, tmp, id) { + if (!strcmp(tmp->uuid, oa_config->uuid)) { + DRM_DEBUG("OA config already exists with this uuid\n"); + err = -EADDRINUSE; + goto sysfs_err; + } + } + + err = create_dynamic_oa_sysfs_entry(dev_priv, oa_config); + if (err) { + DRM_DEBUG("Failed to create sysfs entry for OA config\n"); + goto sysfs_err; + } + + /* Config id 0 is invalid, id 1 for kernel stored test config. */ + oa_config->id = idr_alloc(&dev_priv->perf.metrics_idr, + oa_config, 2, + 0, GFP_KERNEL); + if (oa_config->id < 0) { + DRM_DEBUG("Failed to create sysfs entry for OA config\n"); + err = oa_config->id; + goto sysfs_err; + } + + mutex_unlock(&dev_priv->perf.metrics_lock); + + return oa_config->id; + +sysfs_err: + mutex_unlock(&dev_priv->perf.metrics_lock); +reg_err: + put_oa_config(dev_priv, oa_config); + DRM_DEBUG("Failed to add new OA config\n"); + return err; +} + +/** + * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config + * @dev: drm device + * @data: ioctl data (pointer to u64 integer) copied from userspace + * @file: drm file + * + * Configs can be removed while being used, the will stop appearing in sysfs + * and their content will be freed when the stream using the config is closed. + * + * Returns: 0 on success or a negative error code on failure. + */ +int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u64 *arg = data; + struct i915_oa_config *oa_config; + int ret; + + if (!dev_priv->perf.initialized) { + DRM_DEBUG("i915 perf interface not available for this system\n"); + return -ENOTSUPP; + } + + if (i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { + DRM_DEBUG("Insufficient privileges to remove i915 OA config\n"); + return -EACCES; + } + + ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock); + if (ret) + goto lock_err; + + oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg); + if (!oa_config) { + DRM_DEBUG("Failed to remove unknown OA config\n"); + ret = -ENOENT; + goto config_err; + } + + GEM_BUG_ON(*arg != oa_config->id); + + sysfs_remove_group(dev_priv->perf.metrics_kobj, + &oa_config->sysfs_metric); + + idr_remove(&dev_priv->perf.metrics_idr, *arg); + put_oa_config(dev_priv, oa_config); + +config_err: + mutex_unlock(&dev_priv->perf.metrics_lock); +lock_err: + return ret; +} + static struct ctl_table oa_table[] = { { .procname = "perf_stream_paranoid", @@ -3010,9 +3385,14 @@ static struct ctl_table dev_root[] = { */ void i915_perf_init(struct drm_i915_private *dev_priv) { - dev_priv->perf.oa.n_builtin_sets = 0; + dev_priv->perf.oa.timestamp_frequency = 0; if (IS_HASWELL(dev_priv)) { + dev_priv->perf.oa.ops.is_valid_b_counter_reg = + gen7_is_valid_b_counter_addr; + dev_priv->perf.oa.ops.is_valid_mux_reg = + hsw_is_valid_mux_addr; + dev_priv->perf.oa.ops.is_valid_flex_reg = NULL; dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set; dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set; @@ -3025,9 +3405,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.oa_formats = hsw_oa_formats; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_hsw; } else if (i915.enable_execlists) { /* Note: that although we could theoretically also support the * legacy ringbuffer mode on BDW (and earlier iterations of @@ -3035,6 +3412,22 @@ void i915_perf_init(struct drm_i915_private *dev_priv) * worth the complexity to maintain now that BDW+ enable * execlist mode by default. */ + dev_priv->perf.oa.ops.is_valid_b_counter_reg = + gen7_is_valid_b_counter_addr; + dev_priv->perf.oa.ops.is_valid_mux_reg = + gen8_is_valid_mux_addr; + dev_priv->perf.oa.ops.is_valid_flex_reg = + gen8_is_valid_flex_addr; + + dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; + dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; + dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; + dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; + dev_priv->perf.oa.ops.read = gen8_oa_read; + dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; + + dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; if (IS_GEN8(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; @@ -3043,85 +3436,35 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency = 12500000; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25); - - if (IS_BROADWELL(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_bdw; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_bdw; - } else if (IS_CHERRYVIEW(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_chv; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_chv; + if (IS_CHERRYVIEW(dev_priv)) { + dev_priv->perf.oa.ops.is_valid_mux_reg = + chv_is_valid_mux_addr; } } else if (IS_GEN9(dev_priv)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; - dev_priv->perf.oa.timestamp_frequency = 12000000; - dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); - if (IS_SKL_GT2(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt2; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt2; - } else if (IS_SKL_GT3(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt3; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt3; - } else if (IS_SKL_GT4(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_sklgt4; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_sklgt4; - } else if (IS_BROXTON(dev_priv)) { + switch (dev_priv->info.platform) { + case INTEL_BROXTON: + case INTEL_GEMINILAKE: dev_priv->perf.oa.timestamp_frequency = 19200000; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_bxt; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_bxt; - } else if (IS_KBL_GT2(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_kblgt2; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_kblgt2; - } else if (IS_KBL_GT3(dev_priv)) { - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_kblgt3; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_kblgt3; - } else if (IS_GEMINILAKE(dev_priv)) { - dev_priv->perf.oa.timestamp_frequency = 19200000; - - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_glk; - dev_priv->perf.oa.ops.select_metric_set = - i915_oa_select_metric_set_glk; + break; + case INTEL_SKYLAKE: + case INTEL_KABYLAKE: + dev_priv->perf.oa.timestamp_frequency = 12000000; + break; + default: + /* Leave timestamp_frequency to 0 so we can + * detect unsupported platforms. + */ + break; } } - - if (dev_priv->perf.oa.n_builtin_sets) { - dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; - dev_priv->perf.oa.ops.enable_metric_set = - gen8_enable_metric_set; - dev_priv->perf.oa.ops.disable_metric_set = - gen8_disable_metric_set; - dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; - dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; - dev_priv->perf.oa.ops.read = gen8_oa_read; - dev_priv->perf.oa.ops.oa_hw_tail_read = - gen8_oa_hw_tail_read; - - dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; - } } - if (dev_priv->perf.oa.n_builtin_sets) { + if (dev_priv->perf.oa.timestamp_frequency) { hrtimer_init(&dev_priv->perf.oa.poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb; @@ -3135,10 +3478,23 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.timestamp_frequency / 2; dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); + mutex_init(&dev_priv->perf.metrics_lock); + idr_init(&dev_priv->perf.metrics_idr); + dev_priv->perf.initialized = true; } } +static int destroy_config(int id, void *p, void *data) +{ + struct drm_i915_private *dev_priv = data; + struct i915_oa_config *oa_config = p; + + put_oa_config(dev_priv, oa_config); + + return 0; +} + /** * i915_perf_fini - Counter part to i915_perf_init() * @dev_priv: i915 device instance @@ -3148,6 +3504,9 @@ void i915_perf_fini(struct drm_i915_private *dev_priv) if (!dev_priv->perf.initialized) return; + idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv); + idr_destroy(&dev_priv->perf.metrics_idr); + unregister_sysctl_table(dev_priv->perf.sysctl_header); memset(&dev_priv->perf.oa.ops, 0, sizeof(dev_priv->perf.oa.ops)); diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 2cfe96d3e5d1..0679a58cdbae 100644 --- a/drivers/gpu/drm/i915/i915_pvinfo.h +++ b/drivers/gpu/drm/i915/i915_pvinfo.h @@ -49,12 +49,18 @@ enum vgt_g2v_type { VGT_G2V_MAX, }; +/* + * VGT capabilities type + */ +#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2) + struct vgt_if { u64 magic; /* VGT_MAGIC */ u16 version_major; u16 version_minor; u32 vgt_id; /* ID of vGT instance */ - u32 rsv1[12]; /* pad to offset 0x40 */ + u32 vgt_caps; /* VGT capabilities */ + u32 rsv1[11]; /* pad to offset 0x40 */ /* * Data structure to describe the balooning info of resources. * Each VM can only have one portion of continuous area for now. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c712d01f92ab..ed7cd9ee2c2a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -25,6 +25,97 @@ #ifndef _I915_REG_H_ #define _I915_REG_H_ +/** + * DOC: The i915 register macro definition style guide + * + * Follow the style described here for new macros, and while changing existing + * macros. Do **not** mass change existing definitions just to update the style. + * + * Layout + * '''''' + * + * Keep helper macros near the top. For example, _PIPE() and friends. + * + * Prefix macros that generally should not be used outside of this file with + * underscore '_'. For example, _PIPE() and friends, single instances of + * registers that are defined solely for the use by function-like macros. + * + * Avoid using the underscore prefixed macros outside of this file. There are + * exceptions, but keep them to a minimum. + * + * There are two basic types of register definitions: Single registers and + * register groups. Register groups are registers which have two or more + * instances, for example one per pipe, port, transcoder, etc. Register groups + * should be defined using function-like macros. + * + * For single registers, define the register offset first, followed by register + * contents. + * + * For register groups, define the register instance offsets first, prefixed + * with underscore, followed by a function-like macro choosing the right + * instance based on the parameter, followed by register contents. + * + * Define the register contents (i.e. bit and bit field macros) from most + * significant to least significant bit. Indent the register content macros + * using two extra spaces between ``#define`` and the macro name. + * + * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field + * contents so that they are already shifted in place, and can be directly + * OR'd. For convenience, function-like macros may be used to define bit fields, + * but do note that the macros may be needed to read as well as write the + * register contents. + * + * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in + * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix + * to the name. + * + * Group the register and its contents together without blank lines, separate + * from other registers and their contents with one blank line. + * + * Indent macro values from macro names using TABs. Align values vertically. Use + * braces in macro values as needed to avoid unintended precedence after macro + * substitution. Use spaces in macro values according to kernel coding + * style. Use lower case in hexadecimal values. + * + * Naming + * '''''' + * + * Try to name registers according to the specs. If the register name changes in + * the specs from platform to another, stick to the original name. + * + * Try to re-use existing register macro definitions. Only add new macros for + * new register offsets, or when the register contents have changed enough to + * warrant a full redefinition. + * + * When a register macro changes for a new platform, prefix the new macro using + * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The + * prefix signifies the start platform/generation using the register. + * + * When a bit (field) macro changes or gets added for a new platform, while + * retaining the existing register macro, add a platform acronym or generation + * suffix to the name. For example, ``_SKL`` or ``_GEN8``. + * + * Examples + * '''''''' + * + * (Note that the values in the example are indented using spaces instead of + * TABs to avoid misalignment in generated documentation. Use TABs in the + * definitions.):: + * + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf001 + * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) + * #define FOO_ENABLE (1 << 31) + * #define FOO_MODE_MASK (0xf << 16) + * #define FOO_MODE_SHIFT 16 + * #define FOO_MODE_BAR (0 << 16) + * #define FOO_MODE_BAZ (1 << 16) + * #define FOO_MODE_QUX_SNB (2 << 16) + * + * #define BAR _MMIO(0xb000) + * #define GEN8_BAR _MMIO(0xb888) + */ + typedef struct { uint32_t reg; } i915_reg_t; @@ -229,6 +320,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN8_RPCS_EU_MIN_SHIFT 0 #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) +#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) +/* HSW only */ +#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 +#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) +#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) +/* HSW+ */ +#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) +#define HSW_RCS_CONTEXT_ENABLE (1 << 7) +#define HSW_RCS_INHIBIT (1 << 8) +/* Gen8 */ +#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) +#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 +#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) +#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) +#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 +#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) +#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 +#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) +#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) + #define GAM_ECOCHK _MMIO(0x4090) #define BDW_DISABLE_HDC_INVALIDATION (1<<25) #define ECOCHK_SNB_BIT (1<<10) @@ -729,119 +842,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define EU_PERF_CNTL5 _MMIO(0xe55c) #define EU_PERF_CNTL6 _MMIO(0xe65c) -#define GDT_CHICKEN_BITS _MMIO(0x9840) -#define GT_NOA_ENABLE 0x00000080 - /* * OA Boolean state */ -#define OAREPORTTRIG1 _MMIO(0x2740) -#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ - -#define OAREPORTTRIG2 _MMIO(0x2744) -#define OAREPORTTRIG2_INVERT_A_0 (1<<0) -#define OAREPORTTRIG2_INVERT_A_1 (1<<1) -#define OAREPORTTRIG2_INVERT_A_2 (1<<2) -#define OAREPORTTRIG2_INVERT_A_3 (1<<3) -#define OAREPORTTRIG2_INVERT_A_4 (1<<4) -#define OAREPORTTRIG2_INVERT_A_5 (1<<5) -#define OAREPORTTRIG2_INVERT_A_6 (1<<6) -#define OAREPORTTRIG2_INVERT_A_7 (1<<7) -#define OAREPORTTRIG2_INVERT_A_8 (1<<8) -#define OAREPORTTRIG2_INVERT_A_9 (1<<9) -#define OAREPORTTRIG2_INVERT_A_10 (1<<10) -#define OAREPORTTRIG2_INVERT_A_11 (1<<11) -#define OAREPORTTRIG2_INVERT_A_12 (1<<12) -#define OAREPORTTRIG2_INVERT_A_13 (1<<13) -#define OAREPORTTRIG2_INVERT_A_14 (1<<14) -#define OAREPORTTRIG2_INVERT_A_15 (1<<15) -#define OAREPORTTRIG2_INVERT_B_0 (1<<16) -#define OAREPORTTRIG2_INVERT_B_1 (1<<17) -#define OAREPORTTRIG2_INVERT_B_2 (1<<18) -#define OAREPORTTRIG2_INVERT_B_3 (1<<19) -#define OAREPORTTRIG2_INVERT_C_0 (1<<20) -#define OAREPORTTRIG2_INVERT_C_1 (1<<21) -#define OAREPORTTRIG2_INVERT_D_0 (1<<22) -#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) -#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) - -#define OAREPORTTRIG3 _MMIO(0x2748) -#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG4 _MMIO(0x274c) -#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 - -#define OAREPORTTRIG5 _MMIO(0x2750) -#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff -#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ - -#define OAREPORTTRIG6 _MMIO(0x2754) -#define OAREPORTTRIG6_INVERT_A_0 (1<<0) -#define OAREPORTTRIG6_INVERT_A_1 (1<<1) -#define OAREPORTTRIG6_INVERT_A_2 (1<<2) -#define OAREPORTTRIG6_INVERT_A_3 (1<<3) -#define OAREPORTTRIG6_INVERT_A_4 (1<<4) -#define OAREPORTTRIG6_INVERT_A_5 (1<<5) -#define OAREPORTTRIG6_INVERT_A_6 (1<<6) -#define OAREPORTTRIG6_INVERT_A_7 (1<<7) -#define OAREPORTTRIG6_INVERT_A_8 (1<<8) -#define OAREPORTTRIG6_INVERT_A_9 (1<<9) -#define OAREPORTTRIG6_INVERT_A_10 (1<<10) -#define OAREPORTTRIG6_INVERT_A_11 (1<<11) -#define OAREPORTTRIG6_INVERT_A_12 (1<<12) -#define OAREPORTTRIG6_INVERT_A_13 (1<<13) -#define OAREPORTTRIG6_INVERT_A_14 (1<<14) -#define OAREPORTTRIG6_INVERT_A_15 (1<<15) -#define OAREPORTTRIG6_INVERT_B_0 (1<<16) -#define OAREPORTTRIG6_INVERT_B_1 (1<<17) -#define OAREPORTTRIG6_INVERT_B_2 (1<<18) -#define OAREPORTTRIG6_INVERT_B_3 (1<<19) -#define OAREPORTTRIG6_INVERT_C_0 (1<<20) -#define OAREPORTTRIG6_INVERT_C_1 (1<<21) -#define OAREPORTTRIG6_INVERT_D_0 (1<<22) -#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) -#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) - -#define OAREPORTTRIG7 _MMIO(0x2758) -#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 -#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 -#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 -#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 -#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 -#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 -#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 -#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 - -#define OAREPORTTRIG8 _MMIO(0x275c) -#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf -#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 -#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 -#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 -#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 -#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 -#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 -#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 -#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 - #define OASTARTTRIG1 _MMIO(0x2710) #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 #define OASTARTTRIG1_THRESHOLD_MASK 0xffff @@ -956,6 +960,112 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 #define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 +#define OAREPORTTRIG1 _MMIO(0x2740) +#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG2 _MMIO(0x2744) +#define OAREPORTTRIG2_INVERT_A_0 (1<<0) +#define OAREPORTTRIG2_INVERT_A_1 (1<<1) +#define OAREPORTTRIG2_INVERT_A_2 (1<<2) +#define OAREPORTTRIG2_INVERT_A_3 (1<<3) +#define OAREPORTTRIG2_INVERT_A_4 (1<<4) +#define OAREPORTTRIG2_INVERT_A_5 (1<<5) +#define OAREPORTTRIG2_INVERT_A_6 (1<<6) +#define OAREPORTTRIG2_INVERT_A_7 (1<<7) +#define OAREPORTTRIG2_INVERT_A_8 (1<<8) +#define OAREPORTTRIG2_INVERT_A_9 (1<<9) +#define OAREPORTTRIG2_INVERT_A_10 (1<<10) +#define OAREPORTTRIG2_INVERT_A_11 (1<<11) +#define OAREPORTTRIG2_INVERT_A_12 (1<<12) +#define OAREPORTTRIG2_INVERT_A_13 (1<<13) +#define OAREPORTTRIG2_INVERT_A_14 (1<<14) +#define OAREPORTTRIG2_INVERT_A_15 (1<<15) +#define OAREPORTTRIG2_INVERT_B_0 (1<<16) +#define OAREPORTTRIG2_INVERT_B_1 (1<<17) +#define OAREPORTTRIG2_INVERT_B_2 (1<<18) +#define OAREPORTTRIG2_INVERT_B_3 (1<<19) +#define OAREPORTTRIG2_INVERT_C_0 (1<<20) +#define OAREPORTTRIG2_INVERT_C_1 (1<<21) +#define OAREPORTTRIG2_INVERT_D_0 (1<<22) +#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG3 _MMIO(0x2748) +#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG4 _MMIO(0x274c) +#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OAREPORTTRIG5 _MMIO(0x2750) +#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG6 _MMIO(0x2754) +#define OAREPORTTRIG6_INVERT_A_0 (1<<0) +#define OAREPORTTRIG6_INVERT_A_1 (1<<1) +#define OAREPORTTRIG6_INVERT_A_2 (1<<2) +#define OAREPORTTRIG6_INVERT_A_3 (1<<3) +#define OAREPORTTRIG6_INVERT_A_4 (1<<4) +#define OAREPORTTRIG6_INVERT_A_5 (1<<5) +#define OAREPORTTRIG6_INVERT_A_6 (1<<6) +#define OAREPORTTRIG6_INVERT_A_7 (1<<7) +#define OAREPORTTRIG6_INVERT_A_8 (1<<8) +#define OAREPORTTRIG6_INVERT_A_9 (1<<9) +#define OAREPORTTRIG6_INVERT_A_10 (1<<10) +#define OAREPORTTRIG6_INVERT_A_11 (1<<11) +#define OAREPORTTRIG6_INVERT_A_12 (1<<12) +#define OAREPORTTRIG6_INVERT_A_13 (1<<13) +#define OAREPORTTRIG6_INVERT_A_14 (1<<14) +#define OAREPORTTRIG6_INVERT_A_15 (1<<15) +#define OAREPORTTRIG6_INVERT_B_0 (1<<16) +#define OAREPORTTRIG6_INVERT_B_1 (1<<17) +#define OAREPORTTRIG6_INVERT_B_2 (1<<18) +#define OAREPORTTRIG6_INVERT_B_3 (1<<19) +#define OAREPORTTRIG6_INVERT_C_0 (1<<20) +#define OAREPORTTRIG6_INVERT_C_1 (1<<21) +#define OAREPORTTRIG6_INVERT_D_0 (1<<22) +#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG7 _MMIO(0x2758) +#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG8 _MMIO(0x275c) +#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 + /* CECX_0 */ #define OACEC_COMPARE_LESS_OR_EQUAL 6 #define OACEC_COMPARE_NOT_EQUAL 5 @@ -994,6 +1104,51 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OACEC7_0 _MMIO(0x27a8) #define OACEC7_1 _MMIO(0x27ac) +/* OA perf counters */ +#define OA_PERFCNT1_LO _MMIO(0x91B8) +#define OA_PERFCNT1_HI _MMIO(0x91BC) +#define OA_PERFCNT2_LO _MMIO(0x91C0) +#define OA_PERFCNT2_HI _MMIO(0x91C4) + +#define OA_PERFMATRIX_LO _MMIO(0x91C8) +#define OA_PERFMATRIX_HI _MMIO(0x91CC) + +/* RPM unit config (Gen8+) */ +#define RPM_CONFIG0 _MMIO(0x0D00) +#define RPM_CONFIG1 _MMIO(0x0D04) + +/* RPC unit config (Gen8+) */ +#define RPM_CONFIG _MMIO(0x0D08) + +/* NOA (Gen8+) */ +#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) + +#define MICRO_BP0_0 _MMIO(0x9800) +#define MICRO_BP0_2 _MMIO(0x9804) +#define MICRO_BP0_1 _MMIO(0x9808) + +#define MICRO_BP1_0 _MMIO(0x980C) +#define MICRO_BP1_2 _MMIO(0x9810) +#define MICRO_BP1_1 _MMIO(0x9814) + +#define MICRO_BP2_0 _MMIO(0x9818) +#define MICRO_BP2_2 _MMIO(0x981C) +#define MICRO_BP2_1 _MMIO(0x9820) + +#define MICRO_BP3_0 _MMIO(0x9824) +#define MICRO_BP3_2 _MMIO(0x9828) +#define MICRO_BP3_1 _MMIO(0x982C) + +#define MICRO_BP_TRIGGER _MMIO(0x9830) +#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) +#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) +#define MICRO_BP_FIRED_ARMED _MMIO(0x983C) + +#define GDT_CHICKEN_BITS _MMIO(0x9840) +#define GT_NOA_ENABLE 0x00000080 + +#define NOA_DATA _MMIO(0x986C) +#define NOA_WRITE _MMIO(0x9888) #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 @@ -1063,9 +1218,26 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) -/* See the PUNIT HAS v0.8 for the below bits */ -enum punit_power_well { - /* These numbers are fixed and must match the position of the pw bits */ +/* + * i915_power_well_id: + * + * Platform specific IDs used to look up power wells and - except for custom + * power wells - to define request/status register flag bit positions. As such + * the set of IDs on a given platform must be unique and except for custom + * power wells their value must stay fixed. + */ +enum i915_power_well_id { + /* + * I830 + * - custom power well + */ + I830_DISP_PW_PIPES = 0, + + /* + * VLV/CHV + * - PUNIT_REG_PWRGT_CTRL (bit: id*2), + * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8) + */ PUNIT_POWER_WELL_RENDER = 0, PUNIT_POWER_WELL_MEDIA = 1, PUNIT_POWER_WELL_DISP2D = 3, @@ -1077,14 +1249,20 @@ enum punit_power_well { PUNIT_POWER_WELL_DPIO_RX0 = 10, PUNIT_POWER_WELL_DPIO_RX1 = 11, PUNIT_POWER_WELL_DPIO_CMN_D = 12, - - /* Not actual bit groups. Used as IDs for lookup_power_well() */ - PUNIT_POWER_WELL_ALWAYS_ON, -}; - -enum skl_disp_power_wells { - /* These numbers are fixed and must match the position of the pw bits */ - SKL_DISP_PW_MISC_IO, + /* - custom power well */ + CHV_DISP_PW_PIPE_A, /* 13 */ + + /* + * HSW/BDW + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) + */ + HSW_DISP_PW_GLOBAL = 15, + + /* + * GEN9+ + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) + */ + SKL_DISP_PW_MISC_IO = 0, SKL_DISP_PW_DDI_A_E, GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E, @@ -1103,18 +1281,20 @@ enum skl_disp_power_wells { SKL_DISP_PW_1 = 14, SKL_DISP_PW_2, - /* Not actual bit groups. Used as IDs for lookup_power_well() */ - SKL_DISP_PW_ALWAYS_ON, + /* - custom power wells */ SKL_DISP_PW_DC_OFF, - BXT_DPIO_CMN_A, BXT_DPIO_CMN_BC, - GLK_DPIO_CMN_C, + GLK_DPIO_CMN_C, /* 19 */ + + /* + * Multiple platforms. + * Must start following the highest ID of any platform. + * - custom power wells + */ + I915_DISP_PW_ALWAYS_ON = 20, }; -#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) -#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1)) - #define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_STATUS 0x61 #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) @@ -2156,6 +2336,7 @@ enum skl_disp_power_wells { #define DONE_REG _MMIO(0x40b0) #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) +#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + index*4) #define BSD_HWS_PGA_GEN7 _MMIO(0x04180) #define BLT_HWS_PGA_GEN7 _MMIO(0x04280) #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) @@ -3783,6 +3964,7 @@ enum { #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) #define EDP_PSR_ENABLE (1<<31) #define BDW_PSR_SINGLE_FRAME (1<<30) +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */ #define EDP_PSR_LINK_STANDBY (1<<27) #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) @@ -5227,6 +5409,9 @@ enum { #define _PIPE_MISC_A 0x70030 #define _PIPE_MISC_B 0x71030 +#define PIPEMISC_YUV420_ENABLE (1<<27) +#define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26) +#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11) #define PIPEMISC_DITHER_BPC_MASK (7<<5) #define PIPEMISC_DITHER_8_BPC (0<<5) #define PIPEMISC_DITHER_10_BPC (1<<5) @@ -6106,6 +6291,10 @@ enum { #define _PLANE_KEYMSK_2_A 0x70298 #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0 +#define _PLANE_AUX_DIST_1_A 0x701c0 +#define _PLANE_AUX_DIST_2_A 0x702c0 +#define _PLANE_AUX_OFFSET_1_A 0x701c4 +#define _PLANE_AUX_OFFSET_2_A 0x702c4 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ @@ -6212,6 +6401,24 @@ enum { #define PLANE_NV12_BUF_CFG(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define _PLANE_AUX_DIST_1_B 0x711c0 +#define _PLANE_AUX_DIST_2_B 0x712c0 +#define _PLANE_AUX_DIST_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) +#define _PLANE_AUX_DIST_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) +#define PLANE_AUX_DIST(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) + +#define _PLANE_AUX_OFFSET_1_B 0x711c4 +#define _PLANE_AUX_OFFSET_2_B 0x712c4 +#define _PLANE_AUX_OFFSET_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) +#define _PLANE_AUX_OFFSET_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) +#define PLANE_AUX_OFFSET(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) + #define _PLANE_COLOR_CTL_1_B 0x711CC #define _PLANE_COLOR_CTL_2_B 0x712CC #define _PLANE_COLOR_CTL_3_B 0x713CC @@ -6695,6 +6902,7 @@ enum { # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) #define CHICKEN_PAR1_1 _MMIO(0x42080) +#define SKL_RC_HASH_OUTSIDE (1 << 15) #define DPA_MASK_VBLANK_SRD (1 << 15) #define FORCE_ARB_IDLE_PLANES (1 << 14) #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) @@ -6703,12 +6911,10 @@ enum { #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) #define CHICKEN_MISC_2 _MMIO(0x42084) -#define GLK_CL0_PWR_DOWN (1 << 10) -#define GLK_CL1_PWR_DOWN (1 << 11) +#define CNL_COMP_PWR_DOWN (1 << 23) #define GLK_CL2_PWR_DOWN (1 << 12) - -#define CHICKEN_MISC_2 _MMIO(0x42084) -#define COMP_PWR_DOWN (1 << 23) +#define GLK_CL1_PWR_DOWN (1 << 11) +#define GLK_CL0_PWR_DOWN (1 << 10) #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 @@ -7984,12 +8190,31 @@ enum { #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) /* HSW Power Wells */ -#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ -#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ -#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ -#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ -#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) -#define HSW_PWR_WELL_STATE_ENABLED (1<<30) +#define _HSW_PWR_WELL_CTL1 0x45400 +#define _HSW_PWR_WELL_CTL2 0x45404 +#define _HSW_PWR_WELL_CTL3 0x45408 +#define _HSW_PWR_WELL_CTL4 0x4540C + +/* + * Each power well control register contains up to 16 (request, status) HW + * flag tuples. The register index and HW flag shift is determined by the + * power well ID (see i915_power_well_id). There are 4 possible sources of + * power well requests each source having its own set of control registers: + * BIOS, DRIVER, KVMR, DEBUG. + */ +#define _HSW_PW_REG_IDX(pw) ((pw) >> 4) +#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) +/* TODO: Add all PWR_WELL_CTL registers below for new platforms */ +#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL1)) +#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL2)) +#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) +#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL4)) + +#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) +#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) @@ -7997,11 +8222,17 @@ enum { #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) /* SKL Fuse Status */ +enum skl_power_gate { + SKL_PG0, + SKL_PG1, + SKL_PG2, +}; + #define SKL_FUSE_STATUS _MMIO(0x42000) -#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) -#define SKL_FUSE_PG0_DIST_STATUS (1<<27) -#define SKL_FUSE_PG1_DIST_STATUS (1<<26) -#define SKL_FUSE_PG2_DIST_STATUS (1<<25) +#define SKL_FUSE_DOWNLOAD_STATUS (1<<31) +/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */ +#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1) +#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 diff --git a/drivers/gpu/drm/i915/i915_selftest.h b/drivers/gpu/drm/i915/i915_selftest.h index 9d7d86f1733d..78e1a1b168ff 100644 --- a/drivers/gpu/drm/i915/i915_selftest.h +++ b/drivers/gpu/drm/i915/i915_selftest.h @@ -101,6 +101,4 @@ bool __igt_timeout(unsigned long timeout, const char *fmt, ...); #define igt_timeout(t, fmt, ...) \ __igt_timeout((t), KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) -#define igt_can_mi_store_dword_imm(D) (INTEL_GEN(D) > 2) - #endif /* !__I915_SELFTEST_H__ */ diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 7fcf00622c4c..d61c8727f756 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -220,7 +220,7 @@ out: return ret; } -static struct bin_attribute dpf_attrs = { +static const struct bin_attribute dpf_attrs = { .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, .read = i915_l3_read, @@ -229,7 +229,7 @@ static struct bin_attribute dpf_attrs = { .private = (void *)0 }; -static struct bin_attribute dpf_attrs_1 = { +static const struct bin_attribute dpf_attrs_1 = { .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, .read = i915_l3_read, @@ -532,7 +532,7 @@ static ssize_t error_state_write(struct file *file, struct kobject *kobj, return count; } -static struct bin_attribute error_state_attr = { +static const struct bin_attribute error_state_attr = { .attr.name = "error", .attr.mode = S_IRUSR | S_IWUSR, .size = 0, diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index cf7a958e4d3c..5fe9f3f39467 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -75,10 +75,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv) return; } + dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps)); + dev_priv->vgpu.active = true; DRM_INFO("Virtual GPU for Intel GVT-g detected.\n"); } +bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv) +{ + return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT; +} + struct _balloon_info_ { /* * There are up to 2 regions per mappable/unmappable graphic diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 3c3b2d24e830..b72bd2956b70 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h @@ -27,6 +27,9 @@ #include "i915_pvinfo.h" void i915_check_vgpu(struct drm_i915_private *dev_priv); + +bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv); + int intel_vgt_balloon(struct drm_i915_private *dev_priv); void intel_vgt_deballoon(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 958be0a95960..02d1a5eacb00 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -597,33 +597,11 @@ static void i915_vma_destroy(struct i915_vma *vma) kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); } -void i915_vma_unlink_ctx(struct i915_vma *vma) -{ - struct i915_gem_context *ctx = vma->ctx; - - if (ctx->vma_lut.ht_size & I915_CTX_RESIZE_IN_PROGRESS) { - cancel_work_sync(&ctx->vma_lut.resize); - ctx->vma_lut.ht_size &= ~I915_CTX_RESIZE_IN_PROGRESS; - } - - __hlist_del(&vma->ctx_node); - ctx->vma_lut.ht_count--; - - if (i915_vma_is_ggtt(vma)) - vma->obj->vma_hashed = NULL; - vma->ctx = NULL; - - i915_vma_put(vma); -} - void i915_vma_close(struct i915_vma *vma) { GEM_BUG_ON(i915_vma_is_closed(vma)); vma->flags |= I915_VMA_CLOSED; - if (vma->ctx) - i915_vma_unlink_ctx(vma); - list_del(&vma->obj_link); rb_erase(&vma->obj_node, &vma->obj->vma_tree); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 20cf272c97b1..1fd61e88cfd0 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -112,13 +112,9 @@ struct i915_vma { /** * Used for performing relocations during execbuffer insertion. */ - struct drm_i915_gem_exec_object2 *exec_entry; + unsigned int *exec_flags; struct hlist_node exec_node; u32 exec_handle; - - struct i915_gem_context *ctx; - struct hlist_node ctx_node; - u32 ctx_handle; }; struct i915_vma * diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 82b144cdfa1d..183e87e8ea31 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -1120,8 +1120,8 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; uint8_t aux_channel, ddc_pin; /* Each DDI port can have more than one value on the "DVO Port" field, - * so look for all the possible values for each port and abort if more - * than one is found. */ + * so look for all the possible values for each port. + */ int dvo_ports[][3] = { {DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, {DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, @@ -1130,7 +1130,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, {DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, }; - /* Find the child device to use, abort if more than one found. */ + /* + * Find the first child device to reference the port, report if more + * than one found. + */ for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { it = dev_priv->vbt.child_dev + i; @@ -1140,11 +1143,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, if (it->common.dvo_port == dvo_ports[port][j]) { if (child) { - DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n", + DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", port_name(port)); - return; + } else { + child = it; } - child = it; } } } diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 1813d84989c9..8e4e829682b9 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -41,6 +41,22 @@ #define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256) +/* Post offset values for RGB->YCBCR conversion */ +#define POSTOFF_RGB_TO_YUV_HI 0x800 +#define POSTOFF_RGB_TO_YUV_ME 0x100 +#define POSTOFF_RGB_TO_YUV_LO 0x800 + +/* + * These values are direct register values specified in the Bspec, + * for RGB->YUV conversion matrix (colorspace BT709) + */ +#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 +#define CSC_RGB_TO_YUV_BU 0x37e80000 +#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 +#define CSC_RGB_TO_YUV_BY 0xb5280000 +#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 +#define CSC_RGB_TO_YUV_BV 0x1e080000 + /* * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point * format). This macro takes the coefficient we want transformed and the @@ -91,6 +107,30 @@ static void ctm_mult_by_limited(uint64_t *result, int64_t *input) } } +void i9xx_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc) +{ + int pipe = intel_crtc->pipe; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + + I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); + I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); + I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); + + I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); + I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); + + I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); + I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); + + I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); + I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); + + I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI); + I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME); + I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO); + I915_WRITE(PIPE_CSC_MODE(pipe), 0); +} + /* Set up the pipe CSC unit. */ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) { @@ -101,7 +141,10 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) uint16_t coeffs[9] = { 0, }; struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state); - if (crtc_state->ctm) { + if (intel_crtc_state->ycbcr420) { + i9xx_load_ycbcr_conversion_matrix(intel_crtc); + return; + } else if (crtc_state->ctm) { struct drm_color_ctm *ctm = (struct drm_color_ctm *)crtc_state->ctm->data; uint64_t input[9] = { 0, }; diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f4fbb396054b..4b4fd1f8110b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1174,6 +1174,9 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) else dotclock = pipe_config->port_clock; + if (pipe_config->ycbcr420) + dotclock *= 2; + if (pipe_config->pixel_multiplier) dotclock /= pipe_config->pixel_multiplier; @@ -1873,7 +1876,7 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, if (dev_priv->vbt.edp.low_vswing) { if (voltage == VOLTAGE_INFO_0_85V) { *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); - return cnl_ddi_translations_dp_0_85V; + return cnl_ddi_translations_edp_0_85V; } else if (voltage == VOLTAGE_INFO_0_95V) { *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); return cnl_ddi_translations_edp_0_95V; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f47ab0ef14bb..0e93ec201fe3 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -49,11 +49,6 @@ #include <linux/dma_remapping.h> #include <linux/reservation.h> -static bool is_mmio_work(struct intel_flip_work *work) -{ - return work->mmio_work.func; -} - /* Primary plane formats for gen <= 3 */ static const uint32_t i8xx_primary_formats[] = { DRM_FORMAT_C8, @@ -72,6 +67,12 @@ static const uint32_t i965_primary_formats[] = { DRM_FORMAT_XBGR2101010, }; +static const uint64_t i9xx_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t skl_primary_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, @@ -87,11 +88,34 @@ static const uint32_t skl_primary_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_format_modifiers_noccs[] = { + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static const uint64_t skl_format_modifiers_ccs[] = { + I915_FORMAT_MOD_Yf_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + /* Cursor formats */ static const uint32_t intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; +static const uint64_t cursor_format_modifiers[] = { + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static void i9xx_crtc_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); static void ironlake_pch_clock_get(struct intel_crtc *crtc, @@ -1777,7 +1801,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); + assert_fdi_rx_enabled(dev_priv, PIPE_A); /* Workaround: set timing override bit. */ val = I915_READ(TRANS_CHICKEN2(PIPE_A)); @@ -1853,16 +1877,16 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); } -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); WARN_ON(!crtc->config->has_pch_encoder); if (HAS_PCH_LPT(dev_priv)) - return TRANSCODER_A; + return PIPE_A; else - return (enum transcoder) crtc->pipe; + return crtc->pipe; } /** @@ -1901,7 +1925,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) if (crtc->config->has_pch_encoder) { /* if driving the PCH, we need FDI enabled */ assert_fdi_rx_pll_enabled(dev_priv, - (enum pipe) intel_crtc_pch_transcoder(crtc)); + intel_crtc_pch_transcoder(crtc)); assert_fdi_tx_pll_enabled(dev_priv, (enum pipe) cpu_transcoder); } @@ -1999,11 +2023,19 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) return 128; else return 512; + case I915_FORMAT_MOD_Y_TILED_CCS: + if (plane == 1) + return 128; + /* fall through */ case I915_FORMAT_MOD_Y_TILED: if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; else return 512; + case I915_FORMAT_MOD_Yf_TILED_CCS: + if (plane == 1) + return 128; + /* fall through */ case I915_FORMAT_MOD_Yf_TILED: switch (cpp) { case 1: @@ -2110,7 +2142,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, struct drm_i915_private *dev_priv = to_i915(fb->dev); /* AUX_DIST needs only 4K alignment */ - if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) + if (plane == 1) return 4096; switch (fb->modifier) { @@ -2120,6 +2152,8 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, if (INTEL_GEN(dev_priv) >= 9) return 256 * 1024; return 0; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: return 1 * 1024 * 1024; @@ -2162,6 +2196,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) */ intel_runtime_pm_get(dev_priv); + atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); if (IS_ERR(vma)) goto err; @@ -2189,6 +2225,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) i915_vma_get(vma); err: + atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + intel_runtime_pm_put(dev_priv); return vma; } @@ -2427,12 +2465,48 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) case I915_FORMAT_MOD_X_TILED: return I915_TILING_X; case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: return I915_TILING_Y; default: return I915_TILING_NONE; } } +static const struct drm_format_info ccs_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, +}; + +static const struct drm_format_info * +lookup_format_info(const struct drm_format_info formats[], + int num_formats, u32 format) +{ + int i; + + for (i = 0; i < num_formats; i++) { + if (formats[i].format == format) + return &formats[i]; + } + + return NULL; +} + +static const struct drm_format_info * +intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + switch (cmd->modifier[0]) { + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + return lookup_format_info(ccs_formats, + ARRAY_SIZE(ccs_formats), + cmd->pixel_format); + default: + return NULL; + } +} + static int intel_fill_fb_info(struct drm_i915_private *dev_priv, struct drm_framebuffer *fb) @@ -2456,6 +2530,36 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, intel_fb_offset_to_xy(&x, &y, fb, i); + if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int tile_width, tile_height; + int main_x, main_y; + int ccs_x, ccs_y; + + intel_tile_dims(fb, i, &tile_width, &tile_height); + + ccs_x = (x * hsub) % (tile_width * hsub); + ccs_y = (y * vsub) % (tile_height * vsub); + main_x = intel_fb->normal[0].x % (tile_width * hsub); + main_y = intel_fb->normal[0].y % (tile_height * vsub); + + /* + * CCS doesn't have its own x/y offset register, so the intra CCS tile + * x/y offsets must match between CCS and the main surface. + */ + if (main_x != ccs_x || main_y != ccs_y) { + DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", + main_x, main_y, + ccs_x, ccs_y, + intel_fb->normal[0].x, + intel_fb->normal[0].y, + x, y); + return -EINVAL; + } + } + /* * The fence (if used) is aligned to the start of the object * so having the framebuffer wrap around across the edge of the @@ -2664,20 +2768,6 @@ out_unref_obj: return false; } -/* Update plane->state->fb to match plane->fb after driver-internal updates */ -static void -update_state_fb(struct drm_plane *plane) -{ - if (plane->fb == plane->state->fb) - return; - - if (plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); - plane->state->fb = plane->fb; - if (plane->state->fb) - drm_framebuffer_reference(plane->state->fb); -} - static void intel_set_plane_visible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state, @@ -2830,6 +2920,9 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, break; } break; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* FIXME AUX plane? */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: switch (cpp) { @@ -2852,6 +2945,44 @@ static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, return 2048; } +static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, + int main_x, int main_y, u32 main_offset) +{ + const struct drm_framebuffer *fb = plane_state->base.fb; + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int aux_x = plane_state->aux.x; + int aux_y = plane_state->aux.y; + u32 aux_offset = plane_state->aux.offset; + u32 alignment = intel_surf_alignment(fb, 1); + + while (aux_offset >= main_offset && aux_y <= main_y) { + int x, y; + + if (aux_x == main_x && aux_y == main_y) + break; + + if (aux_offset == 0) + break; + + x = aux_x / hsub; + y = aux_y / vsub; + aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, + aux_offset, aux_offset - alignment); + aux_x = x * hsub + aux_x % hsub; + aux_y = y * vsub + aux_y % vsub; + } + + if (aux_x != main_x || aux_y != main_y) + return false; + + plane_state->aux.offset = aux_offset; + plane_state->aux.x = aux_x; + plane_state->aux.y = aux_y; + + return true; +} + static int skl_check_main_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->base.fb; @@ -2894,7 +3025,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) while ((x + w) * cpp > fb->pitches[0]) { if (offset == 0) { - DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); return -EINVAL; } @@ -2903,6 +3034,26 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) } } + /* + * CCS AUX surface doesn't have its own x/y offsets, we must make sure + * they match with the main surface x/y offsets. + */ + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { + while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { + if (offset == 0) + break; + + offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, + offset, offset - alignment); + } + + if (x != plane_state->aux.x || y != plane_state->aux.y) { + DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); + return -EINVAL; + } + } + plane_state->main.offset = offset; plane_state->main.x = x; plane_state->main.y = y; @@ -2939,6 +3090,49 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) return 0; } +static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->base.plane); + struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); + const struct drm_framebuffer *fb = plane_state->base.fb; + int src_x = plane_state->base.src.x1 >> 16; + int src_y = plane_state->base.src.y1 >> 16; + int hsub = fb->format->hsub; + int vsub = fb->format->vsub; + int x = src_x / hsub; + int y = src_y / vsub; + u32 offset; + + switch (plane->id) { + case PLANE_PRIMARY: + case PLANE_SPRITE0: + break; + default: + DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); + return -EINVAL; + } + + if (crtc->pipe == PIPE_C) { + DRM_DEBUG_KMS("No RC support on pipe C\n"); + return -EINVAL; + } + + if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { + DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", + plane_state->base.rotation); + return -EINVAL; + } + + intel_add_fb_offsets(&x, &y, plane_state, 1); + offset = intel_compute_tile_offset(&x, &y, plane_state, 1); + + plane_state->aux.offset = offset; + plane_state->aux.x = x * hsub + src_x % hsub; + plane_state->aux.y = y * vsub + src_y % vsub; + + return 0; +} + int skl_check_plane_surface(struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->base.fb; @@ -2962,6 +3156,11 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state) ret = skl_check_nv12_aux_surface(plane_state); if (ret) return ret; + } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { + ret = skl_check_ccs_aux_surface(plane_state); + if (ret) + return ret; } else { plane_state->aux.offset = ~0xfff; plane_state->aux.x = 0; @@ -3268,8 +3467,12 @@ static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) return PLANE_CTL_TILED_X; case I915_FORMAT_MOD_Y_TILED: return PLANE_CTL_TILED_Y; + case I915_FORMAT_MOD_Y_TILED_CCS: + return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; case I915_FORMAT_MOD_Yf_TILED: return PLANE_CTL_TILED_YF; + case I915_FORMAT_MOD_Yf_TILED_CCS: + return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; default: MISSING_CASE(fb_modifier); } @@ -3342,6 +3545,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane, u32 plane_ctl = plane_state->ctl; unsigned int rotation = plane_state->base.rotation; u32 stride = skl_plane_stride(fb, 0, rotation); + u32 aux_stride = skl_plane_stride(fb, 1, rotation); u32 surf_addr = plane_state->main.offset; int scaler_id = plane_state->scaler_id; int src_x = plane_state->main.x; @@ -3378,6 +3582,10 @@ static void skylake_update_primary_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), + (plane_state->aux.offset - surf_addr) | aux_stride); + I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->aux.y << 16) | plane_state->aux.x); if (scaler_id >= 0) { uint32_t ps_ctrl = 0; @@ -3419,14 +3627,6 @@ static void skylake_disable_primary_plane(struct intel_plane *primary, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -static void intel_complete_page_flips(struct drm_i915_private *dev_priv) -{ - struct intel_crtc *crtc; - - for_each_intel_crtc(&dev_priv->drm, crtc) - intel_finish_page_flip_cs(dev_priv, crtc->pipe); -} - static int __intel_display_resume(struct drm_device *dev, struct drm_atomic_state *state, @@ -3485,6 +3685,15 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) !gpu_reset_clobbers_display(dev_priv)) return; + /* We have a modeset vs reset deadlock, defensively unbreak it. */ + set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); + wake_up_all(&dev_priv->gpu_error.wait_queue); + + if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { + DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); + i915_gem_set_wedged(dev_priv); + } + /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. @@ -3535,13 +3744,6 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) if (!state) goto unlock; - /* - * Flips in the rings will be nuked by the reset, - * so complete all pending flips so that user space - * will get its events and not get stuck. - */ - intel_complete_page_flips(dev_priv); - dev_priv->modeset_restore_state = NULL; /* reset doesn't touch the display */ @@ -3578,35 +3780,8 @@ unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); mutex_unlock(&dev->mode_config.mutex); -} - -static bool abort_flip_on_reset(struct intel_crtc *crtc) -{ - struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; - - if (i915_reset_backoff(error)) - return true; - - if (crtc->reset_count != i915_reset_count(error)) - return true; - - return false; -} - -static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - bool pending; - - if (abort_flip_on_reset(intel_crtc)) - return false; - spin_lock_irq(&dev->event_lock); - pending = to_intel_crtc(crtc)->flip_work != NULL; - spin_unlock_irq(&dev->event_lock); - - return pending; + clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); } static void intel_update_pipe_config(struct intel_crtc *crtc, @@ -4163,21 +4338,22 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) { - struct intel_crtc *crtc; - - /* Note that we don't need to be called with mode_config.lock here - * as our list of CRTC objects is static for the lifetime of the - * device and so cannot disappear as we iterate. Similarly, we can - * happily treat the predicates as racy, atomic checks as userspace - * cannot claim and pin a new fb without at least acquring the - * struct_mutex and so serialising with us. - */ - for_each_intel_crtc(&dev_priv->drm, crtc) { - if (atomic_read(&crtc->unpin_work_count) == 0) + struct drm_crtc *crtc; + bool cleanup_done; + + drm_for_each_crtc(crtc, &dev_priv->drm) { + struct drm_crtc_commit *commit; + spin_lock(&crtc->commit_lock); + commit = list_first_entry_or_null(&crtc->commit_list, + struct drm_crtc_commit, commit_entry); + cleanup_done = commit ? + try_wait_for_completion(&commit->cleanup_done) : true; + spin_unlock(&crtc->commit_lock); + + if (cleanup_done) continue; - if (crtc->flip_work) - intel_wait_for_vblank(dev_priv, crtc->pipe); + drm_crtc_wait_one_vblank(crtc); return true; } @@ -4185,57 +4361,6 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) return false; } -static void page_flip_completed(struct intel_crtc *intel_crtc) -{ - struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - struct intel_flip_work *work = intel_crtc->flip_work; - - intel_crtc->flip_work = NULL; - - if (work->event) - drm_crtc_send_vblank_event(&intel_crtc->base, work->event); - - drm_crtc_vblank_put(&intel_crtc->base); - - wake_up_all(&dev_priv->pending_flip_queue); - trace_i915_flip_complete(intel_crtc->plane, - work->pending_flip_obj); - - queue_work(dev_priv->wq, &work->unpin_work); -} - -static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - long ret; - - WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); - - ret = wait_event_interruptible_timeout( - dev_priv->pending_flip_queue, - !intel_crtc_has_pending_flip(crtc), - 60*HZ); - - if (ret < 0) - return ret; - - if (ret == 0) { - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = intel_crtc->flip_work; - if (work && !is_mmio_work(work)) { - WARN_ONCE(1, "Removing stuck page flip\n"); - page_flip_completed(intel_crtc); - } - spin_unlock_irq(&dev->event_lock); - } - - return 0; -} - void lpt_disable_iclkip(struct drm_i915_private *dev_priv) { u32 temp; @@ -4555,7 +4680,7 @@ static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); + assert_pch_transcoder_disabled(dev_priv, PIPE_A); lpt_program_iclkip(crtc); @@ -4600,6 +4725,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ need_scaling = src_w != dst_w || src_h != dst_h; + if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) + need_scaling = true; + /* * Scaling/fitting not supported in IF-ID mode in GEN9+ * TODO: Interlace fetch mode doesn't support YUV420 planar formats. @@ -5323,8 +5451,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, return; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); @@ -5409,8 +5536,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, intel_wait_for_vblank(dev_priv, pipe); intel_wait_for_vblank(dev_priv, pipe); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } /* If we change the relative order between pipe/planes enabling, we need @@ -5507,8 +5633,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; if (intel_crtc->config->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - false); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -5536,8 +5661,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, intel_encoders_post_disable(crtc, old_crtc_state, old_state); if (old_crtc_state->has_pch_encoder) - intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, - true); + intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } static void i9xx_pfit_enable(struct intel_crtc *crtc) @@ -5846,8 +5970,6 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, return; if (crtc->primary->state->visible) { - WARN_ON(intel_crtc->flip_work); - intel_pre_disable_primary_noatomic(crtc); intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); @@ -6256,6 +6378,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return -EINVAL; } + if (pipe_config->ycbcr420 && pipe_config->base.ctm) { + /* + * There is only one pipe CSC unit per pipe, and we need that + * for output conversion from RGB->YCBCR. So if CTM is already + * applied we can't support YCBCR420 output. + */ + DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); + return -EINVAL; + } + /* * Pipe horizontal size must be even in: * - DVO ganged mode @@ -8049,6 +8181,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_crtc_state *config = intel_crtc->config; if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { u32 val = 0; @@ -8074,6 +8207,12 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) if (intel_crtc->config->dither) val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; + if (config->ycbcr420) { + val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | + PIPEMISC_YUV420_ENABLE | + PIPEMISC_YUV420_MODE_FULL_BLEND; + } + I915_WRITE(PIPEMISC(intel_crtc->pipe), val); } } @@ -8401,10 +8540,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, fb->modifier = I915_FORMAT_MOD_X_TILED; break; case PLANE_CTL_TILED_Y: - fb->modifier = I915_FORMAT_MOD_Y_TILED; + if (val & PLANE_CTL_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Y_TILED; break; case PLANE_CTL_TILED_YF: - fb->modifier = I915_FORMAT_MOD_Yf_TILED; + if (val & PLANE_CTL_DECOMPRESSION_ENABLE) + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; + else + fb->modifier = I915_FORMAT_MOD_Yf_TILED; break; default: MISSING_CASE(tiling); @@ -8638,7 +8783,8 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", pipe_name(crtc->pipe)); - I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); + I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)), + "Display power well on\n"); I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); @@ -9108,12 +9254,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, u64 power_domain_mask; bool active; - if (INTEL_GEN(dev_priv) >= 9) { - intel_crtc_init_scalers(crtc, pipe_config); - - pipe_config->scaler_state.scaler_id = -1; - pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); - } + intel_crtc_init_scalers(crtc, pipe_config); power_domain = POWER_DOMAIN_PIPE(crtc->pipe); if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) @@ -9143,6 +9284,23 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; + if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) { + u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); + bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; + + if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) { + bool blend_mode_420 = tmp & + PIPEMISC_YUV420_MODE_FULL_BLEND; + + pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; + if (pipe_config->ycbcr420 != clrspace_yuv || + pipe_config->ycbcr420 != blend_mode_420) + DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); + } else if (clrspace_yuv) { + DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); + } + } + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); @@ -10120,849 +10278,11 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, static void intel_crtc_destroy(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct intel_flip_work *work; - - spin_lock_irq(&dev->event_lock); - work = intel_crtc->flip_work; - intel_crtc->flip_work = NULL; - spin_unlock_irq(&dev->event_lock); - - if (work) { - cancel_work_sync(&work->mmio_work); - cancel_work_sync(&work->unpin_work); - kfree(work); - } drm_crtc_cleanup(crtc); - kfree(intel_crtc); } -static void intel_unpin_work_fn(struct work_struct *__work) -{ - struct intel_flip_work *work = - container_of(__work, struct intel_flip_work, unpin_work); - struct intel_crtc *crtc = to_intel_crtc(work->crtc); - struct drm_device *dev = crtc->base.dev; - struct drm_plane *primary = crtc->base.primary; - - if (is_mmio_work(work)) - flush_work(&work->mmio_work); - - mutex_lock(&dev->struct_mutex); - intel_unpin_fb_vma(work->old_vma); - i915_gem_object_put(work->pending_flip_obj); - mutex_unlock(&dev->struct_mutex); - - i915_gem_request_put(work->flip_queued_req); - - intel_frontbuffer_flip_complete(to_i915(dev), - to_intel_plane(primary)->frontbuffer_bit); - intel_fbc_post_update(crtc); - drm_framebuffer_unreference(work->old_fb); - - BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); - atomic_dec(&crtc->unpin_work_count); - - kfree(work); -} - -/* Is 'a' after or equal to 'b'? */ -static bool g4x_flip_count_after_eq(u32 a, u32 b) -{ - return !((a - b) & 0x80000000); -} - -static bool __pageflip_finished_cs(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - - if (abort_flip_on_reset(crtc)) - return true; - - /* - * The relevant registers doen't exist on pre-ctg. - * As the flip done interrupt doesn't trigger for mmio - * flips on gmch platforms, a flip count check isn't - * really needed there. But since ctg has the registers, - * include it in the check anyway. - */ - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) - return true; - - /* - * BDW signals flip done immediately if the plane - * is disabled, even if the plane enable is already - * armed to occur at the next vblank :( - */ - - /* - * A DSPSURFLIVE check isn't enough in case the mmio and CS flips - * used the same base address. In that case the mmio flip might - * have completed, but the CS hasn't even executed the flip yet. - * - * A flip count check isn't enough as the CS might have updated - * the base address just after start of vblank, but before we - * managed to process the interrupt. This means we'd complete the - * CS flip too soon. - * - * Combining both checks should get us a good enough result. It may - * still happen that the CS flip has been executed, but has not - * yet actually completed. But in case the base address is the same - * anyway, we don't really care. - */ - return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == - crtc->flip_work->gtt_offset && - g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), - crtc->flip_work->flip_count); -} - -static bool -__pageflip_finished_mmio(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - /* - * MMIO work completes when vblank is different from - * flip_queued_vblank. - * - * Reset counter value doesn't matter, this is handled by - * i915_wait_request finishing early, so no need to handle - * reset here. - */ - return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; -} - - -static bool pageflip_finished(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - if (!atomic_read(&work->pending)) - return false; - - smp_rmb(); - - if (is_mmio_work(work)) - return __pageflip_finished_mmio(crtc, work); - else - return __pageflip_finished_cs(crtc, work); -} - -void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (!crtc) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = crtc->flip_work; - - if (work != NULL && - !is_mmio_work(work) && - pageflip_finished(crtc, work)) - page_flip_completed(crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - -void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - unsigned long flags; - - /* Ignore early vblank irqs */ - if (!crtc) - return; - - /* - * This is called both by irq handlers and the reset code (to complete - * lost pageflips) so needs the full irqsave spinlocks. - */ - spin_lock_irqsave(&dev->event_lock, flags); - work = crtc->flip_work; - - if (work != NULL && - is_mmio_work(work) && - pageflip_finished(crtc, work)) - page_flip_completed(crtc); - - spin_unlock_irqrestore(&dev->event_lock, flags); -} - -static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, - struct intel_flip_work *work) -{ - work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); - - /* Ensure that the work item is consistent when activating it ... */ - smp_mb__before_atomic(); - atomic_set(&work->pending, 1); -} - -static int intel_gen2_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask, *cs; - - cs = intel_ring_begin(req, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Can't queue multiple flips, so wait for the previous - * one to finish before executing the next. - */ - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - *cs++ = MI_WAIT_FOR_EVENT | flip_mask; - *cs++ = MI_NOOP; - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = 0; /* aux display base address, unused */ - - return 0; -} - -static int intel_gen3_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 flip_mask, *cs; - - cs = intel_ring_begin(req, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - if (intel_crtc->plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; - *cs++ = MI_WAIT_FOR_EVENT | flip_mask; - *cs++ = MI_NOOP; - *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = MI_NOOP; - - return 0; -} - -static int intel_gen4_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 pf, pipesrc, *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* i965+ uses the linear or tiled offsets from the - * Display Registers (which do not change across a page-flip) - * so we need only reprogram the base address. - */ - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0]; - *cs++ = intel_crtc->flip_work->gtt_offset | - intel_fb_modifier_to_tiling(fb->modifier); - - /* XXX Enabling the panel-fitter across page-flip is so far - * untested on non-native modes, so ignore it for now. - * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - *cs++ = pf | pipesrc; - - return 0; -} - -static int intel_gen6_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 pf, pipesrc, *cs; - - cs = intel_ring_begin(req, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); - *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); - *cs++ = intel_crtc->flip_work->gtt_offset; - - /* Contrary to the suggestions in the documentation, - * "Enable Panel Fitter" does not seem to be required when page - * flipping with a non-native mode, and worse causes a normal - * modeset to fail. - * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; - */ - pf = 0; - pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; - *cs++ = pf | pipesrc; - - return 0; -} - -static int intel_gen7_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 *cs, plane_bit = 0; - int len, ret; - - switch (intel_crtc->plane) { - case PLANE_A: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; - break; - case PLANE_B: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; - break; - case PLANE_C: - plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; - break; - default: - WARN_ONCE(1, "unknown plane in flip command\n"); - return -ENODEV; - } - - len = 4; - if (req->engine->id == RCS) { - len += 6; - /* - * On Gen 8, SRM is now taking an extra dword to accommodate - * 48bits addresses, and we need a NOOP for the batch size to - * stay even. - */ - if (IS_GEN8(dev_priv)) - len += 2; - } - - /* - * BSpec MI_DISPLAY_FLIP for IVB: - * "The full packet must be contained within the same cache line." - * - * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same - * cacheline, if we ever start emitting more commands before - * the MI_DISPLAY_FLIP we may need to first emit everything else, - * then do the cacheline alignment, and finally emit the - * MI_DISPLAY_FLIP. - */ - ret = intel_ring_cacheline_align(req); - if (ret) - return ret; - - cs = intel_ring_begin(req, len); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Unmask the flip-done completion message. Note that the bspec says that - * we should do this for both the BCS and RCS, and that we must not unmask - * more than one flip event at any time (or ensure that one flip message - * can be sent by waiting for flip-done prior to queueing new flips). - * Experimentation says that BCS works despite DERRMR masking all - * flip-done completion events and that unmasking all planes at once - * for the RCS also doesn't appear to drop events. Setting the DERRMR - * to zero does lead to lockups within MI_DISPLAY_FLIP. - */ - if (req->engine->id == RCS) { - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(DERRMR); - *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | - DERRMR_PIPEB_PRI_FLIP_DONE | - DERRMR_PIPEC_PRI_FLIP_DONE); - if (IS_GEN8(dev_priv)) - *cs++ = MI_STORE_REGISTER_MEM_GEN8 | - MI_SRM_LRM_GLOBAL_GTT; - else - *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; - *cs++ = i915_mmio_reg_offset(DERRMR); - *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; - if (IS_GEN8(dev_priv)) { - *cs++ = 0; - *cs++ = MI_NOOP; - } - } - - *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; - *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); - *cs++ = intel_crtc->flip_work->gtt_offset; - *cs++ = MI_NOOP; - - return 0; -} - -static bool use_mmio_flip(struct intel_engine_cs *engine, - struct drm_i915_gem_object *obj) -{ - /* - * This is not being used for older platforms, because - * non-availability of flip done interrupt forces us to use - * CS flips. Older platforms derive flip done using some clever - * tricks involving the flip_pending status bits and vblank irqs. - * So using MMIO flips there would disrupt this mechanism. - */ - - if (engine == NULL) - return true; - - if (INTEL_GEN(engine->i915) < 5) - return false; - - if (i915.use_mmio_flip < 0) - return false; - else if (i915.use_mmio_flip > 0) - return true; - else if (i915.enable_execlists) - return true; - - return engine != i915_gem_object_last_write_engine(obj); -} - -static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, - unsigned int rotation, - struct intel_flip_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - const enum pipe pipe = intel_crtc->pipe; - u32 ctl, stride = skl_plane_stride(fb, 0, rotation); - - ctl = I915_READ(PLANE_CTL(pipe, 0)); - ctl &= ~PLANE_CTL_TILED_MASK; - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - break; - case I915_FORMAT_MOD_X_TILED: - ctl |= PLANE_CTL_TILED_X; - break; - case I915_FORMAT_MOD_Y_TILED: - ctl |= PLANE_CTL_TILED_Y; - break; - case I915_FORMAT_MOD_Yf_TILED: - ctl |= PLANE_CTL_TILED_YF; - break; - default: - MISSING_CASE(fb->modifier); - } - - /* - * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on - * PLANE_SURF updates, the update is then guaranteed to be atomic. - */ - I915_WRITE(PLANE_CTL(pipe, 0), ctl); - I915_WRITE(PLANE_STRIDE(pipe, 0), stride); - - I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); - POSTING_READ(PLANE_SURF(pipe, 0)); -} - -static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, - struct intel_flip_work *work) -{ - struct drm_device *dev = intel_crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *fb = intel_crtc->base.primary->fb; - i915_reg_t reg = DSPCNTR(intel_crtc->plane); - u32 dspcntr; - - dspcntr = I915_READ(reg); - - if (fb->modifier == I915_FORMAT_MOD_X_TILED) - dspcntr |= DISPPLANE_TILED; - else - dspcntr &= ~DISPPLANE_TILED; - - I915_WRITE(reg, dspcntr); - - I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); - POSTING_READ(DSPSURF(intel_crtc->plane)); -} - -static void intel_mmio_flip_work_func(struct work_struct *w) -{ - struct intel_flip_work *work = - container_of(w, struct intel_flip_work, mmio_work); - struct intel_crtc *crtc = to_intel_crtc(work->crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_framebuffer *intel_fb = - to_intel_framebuffer(crtc->base.primary->fb); - struct drm_i915_gem_object *obj = intel_fb->obj; - - WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); - - intel_pipe_update_start(crtc); - - if (INTEL_GEN(dev_priv) >= 9) - skl_do_mmio_flip(crtc, work->rotation, work); - else - /* use_mmio_flip() retricts MMIO flips to ilk+ */ - ilk_do_mmio_flip(crtc, work); - - intel_pipe_update_end(crtc, work); -} - -static int intel_default_queue_flip(struct drm_device *dev, - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_i915_gem_object *obj, - struct drm_i915_gem_request *req, - uint32_t flags) -{ - return -ENODEV; -} - -static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, - struct intel_crtc *intel_crtc, - struct intel_flip_work *work) -{ - u32 addr, vblank; - - if (!atomic_read(&work->pending)) - return false; - - smp_rmb(); - - vblank = intel_crtc_get_vblank_counter(intel_crtc); - if (work->flip_ready_vblank == 0) { - if (work->flip_queued_req && - !i915_gem_request_completed(work->flip_queued_req)) - return false; - - work->flip_ready_vblank = vblank; - } - - if (vblank - work->flip_ready_vblank < 3) - return false; - - /* Potential stall - if we see that the flip has happened, - * assume a missed interrupt. */ - if (INTEL_GEN(dev_priv) >= 4) - addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); - else - addr = I915_READ(DSPADDR(intel_crtc->plane)); - - /* There is a potential issue here with a false positive after a flip - * to the same address. We could address this by checking for a - * non-incrementing frame counter. - */ - return addr == work->gtt_offset; -} - -void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) -{ - struct drm_device *dev = &dev_priv->drm; - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - struct intel_flip_work *work; - - WARN_ON(!in_interrupt()); - - if (crtc == NULL) - return; - - spin_lock(&dev->event_lock); - work = crtc->flip_work; - - if (work != NULL && !is_mmio_work(work) && - __pageflip_stall_check_cs(dev_priv, crtc, work)) { - WARN_ONCE(1, - "Kicking stuck page flip: queued at %d, now %d\n", - work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); - page_flip_completed(crtc); - work = NULL; - } - - if (work != NULL && !is_mmio_work(work) && - intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) - intel_queue_rps_boost_for_request(work->flip_queued_req); - spin_unlock(&dev->event_lock); -} - -__maybe_unused -static int intel_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) -{ - struct drm_device *dev = crtc->dev; - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_framebuffer *old_fb = crtc->primary->fb; - struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - struct drm_plane *primary = crtc->primary; - enum pipe pipe = intel_crtc->pipe; - struct intel_flip_work *work; - struct intel_engine_cs *engine; - bool mmio_flip; - struct drm_i915_gem_request *request; - struct i915_vma *vma; - int ret; - - /* - * drm_mode_page_flip_ioctl() should already catch this, but double - * check to be safe. In the future we may enable pageflipping from - * a disabled primary plane. - */ - if (WARN_ON(intel_fb_obj(old_fb) == NULL)) - return -EBUSY; - - /* Can't change pixel format via MI display flips. */ - if (fb->format != crtc->primary->fb->format) - return -EINVAL; - - /* - * TILEOFF/LINOFF registers can't be changed via MI display flips. - * Note that pitch changes could also affect these register. - */ - if (INTEL_GEN(dev_priv) > 3 && - (fb->offsets[0] != crtc->primary->fb->offsets[0] || - fb->pitches[0] != crtc->primary->fb->pitches[0])) - return -EINVAL; - - if (i915_terminally_wedged(&dev_priv->gpu_error)) - goto out_hang; - - work = kzalloc(sizeof(*work), GFP_KERNEL); - if (work == NULL) - return -ENOMEM; - - work->event = event; - work->crtc = crtc; - work->old_fb = old_fb; - INIT_WORK(&work->unpin_work, intel_unpin_work_fn); - - ret = drm_crtc_vblank_get(crtc); - if (ret) - goto free_work; - - /* We borrow the event spin lock for protecting flip_work */ - spin_lock_irq(&dev->event_lock); - if (intel_crtc->flip_work) { - /* Before declaring the flip queue wedged, check if - * the hardware completed the operation behind our backs. - */ - if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { - DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); - page_flip_completed(intel_crtc); - } else { - DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); - spin_unlock_irq(&dev->event_lock); - - drm_crtc_vblank_put(crtc); - kfree(work); - return -EBUSY; - } - } - intel_crtc->flip_work = work; - spin_unlock_irq(&dev->event_lock); - - if (atomic_read(&intel_crtc->unpin_work_count) >= 2) - flush_workqueue(dev_priv->wq); - - /* Reference the objects for the scheduled work. */ - drm_framebuffer_reference(work->old_fb); - - crtc->primary->fb = fb; - update_state_fb(crtc->primary); - - work->pending_flip_obj = i915_gem_object_get(obj); - - ret = i915_mutex_lock_interruptible(dev); - if (ret) - goto cleanup; - - intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); - if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) { - ret = -EIO; - goto unlock; - } - - atomic_inc(&intel_crtc->unpin_work_count); - - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) - work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; - - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - engine = dev_priv->engine[BCS]; - if (fb->modifier != old_fb->modifier) - /* vlv: DISPLAY_FLIP fails to change tiling */ - engine = NULL; - } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { - engine = dev_priv->engine[BCS]; - } else if (INTEL_GEN(dev_priv) >= 7) { - engine = i915_gem_object_last_write_engine(obj); - if (engine == NULL || engine->id != RCS) - engine = dev_priv->engine[BCS]; - } else { - engine = dev_priv->engine[RCS]; - } - - mmio_flip = use_mmio_flip(engine, obj); - - vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto cleanup_pending; - } - - work->old_vma = to_intel_plane_state(primary->state)->vma; - to_intel_plane_state(primary->state)->vma = vma; - - work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; - work->rotation = crtc->primary->state->rotation; - - /* - * There's the potential that the next frame will not be compatible with - * FBC, so we want to call pre_update() before the actual page flip. - * The problem is that pre_update() caches some information about the fb - * object, so we want to do this only after the object is pinned. Let's - * be on the safe side and do this immediately before scheduling the - * flip. - */ - intel_fbc_pre_update(intel_crtc, intel_crtc->config, - to_intel_plane_state(primary->state)); - - if (mmio_flip) { - INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); - queue_work(system_unbound_wq, &work->mmio_work); - } else { - request = i915_gem_request_alloc(engine, - dev_priv->kernel_context); - if (IS_ERR(request)) { - ret = PTR_ERR(request); - goto cleanup_unpin; - } - - ret = i915_gem_request_await_object(request, obj, false); - if (ret) - goto cleanup_request; - - ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, - page_flip_flags); - if (ret) - goto cleanup_request; - - intel_mark_page_flip_active(intel_crtc, work); - - work->flip_queued_req = i915_gem_request_get(request); - i915_add_request(request); - } - - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); - i915_gem_track_fb(intel_fb_obj(old_fb), obj, - to_intel_plane(primary)->frontbuffer_bit); - mutex_unlock(&dev->struct_mutex); - - intel_frontbuffer_flip_prepare(to_i915(dev), - to_intel_plane(primary)->frontbuffer_bit); - - trace_i915_flip_request(intel_crtc->plane, obj); - - return 0; - -cleanup_request: - i915_add_request(request); -cleanup_unpin: - to_intel_plane_state(primary->state)->vma = work->old_vma; - intel_unpin_fb_vma(vma); -cleanup_pending: - atomic_dec(&intel_crtc->unpin_work_count); -unlock: - mutex_unlock(&dev->struct_mutex); -cleanup: - crtc->primary->fb = old_fb; - update_state_fb(crtc->primary); - - i915_gem_object_put(obj); - drm_framebuffer_unreference(work->old_fb); - - spin_lock_irq(&dev->event_lock); - intel_crtc->flip_work = NULL; - spin_unlock_irq(&dev->event_lock); - - drm_crtc_vblank_put(crtc); -free_work: - kfree(work); - - if (ret == -EIO) { - struct drm_atomic_state *state; - struct drm_plane_state *plane_state; - -out_hang: - state = drm_atomic_state_alloc(dev); - if (!state) - return -ENOMEM; - state->acquire_ctx = dev->mode_config.acquire_ctx; - -retry: - plane_state = drm_atomic_get_plane_state(state, primary); - ret = PTR_ERR_OR_ZERO(plane_state); - if (!ret) { - drm_atomic_set_fb_for_plane(plane_state, fb); - - ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); - if (!ret) - ret = drm_atomic_commit(state); - } - - if (ret == -EDEADLK) { - drm_modeset_backoff(state->acquire_ctx); - drm_atomic_state_clear(state); - goto retry; - } - - drm_atomic_state_put(state); - - if (ret == 0 && event) { - spin_lock_irq(&dev->event_lock); - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irq(&dev->event_lock); - } - } - return ret; -} - - /** * intel_wm_need_update - Check whether watermarks need updating * @plane: drm plane @@ -11360,6 +10680,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->fdi_lanes, &pipe_config->fdi_m_n); + if (pipe_config->ycbcr420) + DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); + if (intel_crtc_has_dp_encoder(pipe_config)) { intel_dump_m_n_config(pipe_config, "dp m_n", pipe_config->lane_count, &pipe_config->dp_m_n); @@ -11931,6 +11254,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(hdmi_scrambling); PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); PIPE_CONF_CHECK_I(has_infoframe); + PIPE_CONF_CHECK_I(ycbcr420); PIPE_CONF_CHECK_I(has_audio); @@ -12772,31 +12096,7 @@ static int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct drm_device *dev, struct drm_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_crtc_state *crtc_state; - struct drm_crtc *crtc; - int i, ret; - - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { - if (state->legacy_cursor_update) - continue; - - ret = intel_crtc_wait_for_pending_flips(crtc); - if (ret) - return ret; - - if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) - flush_workqueue(dev_priv->wq); - } - - ret = mutex_lock_interruptible(&dev->struct_mutex); - if (ret) - return ret; - - ret = drm_atomic_helper_prepare_planes(dev, state); - mutex_unlock(&dev->struct_mutex); - - return ret; + return drm_atomic_helper_prepare_planes(dev, state); } u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) @@ -13007,6 +12307,30 @@ static void intel_atomic_helper_free_state_worker(struct work_struct *work) intel_atomic_helper_free_state(dev_priv); } +static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) +{ + struct wait_queue_entry wait_fence, wait_reset; + struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev); + + init_wait_entry(&wait_fence, 0); + init_wait_entry(&wait_reset, 0); + for (;;) { + prepare_to_wait(&intel_state->commit_ready.wait, + &wait_fence, TASK_UNINTERRUPTIBLE); + prepare_to_wait(&dev_priv->gpu_error.wait_queue, + &wait_reset, TASK_UNINTERRUPTIBLE); + + + if (i915_sw_fence_done(&intel_state->commit_ready) + || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags)) + break; + + schedule(); + } + finish_wait(&intel_state->commit_ready.wait, &wait_fence); + finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset); +} + static void intel_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; @@ -13020,6 +12344,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) unsigned crtc_vblank_mask = 0; int i; + intel_atomic_commit_fence_wait(intel_state); + drm_atomic_helper_wait_for_dependencies(state); if (intel_state->modeset) @@ -13159,9 +12485,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); } - mutex_lock(&dev->struct_mutex); drm_atomic_helper_cleanup_planes(dev, state); - mutex_unlock(&dev->struct_mutex); drm_atomic_helper_commit_cleanup_done(state); @@ -13187,10 +12511,8 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence, switch (notify) { case FENCE_COMPLETE: - if (state->base.commit_work.func) - queue_work(system_unbound_wq, &state->base.commit_work); + /* we do blocking waits in the worker, nothing to do here */ break; - case FENCE_FREE: { struct intel_atomic_helper *helper = @@ -13276,9 +12598,7 @@ static int intel_atomic_commit(struct drm_device *dev, if (ret) { i915_sw_fence_commit(&intel_state->commit_ready); - mutex_lock(&dev->struct_mutex); drm_atomic_helper_cleanup_planes(dev, state); - mutex_unlock(&dev->struct_mutex); return ret; } dev_priv->wm.distrust_bios_wm = false; @@ -13294,14 +12614,14 @@ static int intel_atomic_commit(struct drm_device *dev, } drm_atomic_state_get(state); - INIT_WORK(&state->commit_work, - nonblock ? intel_atomic_commit_work : NULL); + INIT_WORK(&state->commit_work, intel_atomic_commit_work); i915_sw_fence_commit(&intel_state->commit_ready); - if (!nonblock) { - i915_sw_fence_wait(&intel_state->commit_ready); + if (nonblock) + queue_work(system_unbound_wq, &state->commit_work); + else intel_atomic_commit_tail(state); - } + return 0; } @@ -13342,32 +12662,6 @@ intel_prepare_plane_fb(struct drm_plane *plane, struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); int ret; - if (obj) { - if (plane->type == DRM_PLANE_TYPE_CURSOR && - INTEL_INFO(dev_priv)->cursor_needs_physical) { - const int align = intel_cursor_alignment(dev_priv); - - ret = i915_gem_object_attach_phys(obj, align); - if (ret) { - DRM_DEBUG_KMS("failed to attach phys object\n"); - return ret; - } - } else { - struct i915_vma *vma; - - vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); - if (IS_ERR(vma)) { - DRM_DEBUG_KMS("failed to pin object\n"); - return PTR_ERR(vma); - } - - to_intel_plane_state(new_state)->vma = vma; - } - } - - if (!obj && !old_obj) - return 0; - if (old_obj) { struct drm_crtc_state *crtc_state = drm_atomic_get_existing_crtc_state(new_state->state, @@ -13406,6 +12700,38 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (!obj) return 0; + ret = i915_gem_object_pin_pages(obj); + if (ret) + return ret; + + ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); + if (ret) { + i915_gem_object_unpin_pages(obj); + return ret; + } + + if (plane->type == DRM_PLANE_TYPE_CURSOR && + INTEL_INFO(dev_priv)->cursor_needs_physical) { + const int align = intel_cursor_alignment(dev_priv); + + ret = i915_gem_object_attach_phys(obj, align); + } else { + struct i915_vma *vma; + + vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); + if (!IS_ERR(vma)) + to_intel_plane_state(new_state)->vma = vma; + else + ret = PTR_ERR(vma); + } + + i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); + + mutex_unlock(&dev_priv->drm.struct_mutex); + i915_gem_object_unpin_pages(obj); + if (ret) + return ret; + if (!new_state->fence) { /* implicit fencing */ ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, obj->resv, NULL, @@ -13413,8 +12739,6 @@ intel_prepare_plane_fb(struct drm_plane *plane, GFP_KERNEL); if (ret < 0) return ret; - - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); } return 0; @@ -13437,8 +12761,11 @@ intel_cleanup_plane_fb(struct drm_plane *plane, /* Should only be called after a successful intel_prepare_plane_fb()! */ vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); - if (vma) + if (vma) { + mutex_lock(&plane->dev->struct_mutex); intel_unpin_fb_vma(vma); + mutex_unlock(&plane->dev->struct_mutex); + } } int @@ -13565,7 +12892,7 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc, { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - intel_pipe_update_end(intel_crtc, NULL); + intel_pipe_update_end(intel_crtc); } /** @@ -13581,7 +12908,102 @@ void intel_plane_destroy(struct drm_plane *plane) kfree(to_intel_plane(plane)); } -const struct drm_plane_funcs intel_plane_funcs = { +static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_XRGB8888: + return modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED; + default: + return false; + } +} + +static bool i965_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_C8: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + return modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED; + default: + return false; + } +} + +static bool skl_mod_supported(uint32_t format, uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_CCS) + return true; + /* fall through */ + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == I915_FORMAT_MOD_Yf_TILED) + return true; + /* fall through */ + case DRM_FORMAT_C8: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED || + modifier == I915_FORMAT_MOD_Y_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && + modifier != DRM_FORMAT_MOD_LINEAR) + return false; + + if (INTEL_GEN(dev_priv) >= 9) + return skl_mod_supported(format, modifier); + else if (INTEL_GEN(dev_priv) >= 4) + return i965_mod_supported(format, modifier); + else + return i8xx_mod_supported(format, modifier); + + unreachable(); +} + +static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; +} + +static struct drm_plane_funcs intel_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = intel_plane_destroy, @@ -13589,6 +13011,7 @@ const struct drm_plane_funcs intel_plane_funcs = { .atomic_set_property = intel_plane_atomic_set_property, .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_primary_plane_format_mod_supported, }; static int @@ -13607,7 +13030,7 @@ intel_legacy_cursor_update(struct drm_plane *plane, struct intel_plane *intel_plane = to_intel_plane(plane); struct drm_framebuffer *old_fb; struct drm_crtc_state *crtc_state = crtc->state; - struct i915_vma *old_vma; + struct i915_vma *old_vma, *vma; /* * When crtc is inactive or there is a modeset pending, @@ -13665,8 +13088,6 @@ intel_legacy_cursor_update(struct drm_plane *plane, goto out_unlock; } } else { - struct i915_vma *vma; - vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); if (IS_ERR(vma)) { DRM_DEBUG_KMS("failed to pin object\n"); @@ -13689,7 +13110,7 @@ intel_legacy_cursor_update(struct drm_plane *plane, *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); new_plane_state->fence = NULL; new_plane_state->fb = old_fb; - to_intel_plane_state(new_plane_state)->vma = old_vma; + to_intel_plane_state(new_plane_state)->vma = NULL; if (plane->state->visible) { trace_intel_update_plane(plane, to_intel_crtc(crtc)); @@ -13701,7 +13122,8 @@ intel_legacy_cursor_update(struct drm_plane *plane, intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); } - intel_cleanup_plane_fb(plane, new_plane_state); + if (old_vma) + intel_unpin_fb_vma(old_vma); out_unlock: mutex_unlock(&dev_priv->drm.struct_mutex); @@ -13723,6 +13145,7 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = { .atomic_set_property = intel_plane_atomic_set_property, .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_cursor_plane_format_mod_supported, }; static struct intel_plane * @@ -13733,6 +13156,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) const uint32_t *intel_primary_formats; unsigned int supported_rotations; unsigned int num_formats; + const uint64_t *modifiers; int ret; primary = kzalloc(sizeof(*primary), GFP_KERNEL); @@ -13768,21 +13192,34 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); primary->check_plane = intel_check_primary_plane; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + intel_primary_formats = skl_primary_formats; + num_formats = ARRAY_SIZE(skl_primary_formats); + modifiers = skl_format_modifiers_ccs; + + primary->update_plane = skylake_update_primary_plane; + primary->disable_plane = skylake_disable_primary_plane; + } else if (INTEL_GEN(dev_priv) >= 9) { intel_primary_formats = skl_primary_formats; num_formats = ARRAY_SIZE(skl_primary_formats); + if (pipe < PIPE_C) + modifiers = skl_format_modifiers_ccs; + else + modifiers = skl_format_modifiers_noccs; primary->update_plane = skylake_update_primary_plane; primary->disable_plane = skylake_disable_primary_plane; } else if (INTEL_GEN(dev_priv) >= 4) { intel_primary_formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); + modifiers = i9xx_format_modifiers; primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; } else { intel_primary_formats = i8xx_primary_formats; num_formats = ARRAY_SIZE(i8xx_primary_formats); + modifiers = i9xx_format_modifiers; primary->update_plane = i9xx_update_primary_plane; primary->disable_plane = i9xx_disable_primary_plane; @@ -13792,21 +13229,21 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane 1%c", pipe_name(pipe)); else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, 0, &intel_plane_funcs, intel_primary_formats, num_formats, - NULL, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane %c", plane_name(primary->plane)); if (ret) @@ -13892,7 +13329,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), - NULL, DRM_PLANE_TYPE_CURSOR, + cursor_format_modifiers, + DRM_PLANE_TYPE_CURSOR, "cursor %c", pipe_name(pipe)); if (ret) goto fail; @@ -14414,10 +13852,12 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_i915_private *dev_priv = to_i915(obj->base.dev); + struct drm_framebuffer *fb = &intel_fb->base; struct drm_format_name_buf format_name; - u32 pitch_limit, stride_alignment; + u32 pitch_limit; unsigned int tiling, stride; int ret = -EINVAL; + int i; i915_gem_object_lock(obj); obj->framebuffer_references++; @@ -14446,6 +13886,19 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, /* Passed in modifier sanity checking. */ switch (mode_cmd->modifier[0]) { + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + switch (mode_cmd->pixel_format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + break; + default: + DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); + goto err; + } + /* fall through */ case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: if (INTEL_GEN(dev_priv) < 9) { @@ -14550,25 +14003,46 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, if (mode_cmd->offsets[0] != 0) goto err; - drm_helper_mode_fill_fb_struct(&dev_priv->drm, - &intel_fb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); - stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); - if (mode_cmd->pitches[0] & (stride_alignment - 1)) { - DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", - mode_cmd->pitches[0], stride_alignment); - goto err; + for (i = 0; i < fb->format->num_planes; i++) { + u32 stride_alignment; + + if (mode_cmd->handles[i] != mode_cmd->handles[0]) { + DRM_DEBUG_KMS("bad plane %d handle\n", i); + return -EINVAL; + } + + stride_alignment = intel_fb_stride_alignment(fb, i); + + /* + * Display WA #0531: skl,bxt,kbl,glk + * + * Render decompression and plane width > 3840 + * combined with horizontal panning requires the + * plane stride to be a multiple of 4. We'll just + * require the entire fb to accommodate that to avoid + * potential runtime errors at plane configuration time. + */ + if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) + stride_alignment *= 4; + + if (fb->pitches[i] & (stride_alignment - 1)) { + DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", + i, fb->pitches[i], stride_alignment); + goto err; + } } intel_fb->obj = obj; - ret = intel_fill_fb_info(dev_priv, &intel_fb->base); + ret = intel_fill_fb_info(dev_priv, fb); if (ret) goto err; - ret = drm_framebuffer_init(obj->base.dev, - &intel_fb->base, - &intel_fb_funcs); + ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); if (ret) { DRM_ERROR("framebuffer init failed %d\n", ret); goto err; @@ -14616,6 +14090,7 @@ static void intel_atomic_state_free(struct drm_atomic_state *state) static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_create = intel_user_framebuffer_create, + .get_format_info = intel_get_format_info, .output_poll_changed = intel_fbdev_output_poll_changed, .atomic_check = intel_atomic_check, .atomic_commit = intel_atomic_commit, @@ -14715,34 +14190,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.update_crtcs = skl_update_crtcs; else dev_priv->display.update_crtcs = intel_update_crtcs; - - switch (INTEL_INFO(dev_priv)->gen) { - case 2: - dev_priv->display.queue_flip = intel_gen2_queue_flip; - break; - - case 3: - dev_priv->display.queue_flip = intel_gen3_queue_flip; - break; - - case 4: - case 5: - dev_priv->display.queue_flip = intel_gen4_queue_flip; - break; - - case 6: - dev_priv->display.queue_flip = intel_gen6_queue_flip; - break; - case 7: - case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ - dev_priv->display.queue_flip = intel_gen7_queue_flip; - break; - case 9: - /* Drop through - unsupported since execlist only. */ - default: - /* Default just returns -ENODEV to indicate unsupported */ - dev_priv->display.queue_flip = intel_default_queue_flip; - } } /* @@ -15673,7 +15120,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_wm_get_hw_state(dev); vlv_wm_sanitize(dev_priv); - } else if (IS_GEN9(dev_priv)) { + } else if (INTEL_GEN(dev_priv) >= 9) { skl_wm_get_hw_state(dev); } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_wm_get_hw_state(dev); @@ -15780,6 +15227,9 @@ void intel_modeset_cleanup(struct drm_device *dev) */ drm_kms_helper_poll_fini(dev); + /* poll work can call into fbdev, hence clean that up afterwards */ + intel_fbdev_fini(dev_priv); + intel_unregister_dsm_handler(); intel_fbc_global_disable(dev_priv); @@ -15899,7 +15349,8 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) return NULL; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); + error->power_well_driver = + I915_READ(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL)); for_each_pipe(dev_priv, i) { error->pipe[i].power_domain_on = diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 76c8a0bd17f9..4fd4853b2250 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -97,6 +97,9 @@ static const int bxt_rates[] = { 162000, 216000, 243000, 270000, 324000, 432000, 540000 }; static const int skl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; +static const int cnl_rates[] = { 162000, 216000, 270000, + 324000, 432000, 540000, + 648000, 810000 }; static const int default_rates[] = { 162000, 270000, 540000 }; /** @@ -229,8 +232,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->port; const int *source_rates; int size; + u32 voltage; /* This should only be done once */ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); @@ -238,6 +243,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) if (IS_GEN9_LP(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); + } else if (IS_CANNONLAKE(dev_priv)) { + source_rates = cnl_rates; + size = ARRAY_SIZE(cnl_rates); + voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + if (port == PORT_A || port == PORT_D || + voltage == VOLTAGE_INFO_0_85V) + size -= 2; } else if (IS_GEN9_BC(dev_priv)) { source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); @@ -322,19 +334,20 @@ static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, return 0; } -static bool intel_dp_link_params_valid(struct intel_dp *intel_dp) +static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, + uint8_t lane_count) { /* * FIXME: we need to synchronize the current link parameters with * hardware readout. Currently fast link training doesn't work on * boot-up. */ - if (intel_dp->link_rate == 0 || - intel_dp->link_rate > intel_dp->max_link_rate) + if (link_rate == 0 || + link_rate > intel_dp->max_link_rate) return false; - if (intel_dp->lane_count == 0 || - intel_dp->lane_count > intel_dp_max_lane_count(intel_dp)) + if (lane_count == 0 || + lane_count > intel_dp_max_lane_count(intel_dp)) return false; return true; @@ -1606,6 +1619,23 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, return bpp; } +static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1, + struct drm_display_mode *m2) +{ + bool bres = false; + + if (m1 && m2) + bres = (m1->hdisplay == m2->hdisplay && + m1->hsync_start == m2->hsync_start && + m1->hsync_end == m2->hsync_end && + m1->htotal == m2->htotal && + m1->vdisplay == m2->vdisplay && + m1->vsync_start == m2->vsync_start && + m1->vsync_end == m2->vsync_end && + m1->vtotal == m2->vtotal); + return bres; +} + bool intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, @@ -1652,8 +1682,16 @@ intel_dp_compute_config(struct intel_encoder *encoder, pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { - intel_fixed_panel_mode(intel_connector->panel.fixed_mode, - adjusted_mode); + struct drm_display_mode *panel_mode = + intel_connector->panel.alt_fixed_mode; + struct drm_display_mode *req_mode = &pipe_config->base.mode; + + if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) + panel_mode = intel_connector->panel.fixed_mode; + + drm_mode_debug_printmodeline(panel_mode); + + intel_fixed_panel_mode(panel_mode, adjusted_mode); if (INTEL_GEN(dev_priv) >= 9) { int ret; @@ -1677,12 +1715,18 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { int index; - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - intel_dp->compliance.test_link_rate); - if (index >= 0) - min_clock = max_clock = index; - min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + /* Validate the compliance test data since max values + * might have changed due to link train fallback. + */ + if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, + intel_dp->compliance.test_lane_count)) { + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + intel_dp->compliance.test_link_rate); + if (index >= 0) + min_clock = max_clock = index; + min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; + } } DRM_DEBUG_KMS("DP link computation with max lane count %i " "max bw %d pixel clock %iKHz\n", @@ -3963,8 +4007,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { int status = 0; - int min_lane_count = 1; - int link_rate_index, test_link_rate; + int test_link_rate; uint8_t test_lane_count, test_link_bw; /* (DP CTS 1.2) * 4.3.1.11 @@ -3978,10 +4021,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) return DP_TEST_NAK; } test_lane_count &= DP_MAX_LANE_COUNT_MASK; - /* Validate the requested lane count */ - if (test_lane_count < min_lane_count || - test_lane_count > intel_dp->max_link_lane_count) - return DP_TEST_NAK; status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, &test_link_bw); @@ -3989,12 +4028,11 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Link Rate read failed\n"); return DP_TEST_NAK; } - /* Validate the requested link rate */ test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); - link_rate_index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - test_link_rate); - if (link_rate_index < 0) + + /* Validate the requested link rate and lane count */ + if (!intel_dp_link_params_valid(intel_dp, test_link_rate, + test_lane_count)) return DP_TEST_NAK; intel_dp->compliance.test_lane_count = test_lane_count; @@ -4263,7 +4301,8 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) * Validate the cached values of intel_dp->link_rate and * intel_dp->lane_count before attempting to retrain. */ - if (!intel_dp_link_params_valid(intel_dp)) + if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, + intel_dp->lane_count)) return; /* Retrain if Channel EQ or CR not ok */ @@ -4566,7 +4605,7 @@ static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, enum port port; u32 bit; - intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); + port = intel_hpd_pin_to_port(intel_encoder->hpd_pin); switch (port) { case PORT_A: bit = BXT_DE_PORT_HP_DDIA; @@ -5780,6 +5819,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct drm_display_mode *fixed_mode = NULL; + struct drm_display_mode *alt_fixed_mode = NULL; struct drm_display_mode *downclock_mode = NULL; bool has_dpcd; struct drm_display_mode *scan; @@ -5835,13 +5875,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, } intel_connector->edid = edid; - /* prefer fixed mode from EDID if available */ + /* prefer fixed mode from EDID if available, save an alt mode also */ list_for_each_entry(scan, &connector->probed_modes, head) { if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { fixed_mode = drm_mode_duplicate(dev, scan); downclock_mode = intel_dp_drrs_init( intel_connector, fixed_mode); - break; + } else if (!alt_fixed_mode) { + alt_fixed_mode = drm_mode_duplicate(dev, scan); } } @@ -5878,7 +5919,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, pipe_name(pipe)); } - intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); + intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode, + downclock_mode); intel_connector->panel.backlight.power = intel_edp_backlight_power; intel_panel_setup_backlight(connector, pipe); @@ -5904,26 +5946,22 @@ intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port) struct intel_encoder *encoder = &intel_dig_port->base; struct intel_dp *intel_dp = &intel_dig_port->dp; + encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port); + switch (intel_dig_port->port) { case PORT_A: - encoder->hpd_pin = HPD_PORT_A; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A; break; case PORT_B: - encoder->hpd_pin = HPD_PORT_B; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B; break; case PORT_C: - encoder->hpd_pin = HPD_PORT_C; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C; break; case PORT_D: - encoder->hpd_pin = HPD_PORT_D; intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; break; case PORT_E: - encoder->hpd_pin = HPD_PORT_E; - /* FIXME: Check VBT for actual wiring of PORT E */ intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; break; diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index b25cd88fc1c5..d2830ba3162e 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -173,24 +173,6 @@ static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) return true; } -/* -* Set minimum / maximum dynamic brightness percentage. This value is expressed -* as the percentage of normal brightness in 5% increments. -*/ -static bool -intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp, - u32 min, u32 max) -{ - u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5) }; - - if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, - dbc, sizeof(dbc)) < 0) { - DRM_DEBUG_KMS("Failed to write aux DBC brightness level\n"); - return false; - } - return true; -} - static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { @@ -226,14 +208,6 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st if (intel_dp_aux_set_pwm_freq(connector)) new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; - if (i915.enable_dbc && - (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) { - if(intel_dp_aux_set_dynamic_backlight_percent(intel_dp, 0, 100)) { - new_dpcd_buf |= DP_EDP_DYNAMIC_BACKLIGHT_ENABLE; - DRM_DEBUG_KMS("Enable dynamic brightness.\n"); - } - } - if (new_dpcd_buf != dpcd_buf) { if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) { @@ -277,66 +251,15 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) /* Check the eDP Display control capabilities registers to determine if * the panel can support backlight control over the aux channel */ - if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) && - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) { + if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP && + (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) && + !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { DRM_DEBUG_KMS("AUX Backlight Control Supported!\n"); return true; } return false; } -/* - * Heuristic function whether we should use AUX for backlight adjustment or not. - * - * We should use AUX for backlight brightness adjustment if panel doesn't this - * via PWM pin or using AUX is better than using PWM pin. - * - * The heuristic to determine that using AUX pin is better than using PWM pin is - * that the panel support any of the feature list here. - * - Regional backlight brightness adjustment - * - Backlight PWM frequency set - * - More than 8 bits resolution of brightness level - * - Backlight enablement via AUX and not by BL_ENABLE pin - * - * If all above are not true, assume that using PWM pin is better. - */ -static bool -intel_dp_aux_display_control_heuristic(struct intel_connector *connector) -{ - struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); - uint8_t reg_val; - - /* Panel doesn't support adjusting backlight brightness via PWN pin */ - if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) - return true; - - /* Panel supports regional backlight brightness adjustment */ - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_GENERAL_CAP_3, - ®_val) != 1) { - DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", - DP_EDP_GENERAL_CAP_3); - return false; - } - if (reg_val > 0) - return true; - - /* Panel supports backlight PWM frequency set */ - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) - return true; - - /* Panel supports more than 8 bits resolution of brightness level */ - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) - return true; - - /* Panel supports enabling backlight via AUX but not by BL_ENABLE pin */ - if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) && - !(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP)) - return true; - - return false; - -} - int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) { struct intel_panel *panel = &intel_connector->panel; @@ -347,10 +270,6 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) if (!intel_dp_aux_display_control_capable(intel_connector)) return -ENODEV; - if (i915.enable_dpcd_backlight == -1 && - !intel_dp_aux_display_control_heuristic(intel_connector)) - return -ENODEV; - panel->backlight.setup = intel_dp_aux_setup_backlight; panel->backlight.enable = intel_dp_aux_enable_backlight; panel->backlight.disable = intel_dp_aux_disable_backlight; diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index b79c1c0e404c..05907fa8a553 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -321,12 +321,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) if (!intel_dp_link_training_channel_equalization(intel_dp)) goto failure_handling; - DRM_DEBUG_KMS("Link Training Passed at Link Rate = %d, Lane count = %d", + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, intel_dp->link_rate, intel_dp->lane_count); return; failure_handling: - DRM_DEBUG_KMS("Link Training failed at link rate = %d, lane count = %d", + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, intel_dp->link_rate, intel_dp->lane_count); if (!intel_dp_get_link_train_fallback_values(intel_dp, intel_dp->link_rate, diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 58568559711a..93fc8ab9bb31 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -370,6 +370,9 @@ intel_dp_mst_mode_valid(struct drm_connector *connector, int bpp = 24; /* MST uses fixed bpp */ int max_rate, mode_rate, max_lanes, max_link_clock; + if (!intel_dp) + return MODE_ERROR; + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 2f7b0e64f628..a2a3d93d67bd 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2379,6 +2379,15 @@ cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, return pll; } +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, + struct intel_dpll_hw_state *hw_state) +{ + DRM_DEBUG_KMS("dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); +} + static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { .enable = cnl_ddi_pll_enable, .disable = cnl_ddi_pll_disable, @@ -2395,7 +2404,7 @@ static const struct dpll_info cnl_plls[] = { static const struct intel_dpll_mgr cnl_pll_mgr = { .dpll_info = cnl_plls, .get_dpll = cnl_get_dpll, - .dump_hw_state = skl_dump_hw_state, + .dump_hw_state = cnl_dump_hw_state, }; /** diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 210a8c63bde8..fa47285918f4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -265,6 +265,7 @@ struct intel_encoder { struct intel_panel { struct drm_display_mode *fixed_mode; + struct drm_display_mode *alt_fixed_mode; struct drm_display_mode *downclock_mode; /* backlight */ @@ -780,6 +781,9 @@ struct intel_crtc_state { /* HDMI High TMDS char rate ratio */ bool hdmi_high_tmds_clock_ratio; + + /* output format is YCBCR 4:2:0 */ + bool ycbcr420; }; struct intel_crtc { @@ -796,9 +800,6 @@ struct intel_crtc { u8 plane_ids_mask; unsigned long long enabled_power_domains; struct intel_overlay *overlay; - struct intel_flip_work *flip_work; - - atomic_t unpin_work_count; /* Display surface base address adjustement for pageflips. Note that on * gen4+ this only adjusts up to a tile, offsets within a tile are @@ -1131,24 +1132,6 @@ intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane) return dev_priv->plane_to_crtc_mapping[plane]; } -struct intel_flip_work { - struct work_struct unpin_work; - struct work_struct mmio_work; - - struct drm_crtc *crtc; - struct i915_vma *old_vma; - struct drm_framebuffer *old_fb; - struct drm_i915_gem_object *pending_flip_obj; - struct drm_pending_vblank_event *event; - atomic_t pending; - u32 flip_count; - u32 gtt_offset; - struct drm_i915_gem_request *flip_queued_req; - u32 flip_queued_vblank; - u32 flip_ready_vblank; - unsigned int rotation; -}; - struct intel_load_detect_pipe { struct drm_atomic_state *restore_state; }; @@ -1210,12 +1193,12 @@ hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable); bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable); void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe); void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder); + enum pipe pch_transcoder); void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); @@ -1250,9 +1233,9 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) int intel_get_crtc_scanline(struct intel_crtc *crtc); void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask); + u8 pipe_mask); void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, - unsigned int pipe_mask); + u8 pipe_mask); void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); @@ -1325,7 +1308,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, /* intel_display.c */ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); -enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc); +enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc); void intel_update_rawclk(struct drm_i915_private *dev_priv); int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); int vlv_get_cck_clock(struct drm_i915_private *dev_priv, @@ -1334,7 +1317,6 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, const char *name, u32 reg); void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); void lpt_disable_iclkip(struct drm_i915_private *dev_priv); -extern const struct drm_plane_funcs intel_plane_funcs; void intel_init_display_hooks(struct drm_i915_private *dev_priv); unsigned int intel_fb_xy_to_linear(int x, int y, const struct intel_plane_state *state, @@ -1407,9 +1389,6 @@ void intel_unpin_fb_vma(struct i915_vma *vma); struct drm_framebuffer * intel_framebuffer_create(struct drm_i915_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd); -void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe); -void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe); -void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe); int intel_prepare_plane_fb(struct drm_plane *plane, struct drm_plane_state *new_state); void intel_cleanup_plane_fb(struct drm_plane *plane, @@ -1596,7 +1575,8 @@ void intel_hpd_poll_init(struct drm_i915_private *dev_priv); #ifdef CONFIG_DRM_FBDEV_EMULATION extern int intel_fbdev_init(struct drm_device *dev); extern void intel_fbdev_initial_config_async(struct drm_device *dev); -extern void intel_fbdev_fini(struct drm_device *dev); +extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv); +extern void intel_fbdev_fini(struct drm_i915_private *dev_priv); extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); extern void intel_fbdev_output_poll_changed(struct drm_device *dev); extern void intel_fbdev_restore_mode(struct drm_device *dev); @@ -1610,7 +1590,11 @@ static inline void intel_fbdev_initial_config_async(struct drm_device *dev) { } -static inline void intel_fbdev_fini(struct drm_device *dev) +static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) +{ +} + +static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) { } @@ -1695,6 +1679,7 @@ void intel_overlay_reset(struct drm_i915_private *dev_priv); /* intel_panel.c */ int intel_panel_init(struct intel_panel *panel, struct drm_display_mode *fixed_mode, + struct drm_display_mode *alt_fixed_mode, struct drm_display_mode *downclock_mode); void intel_panel_fini(struct intel_panel *panel); void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, @@ -1900,7 +1885,7 @@ struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); void intel_pipe_update_start(struct intel_crtc *crtc); -void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work); +void intel_pipe_update_end(struct intel_crtc *crtc); /* intel_tv.c */ void intel_tv_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index b0b3adf016f8..f0c11aec5ea5 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -1849,7 +1849,7 @@ void intel_dsi_init(struct drm_i915_private *dev_priv) connector->display_info.width_mm = fixed_mode->width_mm; connector->display_info.height_mm = fixed_mode->height_mm; - intel_panel_init(&intel_connector->panel, fixed_mode, NULL); + intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL); intel_panel_setup_backlight(connector, INVALID_PIPE); intel_dsi_add_properties(intel_connector); diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c index 6e09ceb71500..150a156f3b1e 100644 --- a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c @@ -46,7 +46,7 @@ static u32 dcs_get_backlight(struct intel_connector *connector) struct intel_encoder *encoder = connector->encoder; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct mipi_dsi_device *dsi_device; - u8 data; + u8 data = 0; enum port port; /* FIXME: Need to take care of 16 bit brightness level */ diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c index 7158c7ce9c09..91c07b0c8db9 100644 --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c @@ -306,7 +306,7 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, if (!gpio_desc) { gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, - "panel", gpio_index, + NULL, gpio_index, value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH); diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index baf369d2de30..c0a027274c06 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -552,7 +552,7 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) */ intel_panel_init(&intel_connector->panel, intel_dvo_get_current_mode(connector), - NULL); + NULL, NULL); intel_dvo->panel_wants_dither = true; } diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 24db316e0fd1..9ab596941372 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -337,9 +337,6 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) { struct drm_i915_private *dev_priv = engine->i915; - GEM_BUG_ON(!intel_engine_is_idle(engine)); - GEM_BUG_ON(i915_gem_active_isset(&engine->timeline->last_request)); - /* Our semaphore implementation is strictly monotonic (i.e. we proceed * so long as the semaphore value in the register/page is greater * than the sync value), so whenever we reset the seqno, @@ -1283,6 +1280,10 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) if (port_request(&engine->execlist_port[0])) return false; + /* ELSP is empty, but there are ready requests? */ + if (READ_ONCE(engine->execlist_first)) + return false; + /* Ring stopped? */ if (!ring_is_idle(engine)) return false; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 860b8c26d29b..3fca9fa39a8e 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -461,6 +461,8 @@ static void intel_fbc_schedule_activation(struct intel_crtc *crtc) struct intel_fbc_work *work = &fbc->work; WARN_ON(!mutex_is_locked(&fbc->lock)); + if (WARN_ON(!fbc->enabled)) + return; if (drm_crtc_vblank_get(&crtc->base)) { DRM_ERROR("vblank not available for FBC on pipe %c\n", @@ -1216,7 +1218,7 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work) mutex_lock(&fbc->lock); /* Maybe we were scheduled twice. */ - if (fbc->underrun_detected) + if (fbc->underrun_detected || !fbc->enabled) goto out; DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n"); diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 0986ca4f16f1..262e75c00dd2 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -507,8 +507,6 @@ static void intel_fbdev_destroy(struct intel_fbdev *ifbdev) * trying to rectify all the possible error paths leading here. */ - drm_fb_helper_unregister_fbi(&ifbdev->helper); - drm_fb_helper_fini(&ifbdev->helper); if (ifbdev->vma) { @@ -696,8 +694,10 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie) /* Due to peculiar init order wrt to hpd handling this is separate. */ if (drm_fb_helper_initial_config(&ifbdev->helper, - ifbdev->preferred_bpp)) - intel_fbdev_fini(ifbdev->helper.dev); + ifbdev->preferred_bpp)) { + intel_fbdev_unregister(to_i915(ifbdev->helper.dev)); + intel_fbdev_fini(to_i915(ifbdev->helper.dev)); + } } void intel_fbdev_initial_config_async(struct drm_device *dev) @@ -720,9 +720,8 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev) ifbdev->cookie = 0; } -void intel_fbdev_fini(struct drm_device *dev) +void intel_fbdev_unregister(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_fbdev *ifbdev = dev_priv->fbdev; if (!ifbdev) @@ -732,8 +731,17 @@ void intel_fbdev_fini(struct drm_device *dev) if (!current_is_async()) intel_fbdev_sync(ifbdev); + drm_fb_helper_unregister_fbi(&ifbdev->helper); +} + +void intel_fbdev_fini(struct drm_i915_private *dev_priv) +{ + struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev); + + if (!ifbdev) + return; + intel_fbdev_destroy(ifbdev); - dev_priv->fbdev = NULL; } void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index d484862cc7df..5a7cca32c0fa 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -313,11 +313,11 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, * Returns the previous state of underrun reporting. */ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder, + enum pipe pch_transcoder, bool enable) { struct intel_crtc *crtc = - intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder); + intel_get_crtc_for_pipe(dev_priv, pch_transcoder); unsigned long flags; bool old; @@ -390,7 +390,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, * interrupt to avoid an irq storm. */ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, - enum transcoder pch_transcoder) + enum pipe pch_transcoder) { if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, false)) { diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 9b0ece427bdc..d9d87d96fb69 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -324,7 +324,7 @@ hangcheck_get_action(struct intel_engine_cs *engine, if (engine->hangcheck.seqno != hc->seqno) return ENGINE_ACTIVE_SEQNO; - if (i915_seqno_passed(hc->seqno, intel_engine_last_submit(engine))) + if (intel_engine_is_idle(engine)) return ENGINE_IDLE; return engine_stuck(engine, hc->acthd); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index eb0c559b66c1..e8abea7594ec 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -472,12 +472,18 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, return; } + if (crtc_state->ycbcr420) + frame.avi.colorspace = HDMI_COLORSPACE_YUV420; + else + frame.avi.colorspace = HDMI_COLORSPACE_RGB; + drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, crtc_state->limited_color_range ? HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL, intel_hdmi->rgb_quant_range_selectable); + /* TODO: handle pixel repetition for YCBCR420 outputs */ intel_write_infoframe(encoder, crtc_state, &frame); } @@ -1295,6 +1301,9 @@ intel_hdmi_mode_valid(struct drm_connector *connector, if (mode->flags & DRM_MODE_FLAG_DBLCLK) clock *= 2; + if (drm_mode_is_420_only(&connector->display_info, mode)) + clock /= 2; + /* check if we can do 8bpc */ status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); @@ -1330,8 +1339,15 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) if (connector_state->crtc != crtc_state->base.crtc) continue; - if ((info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36) == 0) - return false; + if (crtc_state->ycbcr420) { + const struct drm_hdmi_info *hdmi = &info->hdmi; + + if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) + return false; + } else { + if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) + return false; + } } /* Display Wa #1139 */ @@ -1342,6 +1358,36 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) return true; } +static bool +intel_hdmi_ycbcr420_config(struct drm_connector *connector, + struct intel_crtc_state *config, + int *clock_12bpc, int *clock_8bpc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); + + if (!connector->ycbcr_420_allowed) { + DRM_ERROR("Platform doesn't support YCBCR420 output\n"); + return false; + } + + /* YCBCR420 TMDS rate requirement is half the pixel clock */ + config->port_clock /= 2; + *clock_12bpc /= 2; + *clock_8bpc /= 2; + config->ycbcr420 = true; + + /* YCBCR 420 output conversion needs a scaler */ + if (skl_update_scaler_crtc(config)) { + DRM_DEBUG_KMS("Scaler allocation for output failed\n"); + return false; + } + + intel_pch_panel_fitting(intel_crtc, config, + DRM_MODE_SCALE_FULLSCREEN); + + return true; +} + bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) @@ -1349,7 +1395,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - struct drm_scdc *scdc = &conn_state->connector->display_info.hdmi.scdc; + struct drm_connector *connector = conn_state->connector; + struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; struct intel_digital_connector_state *intel_conn_state = to_intel_digital_connector_state(conn_state); int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; @@ -1379,6 +1426,14 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, clock_12bpc *= 2; } + if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { + if (!intel_hdmi_ycbcr420_config(connector, pipe_config, + &clock_12bpc, &clock_8bpc)) { + DRM_ERROR("Can't support YCBCR420 output\n"); + return false; + } + } + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) pipe_config->has_pch_encoder = true; @@ -1788,45 +1843,114 @@ void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, DRM_DEBUG_KMS("sink scrambling handled\n"); } -static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, - enum port port) +static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { - const struct ddi_vbt_port_info *info = - &dev_priv->vbt.ddi_port_info[port]; u8 ddc_pin; - if (info->alternate_ddc_pin) { - DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", - info->alternate_ddc_pin, port_name(port)); - return info->alternate_ddc_pin; + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_DPB; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_DPC; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_DPD_CHV; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_DPB; + break; } + return ddc_pin; +} + +static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + u8 ddc_pin; switch (port) { case PORT_B: - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_1_BXT; - else - ddc_pin = GMBUS_PIN_DPB; + ddc_pin = GMBUS_PIN_1_BXT; break; case PORT_C: - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_2_BXT; - else - ddc_pin = GMBUS_PIN_DPC; + ddc_pin = GMBUS_PIN_2_BXT; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_1_BXT; + break; + } + return ddc_pin; +} + +static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_1_BXT; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_2_BXT; break; case PORT_D: - if (HAS_PCH_CNP(dev_priv)) - ddc_pin = GMBUS_PIN_4_CNP; - else if (IS_CHERRYVIEW(dev_priv)) - ddc_pin = GMBUS_PIN_DPD_CHV; - else - ddc_pin = GMBUS_PIN_DPD; + ddc_pin = GMBUS_PIN_4_CNP; + break; + default: + MISSING_CASE(port); + ddc_pin = GMBUS_PIN_1_BXT; + break; + } + return ddc_pin; +} + +static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + u8 ddc_pin; + + switch (port) { + case PORT_B: + ddc_pin = GMBUS_PIN_DPB; + break; + case PORT_C: + ddc_pin = GMBUS_PIN_DPC; + break; + case PORT_D: + ddc_pin = GMBUS_PIN_DPD; break; default: MISSING_CASE(port); ddc_pin = GMBUS_PIN_DPB; break; } + return ddc_pin; +} + +static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + const struct ddi_vbt_port_info *info = + &dev_priv->vbt.ddi_port_info[port]; + u8 ddc_pin; + + if (info->alternate_ddc_pin) { + DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", + info->alternate_ddc_pin, port_name(port)); + return info->alternate_ddc_pin; + } + + if (IS_CHERRYVIEW(dev_priv)) + ddc_pin = chv_port_to_ddc_pin(dev_priv, port); + else if (IS_GEN9_LP(dev_priv)) + ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); + else if (HAS_PCH_CNP(dev_priv)) + ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); + else + ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", ddc_pin, port_name(port)); @@ -1860,25 +1984,14 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, connector->doublescan_allowed = 0; connector->stereo_allowed = 1; + if (IS_GEMINILAKE(dev_priv)) + connector->ycbcr_420_allowed = true; + intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); - switch (port) { - case PORT_B: - intel_encoder->hpd_pin = HPD_PORT_B; - break; - case PORT_C: - intel_encoder->hpd_pin = HPD_PORT_C; - break; - case PORT_D: - intel_encoder->hpd_pin = HPD_PORT_D; - break; - case PORT_E: - intel_encoder->hpd_pin = HPD_PORT_E; - break; - default: - MISSING_CASE(port); + if (WARN_ON(port == PORT_A)) return; - } + intel_encoder->hpd_pin = intel_hpd_pin(port); if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_hdmi->write_infoframe = vlv_write_infoframe; diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index f1200272a699..875d5d218d5c 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -76,26 +76,54 @@ * it will use i915_hotplug_work_func where this logic is handled. */ -bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port) +/** + * intel_hpd_port - return port hard associated with certain pin. + * @pin: the hpd pin to get associated port + * + * Return port that is associatade with @pin and PORT_NONE if no port is + * hard associated with that @pin. + */ +enum port intel_hpd_pin_to_port(enum hpd_pin pin) { switch (pin) { case HPD_PORT_A: - *port = PORT_A; - return true; + return PORT_A; case HPD_PORT_B: - *port = PORT_B; - return true; + return PORT_B; case HPD_PORT_C: - *port = PORT_C; - return true; + return PORT_C; case HPD_PORT_D: - *port = PORT_D; - return true; + return PORT_D; case HPD_PORT_E: - *port = PORT_E; - return true; + return PORT_E; + default: + return PORT_NONE; /* no port for this pin */ + } +} + +/** + * intel_hpd_pin - return pin hard associated with certain port. + * @port: the hpd port to get associated pin + * + * Return pin that is associatade with @port and HDP_NONE if no pin is + * hard associated with that @port. + */ +enum hpd_pin intel_hpd_pin(enum port port) +{ + switch (port) { + case PORT_A: + return HPD_PORT_A; + case PORT_B: + return HPD_PORT_B; + case PORT_C: + return HPD_PORT_C; + case PORT_D: + return HPD_PORT_D; + case PORT_E: + return HPD_PORT_E; default: - return false; /* no hpd */ + MISSING_CASE(port); + return HPD_NONE; } } @@ -389,8 +417,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, if (!(BIT(i) & pin_mask)) continue; - is_dig_port = intel_hpd_pin_to_port(i, &port) && - dev_priv->hotplug.irq_port[port]; + port = intel_hpd_pin_to_port(i); + is_dig_port = port != PORT_NONE && + dev_priv->hotplug.irq_port[port]; if (is_dig_port) { bool long_hpd = long_mask & BIT(i); diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 3c9e00d4ba5a..6698826954e1 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -592,7 +592,6 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) int ret; intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); - mutex_lock(&dev_priv->gmbus_mutex); if (bus->force_bit) { ret = i2c_bit_algo.master_xfer(adapter, msgs, num); @@ -604,7 +603,6 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) bus->force_bit |= GMBUS_FORCE_BIT_RETRY; } - mutex_unlock(&dev_priv->gmbus_mutex); intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); return ret; @@ -624,6 +622,39 @@ static const struct i2c_algorithm gmbus_algorithm = { .functionality = gmbus_func }; +static void gmbus_lock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + mutex_lock(&dev_priv->gmbus_mutex); +} + +static int gmbus_trylock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + return mutex_trylock(&dev_priv->gmbus_mutex); +} + +static void gmbus_unlock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_gmbus *bus = to_intel_gmbus(adapter); + struct drm_i915_private *dev_priv = bus->dev_priv; + + mutex_unlock(&dev_priv->gmbus_mutex); +} + +const struct i2c_lock_operations gmbus_lock_ops = { + .lock_bus = gmbus_lock_bus, + .trylock_bus = gmbus_trylock_bus, + .unlock_bus = gmbus_unlock_bus, +}; + /** * intel_gmbus_setup - instantiate all Intel i2c GMBuses * @dev_priv: i915 device private @@ -665,6 +696,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) bus->dev_priv = dev_priv; bus->adapter.algo = &gmbus_algorithm; + bus->adapter.lock_ops = &gmbus_lock_ops; /* * We wish to retry with bit banging diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 699868d81de8..b0738d2b2a7f 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1306,6 +1306,31 @@ static void reset_common_ring(struct intel_engine_cs *engine, { struct execlist_port *port = engine->execlist_port; struct intel_context *ce; + unsigned int n; + + /* + * Catch up with any missed context-switch interrupts. + * + * Ideally we would just read the remaining CSB entries now that we + * know the gpu is idle. However, the CSB registers are sometimes^W + * often trashed across a GPU reset! Instead we have to rely on + * guessing the missed context-switch events by looking at what + * requests were completed. + */ + if (!request) { + for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) + i915_gem_request_put(port_request(&port[n])); + memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); + return; + } + + if (request->ctx != port_request(port)->ctx) { + i915_gem_request_put(port_request(port)); + port[0] = port[1]; + memset(&port[1], 0, sizeof(port[1])); + } + + GEM_BUG_ON(request->ctx != port_request(port)->ctx); /* If the request was innocent, we leave the request in the ELSP * and will try to replay it on restarting. The context image may @@ -1317,7 +1342,7 @@ static void reset_common_ring(struct intel_engine_cs *engine, * and have to at least restore the RING register in the context * image back to the expected values to skip over the guilty request. */ - if (!request || request->fence.error != -EIO) + if (request->fence.error != -EIO) return; /* We want a simple context + ring to execute the breadcrumb update. @@ -1339,15 +1364,6 @@ static void reset_common_ring(struct intel_engine_cs *engine, request->ring->head = request->postfix; intel_ring_update_space(request->ring); - /* Catch up with any missed context-switch interrupts */ - if (request->ctx != port_request(port)->ctx) { - i915_gem_request_put(port_request(port)); - port[0] = port[1]; - memset(&port[1], 0, sizeof(port[1])); - } - - GEM_BUG_ON(request->ctx != port_request(port)->ctx); - /* Reset WaIdleLiteRestore:bdw,skl as well */ request->tail = intel_ring_wrap(request->ring, diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 52b3a1fd4059..57ef5833c427 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -63,7 +63,6 @@ enum { }; /* Logical Rings */ -void intel_logical_ring_stop(struct intel_engine_cs *engine); void intel_logical_ring_cleanup(struct intel_engine_cs *engine); int logical_render_ring_init(struct intel_engine_cs *engine); int logical_xcs_ring_init(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/intel_lspcon.c b/drivers/gpu/drm/i915/intel_lspcon.c index 5abef482eacf..beb9baaf2f2e 100644 --- a/drivers/gpu/drm/i915/intel_lspcon.c +++ b/drivers/gpu/drm/i915/intel_lspcon.c @@ -210,8 +210,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - if (!IS_GEN9(dev_priv)) { - DRM_ERROR("LSPCON is supported on GEN9 only\n"); + if (!HAS_LSPCON(dev_priv)) { + DRM_ERROR("LSPCON is not supported on this platform\n"); return false; } diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 61d557948e21..8e215777c7f4 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -1138,7 +1138,8 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) out: mutex_unlock(&dev->mode_config.mutex); - intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); + intel_panel_init(&intel_connector->panel, fixed_mode, NULL, + downclock_mode); intel_panel_setup_backlight(connector, INVALID_PIPE); lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 2bd03001cc70..98154efcb2f4 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@ -27,6 +27,7 @@ #include <linux/acpi.h> #include <linux/dmi.h> +#include <linux/firmware.h> #include <acpi/video.h> #include <drm/drmP.h> @@ -829,6 +830,10 @@ void intel_opregion_unregister(struct drm_i915_private *dev_priv) memunmap(opregion->rvda); opregion->rvda = NULL; } + if (opregion->vbt_firmware) { + kfree(opregion->vbt_firmware); + opregion->vbt_firmware = NULL; + } opregion->header = NULL; opregion->acpi = NULL; opregion->swsci = NULL; @@ -912,6 +917,43 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = { { } }; +static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) +{ + struct intel_opregion *opregion = &dev_priv->opregion; + const struct firmware *fw = NULL; + const char *name = i915.vbt_firmware; + int ret; + + if (!name || !*name) + return -ENOENT; + + ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); + if (ret) { + DRM_ERROR("Requesting VBT firmware \"%s\" failed (%d)\n", + name, ret); + return ret; + } + + if (intel_bios_is_valid_vbt(fw->data, fw->size)) { + opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL); + if (opregion->vbt_firmware) { + DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", name); + opregion->vbt = opregion->vbt_firmware; + opregion->vbt_size = fw->size; + ret = 0; + } else { + ret = -ENOMEM; + } + } else { + DRM_DEBUG_KMS("Invalid VBT firmware \"%s\"\n", name); + ret = -EINVAL; + } + + release_firmware(fw); + + return ret; +} + int intel_opregion_setup(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; @@ -974,6 +1016,9 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) if (mboxes & MBOX_ASLE_EXT) DRM_DEBUG_DRIVER("ASLE extension supported\n"); + if (intel_load_vbt_firmware(dev_priv) == 0) + goto out; + if (dmi_check_system(intel_no_opregion_vbt)) goto out; diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index b96aed941b97..aace22e7ccac 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -799,9 +799,13 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, if (ret != 0) return ret; + atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto out_pin_section; + } ret = i915_vma_put_fence(vma); if (ret) @@ -886,6 +890,9 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, out_unpin: i915_gem_object_unpin_from_display_plane(vma); +out_pin_section: + atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + return ret; } diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 593349be8b9d..a17b1de7d7e0 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -110,7 +110,8 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, /* Native modes don't need fitting */ if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && - adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) + adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && + !pipe_config->ycbcr420) goto done; switch (fitting_mode) { @@ -1919,11 +1920,13 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) int intel_panel_init(struct intel_panel *panel, struct drm_display_mode *fixed_mode, + struct drm_display_mode *alt_fixed_mode, struct drm_display_mode *downclock_mode) { intel_panel_init_backlight_funcs(panel); panel->fixed_mode = fixed_mode; + panel->alt_fixed_mode = alt_fixed_mode; panel->downclock_mode = downclock_mode; return 0; @@ -1937,6 +1940,10 @@ void intel_panel_fini(struct intel_panel *panel) if (panel->fixed_mode) drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); + if (panel->alt_fixed_mode) + drm_mode_destroy(intel_connector->base.dev, + panel->alt_fixed_mode); + if (panel->downclock_mode) drm_mode_destroy(intel_connector->base.dev, panel->downclock_mode); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 48785ef75d33..ed662937ec3c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -62,6 +62,20 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(CHICKEN_PAR1_1, I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); + /* + * Display WA#0390: skl,bxt,kbl,glk + * + * Must match Sampler, Pixel Back End, and Media + * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31). + * + * Including bits outside the page in the hash would + * require 2 (or 4?) MiB alignment of resources. Just + * assume the defaul hashing mode which only uses bits + * within the page. + */ + I915_WRITE(CHICKEN_PAR1_1, + I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE); + I915_WRITE(GEN8_CONFIG0, I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); @@ -78,6 +92,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_DISABLE_DUMMY0); + + if (IS_SKYLAKE(dev_priv)) { + /* WaDisableDopClockGating */ + I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) + & ~GEN7_DOP_CLOCK_GATE_ENABLE); + } } static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) @@ -2758,7 +2778,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) static void intel_read_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[8]) { - if (IS_GEN9(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 9) { uint32_t val; int ret, i; int level, max_level = ilk_wm_max_level(dev_priv); @@ -2818,7 +2838,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, } /* - * WaWmMemoryReadLatency:skl,glk + * WaWmMemoryReadLatency:skl+,glk * * punit doesn't take into account the read latency so we need * to add 2us to the various latency levels we retrieve from the @@ -2857,6 +2877,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, wm[0] = 7; wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; + } else { + MISSING_CASE(INTEL_DEVID(dev_priv)); } } @@ -2912,7 +2934,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, * - latencies are in us on gen9. * - before then, WM1+ latency values are in 0.5us units */ - if (IS_GEN9(dev_priv)) + if (INTEL_GEN(dev_priv) >= 9) latency *= 10; else if (level > 0) latency *= 5; @@ -3530,8 +3552,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev) return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); } -#define SKL_SAGV_BLOCK_TIME 30 /* µs */ - /* * FIXME: We still don't have the proper code detect if we need to apply the WA, * so assume we'll always need it in order to avoid underruns. @@ -3549,7 +3569,8 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || + IS_CANNONLAKE(dev_priv)) return true; if (IS_SKYLAKE(dev_priv) && @@ -3655,12 +3676,13 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) struct intel_crtc_state *cstate; enum pipe pipe; int level, latency; + int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20; if (!intel_has_sagv(dev_priv)) return false; /* - * SKL workaround: bspec recommends we disable the SAGV when we have + * SKL+ workaround: bspec recommends we disable the SAGV when we have * more then one pipe enabled * * If there are no active CRTCs, no additional checks need be performed @@ -3699,11 +3721,11 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) latency += 15; /* - * If any of the planes on this pipe don't enable wm levels - * that incur memory latencies higher then 30µs we can't enable - * the SAGV + * If any of the planes on this pipe don't enable wm levels that + * incur memory latencies higher than sagv_block_time_us we + * can't enable the SAGV. */ - if (latency < SKL_SAGV_BLOCK_TIME) + if (latency < sagv_block_time_us) return false; } @@ -4071,7 +4093,9 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, /* For Non Y-tile return 8-blocks */ if (fb->modifier != I915_FORMAT_MOD_Y_TILED && - fb->modifier != I915_FORMAT_MOD_Yf_TILED) + fb->modifier != I915_FORMAT_MOD_Yf_TILED && + fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS && + fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS) return 8; /* @@ -4266,8 +4290,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, * should allow pixel_rate up to ~2 GHz which seems sufficient since max * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. */ -static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, - uint32_t latency) +static uint_fixed_16_16_t +skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, + uint8_t cpp, uint32_t latency) { uint32_t wm_intermediate_val; uint_fixed_16_16_t ret; @@ -4277,6 +4302,10 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, wm_intermediate_val = latency * pixel_rate * cpp; ret = div_fixed16(wm_intermediate_val, 1000 * 512); + + if (INTEL_GEN(dev_priv) >= 10) + ret = add_fixed16_u32(ret, 1); + return ret; } @@ -4377,7 +4406,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, } y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || - fb->modifier == I915_FORMAT_MOD_Yf_TILED; + fb->modifier == I915_FORMAT_MOD_Yf_TILED || + fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS; x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; /* Display WA #1141: kbl,cfl */ @@ -4430,9 +4461,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, if (y_tiled) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512); + + if (INTEL_GEN(dev_priv) >= 10) + interm_pbpl++; + plane_blocks_per_line = div_fixed16(interm_pbpl, y_min_scanlines); - } else if (x_tiled) { + } else if (x_tiled && INTEL_GEN(dev_priv) == 9) { interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); plane_blocks_per_line = u32_to_fixed16(interm_pbpl); } else { @@ -4440,7 +4475,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, plane_blocks_per_line = u32_to_fixed16(interm_pbpl); } - method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); + method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency); method2 = skl_wm_method2(plane_pixel_rate, cstate->base.adjusted_mode.crtc_htotal, latency, @@ -4472,6 +4507,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, res_lines = div_round_up_fixed16(selected_result, plane_blocks_per_line); + /* Display WA #1125: skl,bxt,kbl,glk */ + if (level == 0 && + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) + res_blocks += fixed16_to_u32_round_up(y_tile_minimum); + + /* Display WA #1126: skl,bxt,kbl,glk */ if (level >= 1 && level <= 7) { if (y_tiled) { res_blocks += fixed16_to_u32_round_up(y_tile_minimum); @@ -8831,6 +8873,7 @@ static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) case GEN6_PCODE_SUCCESS: return 0; case GEN6_PCODE_UNIMPLEMENTED_CMD: + return -ENODEV; case GEN6_PCODE_ILLEGAL_CMD: return -ENXIO; case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: @@ -8878,7 +8921,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val */ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n", + mbox, __builtin_return_address(0)); return -EAGAIN; } @@ -8889,7 +8933,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val if (__intel_wait_for_register_fw(dev_priv, GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); + DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n", + mbox, __builtin_return_address(0)); return -ETIMEDOUT; } @@ -8902,8 +8947,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val status = gen6_check_mailbox_status(dev_priv); if (status) { - DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n", - status); + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n", + mbox, __builtin_return_address(0), status); return status; } @@ -8923,7 +8968,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, */ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { - DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n", + val, mbox, __builtin_return_address(0)); return -EAGAIN; } @@ -8934,7 +8980,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, if (__intel_wait_for_register_fw(dev_priv, GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, 500, 0, NULL)) { - DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); + DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n", + val, mbox, __builtin_return_address(0)); return -ETIMEDOUT; } @@ -8946,8 +8993,8 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, status = gen6_check_mailbox_status(dev_priv); if (status) { - DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n", - status); + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n", + val, mbox, __builtin_return_address(0), status); return status; } diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 559f1ab42bfc..1b31ab002dae 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TP2_SEL; + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; I915_WRITE(EDP_PSR_CTL, val); } diff --git a/drivers/gpu/drm/i915/intel_renderstate_gen9.c b/drivers/gpu/drm/i915/intel_renderstate_gen9.c index 16a7ec273bd9..7d3ac02f0177 100644 --- a/drivers/gpu/drm/i915/intel_renderstate_gen9.c +++ b/drivers/gpu/drm/i915/intel_renderstate_gen9.c @@ -20,7 +20,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * - * Generated by: intel-gpu-tools-1.8-220-g01153e7 + * Generated by: intel-gpu-tools-1.19-177-g68e2eab2 */ #include "intel_renderstate.h" @@ -873,7 +873,7 @@ static const u32 gen9_null_state_batch[] = { 0x00000000, 0x00000000, 0x78550003, - 0x00000000, + 0x0000000f, 0x00000000, 0x00000000, 0x00000000, diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5224b7abb8a3..cdf084ef5aae 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1712,6 +1712,9 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, unsigned int total_bytes; u32 *cs; + /* Packets must be qword aligned. */ + GEM_BUG_ON(num_dwords & 1); + total_bytes = bytes + req->reserved_space; GEM_BUG_ON(total_bytes > ring->effective_size); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index d33c93444c0d..02d8974bf9ab 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -735,4 +735,16 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv); void intel_engines_mark_idle(struct drm_i915_private *i915); void intel_engines_reset_default_submission(struct drm_i915_private *i915); +static inline bool +__intel_engine_can_store_dword(unsigned int gen, unsigned int class) +{ + if (gen <= 2) + return false; /* uses physical not virtual addresses */ + + if (gen == 6 && class == VIDEO_DECODE_CLASS) + return false; /* b0rked */ + + return true; +} + #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index f630d632a976..b66d8e136aa3 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -50,10 +50,11 @@ */ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, - int power_well_id); + enum i915_power_well_id power_well_id); static struct i915_power_well * -lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id); +lookup_power_well(struct drm_i915_private *dev_priv, + enum i915_power_well_id power_well_id); const char * intel_display_power_domain_str(enum intel_display_power_domain domain) @@ -168,18 +169,6 @@ static void intel_power_well_put(struct drm_i915_private *dev_priv, intel_power_well_disable(dev_priv, power_well); } -/* - * We should only use the power well if we explicitly asked the hardware to - * enable it, so check if it's enabled and also check if we've requested it to - * be enabled. - */ -static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - return I915_READ(HSW_PWR_WELL_DRIVER) == - (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); -} - /** * __intel_display_power_is_enabled - unlocked check for a power domain * @dev_priv: i915 device instance @@ -278,7 +267,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv, * to be enabled, and it will only be disabled if none of the registers is * requesting it to be enabled. */ -static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) +static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, + u8 irq_pipe_mask, bool has_vga) { struct pci_dev *pdev = dev_priv->drm.pdev; @@ -292,85 +282,55 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) * sure vgacon can keep working normally without triggering interrupts * and error messages. */ - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); - vga_put(pdev, VGA_RSRC_LEGACY_IO); - - if (IS_BROADWELL(dev_priv)) - gen8_irq_power_well_post_enable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); -} - -static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) -{ - if (IS_BROADWELL(dev_priv)) - gen8_irq_power_well_pre_disable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); -} - -static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - struct pci_dev *pdev = dev_priv->drm.pdev; - - /* - * After we re-enable the power well, if we touch VGA register 0x3d5 - * we'll get unclaimed register interrupts. This stops after we write - * anything to the VGA MSR register. The vgacon module uses this - * register all the time, so if we unbind our driver and, as a - * consequence, bind vgacon, we'll get stuck in an infinite loop at - * console_unlock(). So make here we touch the VGA MSR register, making - * sure vgacon can keep working normally without triggering interrupts - * and error messages. - */ - if (power_well->id == SKL_DISP_PW_2) { + if (has_vga) { vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); vga_put(pdev, VGA_RSRC_LEGACY_IO); - - gen8_irq_power_well_post_enable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); } + + if (irq_pipe_mask) + gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); } -static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, + u8 irq_pipe_mask) { - if (power_well->id == SKL_DISP_PW_2) - gen8_irq_power_well_pre_disable(dev_priv, - 1 << PIPE_C | 1 << PIPE_B); + if (irq_pipe_mask) + gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); } -static void gen9_wait_for_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) + +static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { - int id = power_well->id; + enum i915_power_well_id id = power_well->id; /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ WARN_ON(intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - SKL_POWER_WELL_STATE(id), - SKL_POWER_WELL_STATE(id), + HSW_PWR_WELL_CTL_DRIVER(id), + HSW_PWR_WELL_CTL_STATE(id), + HSW_PWR_WELL_CTL_STATE(id), 1)); } -static u32 gen9_power_well_requesters(struct drm_i915_private *dev_priv, int id) +static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, + enum i915_power_well_id id) { - u32 req_mask = SKL_POWER_WELL_REQ(id); + u32 req_mask = HSW_PWR_WELL_CTL_REQ(id); u32 ret; - ret = I915_READ(HSW_PWR_WELL_BIOS) & req_mask ? 1 : 0; - ret |= I915_READ(HSW_PWR_WELL_DRIVER) & req_mask ? 2 : 0; - ret |= I915_READ(HSW_PWR_WELL_KVMR) & req_mask ? 4 : 0; - ret |= I915_READ(HSW_PWR_WELL_DEBUG) & req_mask ? 8 : 0; + ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; + ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; return ret; } -static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) +static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) { - int id = power_well->id; + enum i915_power_well_id id = power_well->id; bool disabled; u32 reqs; @@ -383,9 +343,9 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, * Skip the wait in case any of the request bits are set and print a * diagnostic message. */ - wait_for((disabled = !(I915_READ(HSW_PWR_WELL_DRIVER) & - SKL_POWER_WELL_STATE(id))) || - (reqs = gen9_power_well_requesters(dev_priv, id)), 1); + wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & + HSW_PWR_WELL_CTL_STATE(id))) || + (reqs = hsw_power_well_requesters(dev_priv, id)), 1); if (disabled) return; @@ -394,216 +354,85 @@ static void gen9_wait_for_power_well_disable(struct drm_i915_private *dev_priv, !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); } -static void hsw_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) +static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, + enum skl_power_gate pg) { - bool is_enabled, enable_requested; - uint32_t tmp; + /* Timeout 5us for PG#0, for other PGs 1us */ + WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, + SKL_FUSE_PG_DIST_STATUS(pg), + SKL_FUSE_PG_DIST_STATUS(pg), 1)); +} - tmp = I915_READ(HSW_PWR_WELL_DRIVER); - is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; - enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; - - if (enable) { - if (!enable_requested) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling power well\n"); - if (intel_wait_for_register(dev_priv, - HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_STATE_ENABLED, - HSW_PWR_WELL_STATE_ENABLED, - 20)) - DRM_ERROR("Timeout enabling power well\n"); - hsw_power_well_post_enable(dev_priv); - } +static void hsw_power_well_enable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + bool wait_fuses = power_well->hsw.has_fuses; + enum skl_power_gate pg; + u32 val; - } else { - if (enable_requested) { - hsw_power_well_pre_disable(dev_priv); - I915_WRITE(HSW_PWR_WELL_DRIVER, 0); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Requesting to disable the power well\n"); - } + if (wait_fuses) { + pg = SKL_PW_TO_PG(id); + /* + * For PW1 we have to wait both for the PW0/PG0 fuse state + * before enabling the power well and PW1/PG1's own fuse + * state after the enabling. For all other power wells with + * fuses we only have to wait for that PW/PG's fuse state + * after the enabling. + */ + if (pg == SKL_PG1) + gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); } + + val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id)); + hsw_wait_for_power_well_enable(dev_priv, power_well); + + if (wait_fuses) + gen9_wait_for_power_well_fuses(dev_priv, pg); + + hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, + power_well->hsw.has_vga); } -#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) +static void hsw_power_well_disable(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + u32 val; -#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_GMBUS) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) + hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); -#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) -#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) -#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) -#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) + val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), + val & ~HSW_PWR_WELL_CTL_REQ(id)); + hsw_wait_for_power_well_disable(dev_priv, power_well); +} -#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_B) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_C) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_AUX_D) | \ - BIT_ULL(POWER_DOMAIN_INIT)) -#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ - BIT_ULL(POWER_DOMAIN_MODESET) | \ - BIT_ULL(POWER_DOMAIN_AUX_A) | \ - BIT_ULL(POWER_DOMAIN_INIT)) +/* + * We should only use the power well if we explicitly asked the hardware to + * enable it, so check if it's enabled and also check if we've requested it to + * be enabled. + */ +static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id) | HSW_PWR_WELL_CTL_STATE(id); + + return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; +} static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) { + enum i915_power_well_id id = SKL_DISP_PW_2; + WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), "DC9 already programmed to be enabled.\n"); WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, "DC5 still not disabled to enable DC9.\n"); - WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) & - SKL_POWER_WELL_REQ(SKL_DISP_PW_2), + WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & + HSW_PWR_WELL_CTL_REQ(id), "Power well 2 on.\n"); WARN_ONCE(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); @@ -799,181 +628,39 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); } -static void skl_set_power_well(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well, bool enable) -{ - uint32_t tmp, fuse_status; - uint32_t req_mask, state_mask; - bool is_enabled, enable_requested, check_fuse_status = false; - - tmp = I915_READ(HSW_PWR_WELL_DRIVER); - fuse_status = I915_READ(SKL_FUSE_STATUS); - - switch (power_well->id) { - case SKL_DISP_PW_1: - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG0_DIST_STATUS, - SKL_FUSE_PG0_DIST_STATUS, - 1)) { - DRM_ERROR("PG0 not enabled\n"); - return; - } - break; - case SKL_DISP_PW_2: - if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { - DRM_ERROR("PG1 in disabled state\n"); - return; - } - break; - case SKL_DISP_PW_MISC_IO: - case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */ - case SKL_DISP_PW_DDI_B: - case SKL_DISP_PW_DDI_C: - case SKL_DISP_PW_DDI_D: - case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */ - case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */ - case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */ - case CNL_DISP_PW_AUX_D: - break; - default: - WARN(1, "Unknown power well %lu\n", power_well->id); - return; - } - - req_mask = SKL_POWER_WELL_REQ(power_well->id); - enable_requested = tmp & req_mask; - state_mask = SKL_POWER_WELL_STATE(power_well->id); - is_enabled = tmp & state_mask; - - if (!enable && enable_requested) - skl_power_well_pre_disable(dev_priv, power_well); - - if (enable) { - if (!enable_requested) { - WARN((tmp & state_mask) && - !I915_READ(HSW_PWR_WELL_BIOS), - "Invalid for power well status to be enabled, unless done by the BIOS, \ - when request is to disable!\n"); - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); - } - - if (!is_enabled) { - DRM_DEBUG_KMS("Enabling %s\n", power_well->name); - check_fuse_status = true; - } - - gen9_wait_for_power_well_enable(dev_priv, power_well); - } else { - if (enable_requested) { - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); - } - - gen9_wait_for_power_well_disable(dev_priv, power_well); - } - - if (check_fuse_status) { - if (power_well->id == SKL_DISP_PW_1) { - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG1_DIST_STATUS, - SKL_FUSE_PG1_DIST_STATUS, - 1)) - DRM_ERROR("PG1 distributing status timeout\n"); - } else if (power_well->id == SKL_DISP_PW_2) { - if (intel_wait_for_register(dev_priv, - SKL_FUSE_STATUS, - SKL_FUSE_PG2_DIST_STATUS, - SKL_FUSE_PG2_DIST_STATUS, - 1)) - DRM_ERROR("PG2 distributing status timeout\n"); - } - } - - if (enable && !is_enabled) - skl_power_well_post_enable(dev_priv, power_well); -} - static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - /* Take over the request bit if set by BIOS. */ - if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) { - if (!(I915_READ(HSW_PWR_WELL_DRIVER) & - HSW_PWR_WELL_ENABLE_REQUEST)) - I915_WRITE(HSW_PWR_WELL_DRIVER, - HSW_PWR_WELL_ENABLE_REQUEST); - I915_WRITE(HSW_PWR_WELL_BIOS, 0); - } -} - -static void hsw_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - hsw_set_power_well(dev_priv, power_well, true); -} - -static void hsw_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - hsw_set_power_well(dev_priv, power_well, false); -} - -static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - uint32_t mask = SKL_POWER_WELL_REQ(power_well->id) | - SKL_POWER_WELL_STATE(power_well->id); - - return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; -} - -static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - uint32_t mask = SKL_POWER_WELL_REQ(power_well->id); - uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS); + enum i915_power_well_id id = power_well->id; + u32 mask = HSW_PWR_WELL_CTL_REQ(id); + u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)); /* Take over the request bit if set by BIOS. */ if (bios_req & mask) { - uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER); + u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); if (!(drv_req & mask)) - I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask); - I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask); + I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), drv_req | mask); + I915_WRITE(HSW_PWR_WELL_CTL_BIOS(id), bios_req & ~mask); } } -static void skl_power_well_enable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - skl_set_power_well(dev_priv, power_well, true); -} - -static void skl_power_well_disable(struct drm_i915_private *dev_priv, - struct i915_power_well *power_well) -{ - skl_set_power_well(dev_priv, power_well, false); -} - static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - bxt_ddi_phy_init(dev_priv, power_well->data); + bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); } static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - bxt_ddi_phy_uninit(dev_priv, power_well->data); + bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); } static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return bxt_ddi_phy_is_enabled(dev_priv, power_well->data); + return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); } static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) @@ -982,16 +669,16 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); if (IS_GEMINILAKE(dev_priv)) { power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); if (power_well->count > 0) - bxt_ddi_phy_verify_state(dev_priv, power_well->data); + bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); } } @@ -1089,7 +776,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, static void vlv_set_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum punit_power_well power_well_id = power_well->id; + enum i915_power_well_id power_well_id = power_well->id; u32 mask; u32 state; u32 ctrl; @@ -1137,7 +824,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv, static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - int power_well_id = power_well->id; + enum i915_power_well_id power_well_id = power_well->id; bool enabled = false; u32 mask; u32 state; @@ -1324,8 +1011,9 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0)) -static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, - int power_well_id) +static struct i915_power_well * +lookup_power_well(struct drm_i915_private *dev_priv, + enum i915_power_well_id power_well_id) { struct i915_power_domains *power_domains = &dev_priv->power_domains; int i; @@ -1672,7 +1360,7 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - enum pipe pipe = power_well->id; + enum pipe pipe = PIPE_A; bool enabled; u32 state, ctrl; @@ -1702,7 +1390,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, bool enable) { - enum pipe pipe = power_well->id; + enum pipe pipe = PIPE_A; u32 state; u32 ctrl; @@ -1735,7 +1423,7 @@ out: static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN_ON_ONCE(power_well->id != PIPE_A); + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); chv_set_pipe_power_well(dev_priv, power_well, true); @@ -1745,7 +1433,7 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN_ON_ONCE(power_well->id != PIPE_A); + WARN_ON_ONCE(power_well->id != CHV_DISP_PW_PIPE_A); vlv_display_power_well_deinit(dev_priv); @@ -1861,37 +1549,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, intel_runtime_pm_put(dev_priv); } -#define HSW_DISPLAY_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ - BIT_ULL(POWER_DOMAIN_INIT)) - -#define BDW_DISPLAY_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ - BIT_ULL(POWER_DOMAIN_VGA) | \ - BIT_ULL(POWER_DOMAIN_AUDIO) | \ +#define I830_PIPES_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ BIT_ULL(POWER_DOMAIN_INIT)) #define VLV_DISPLAY_POWER_DOMAINS ( \ @@ -1974,13 +1638,201 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_AUX_D) | \ BIT_ULL(POWER_DOMAIN_INIT)) -#define I830_PIPES_POWER_DOMAINS ( \ - BIT_ULL(POWER_DOMAIN_PIPE_A) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B) | \ - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ +#define HSW_DISPLAY_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define BDW_DISPLAY_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_GMBUS) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)) +#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)) +#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)) +#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_C) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_INIT)) +#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_INIT)) static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { @@ -2010,6 +1862,7 @@ static struct i915_power_well i9xx_always_on_power_well[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, }; @@ -2026,11 +1879,13 @@ static struct i915_power_well i830_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "pipes", .domains = I830_PIPES_POWER_DOMAINS, .ops = &i830_pipes_power_well_ops, + .id = I830_DISP_PW_PIPES, }, }; @@ -2041,13 +1896,6 @@ static const struct i915_power_well_ops hsw_power_well_ops = { .is_enabled = hsw_power_well_enabled, }; -static const struct i915_power_well_ops skl_power_well_ops = { - .sync_hw = skl_power_well_sync_hw, - .enable = skl_power_well_enable, - .disable = skl_power_well_disable, - .is_enabled = skl_power_well_enabled, -}; - static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = gen9_dc_off_power_well_enable, @@ -2068,11 +1916,16 @@ static struct i915_power_well hsw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", .domains = HSW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, + .id = HSW_DISP_PW_GLOBAL, + { + .hsw.has_vga = true, + }, }, }; @@ -2082,11 +1935,17 @@ static struct i915_power_well bdw_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", .domains = BDW_DISPLAY_POWER_DOMAINS, .ops = &hsw_power_well_ops, + .id = HSW_DISP_PW_GLOBAL, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + }, }, }; @@ -2117,7 +1976,7 @@ static struct i915_power_well vlv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = PUNIT_POWER_WELL_ALWAYS_ON, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2175,6 +2034,7 @@ static struct i915_power_well chv_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "display", @@ -2184,7 +2044,7 @@ static struct i915_power_well chv_power_wells[] = { * required for any pipe to work. */ .domains = CHV_DISPLAY_POWER_DOMAINS, - .id = PIPE_A, + .id = CHV_DISP_PW_PIPE_A, .ops = &chv_pipe_power_well_ops, }, { @@ -2202,7 +2062,7 @@ static struct i915_power_well chv_power_wells[] = { }; bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, - int power_well_id) + enum i915_power_well_id power_well_id) { struct i915_power_well *power_well; bool ret; @@ -2219,20 +2079,23 @@ static struct i915_power_well skl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, - .id = SKL_DISP_PW_ALWAYS_ON, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "MISC IO power well", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_MISC_IO, }, { @@ -2244,31 +2107,36 @@ static struct i915_power_well skl_power_wells[] = { { .name = "power well 2", .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "DDI A/E IO power well", .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_A_E, }, { .name = "DDI B IO power well", .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, { .name = "DDI D IO power well", .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_D, }, }; @@ -2279,12 +2147,16 @@ static struct i915_power_well bxt_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "DC off", @@ -2295,22 +2167,31 @@ static struct i915_power_well bxt_power_wells[] = { { .name = "power well 2", .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "dpio-common-a", .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .data = DPIO_PHY1, + { + .bxt.phy = DPIO_PHY1, + }, }, { .name = "dpio-common-bc", .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .data = DPIO_PHY0, + { + .bxt.phy = DPIO_PHY0, + }, }, }; @@ -2320,13 +2201,17 @@ static struct i915_power_well glk_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "DC off", @@ -2337,64 +2222,75 @@ static struct i915_power_well glk_power_wells[] = { { .name = "power well 2", .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "dpio-common-a", .domains = GLK_DPIO_CMN_A_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_A, - .data = DPIO_PHY1, + { + .bxt.phy = DPIO_PHY1, + }, }, { .name = "dpio-common-b", .domains = GLK_DPIO_CMN_B_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = BXT_DPIO_CMN_BC, - .data = DPIO_PHY0, + { + .bxt.phy = DPIO_PHY0, + }, }, { .name = "dpio-common-c", .domains = GLK_DPIO_CMN_C_POWER_DOMAINS, .ops = &bxt_dpio_cmn_power_well_ops, .id = GLK_DPIO_CMN_C, - .data = DPIO_PHY2, + { + .bxt.phy = DPIO_PHY2, + }, }, { .name = "AUX A", .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_A, }, { .name = "AUX B", .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_B, }, { .name = "AUX C", .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_AUX_C, }, { .name = "DDI A IO power well", .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = GLK_DISP_PW_DDI_A, }, { .name = "DDI B IO power well", .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, }; @@ -2405,36 +2301,40 @@ static struct i915_power_well cnl_power_wells[] = { .always_on = 1, .domains = POWER_DOMAIN_MASK, .ops = &i9xx_always_on_power_well_ops, + .id = I915_DISP_PW_ALWAYS_ON, }, { .name = "power well 1", /* Handled by the DMC firmware */ .domains = 0, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_1, + { + .hsw.has_fuses = true, + }, }, { .name = "AUX A", .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_A, }, { .name = "AUX B", .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_B, }, { .name = "AUX C", .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_C, }, { .name = "AUX D", .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_AUX_D, }, { @@ -2446,31 +2346,36 @@ static struct i915_power_well cnl_power_wells[] = { { .name = "power well 2", .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_2, + { + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, }, { .name = "DDI A IO power well", .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = CNL_DISP_PW_DDI_A, }, { .name = "DDI B IO power well", .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C IO power well", .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, { .name = "DDI D IO power well", .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &hsw_power_well_ops, .id = SKL_DISP_PW_DDI_D, }, }; @@ -2534,6 +2439,22 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, return mask; } +static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) +{ + struct i915_power_domains *power_domains = &dev_priv->power_domains; + u64 power_well_ids; + int i; + + power_well_ids = 0; + for (i = 0; i < power_domains->power_well_count; i++) { + enum i915_power_well_id id = power_domains->power_wells[i].id; + + WARN_ON(id >= sizeof(power_well_ids) * 8); + WARN_ON(power_well_ids & BIT_ULL(id)); + power_well_ids |= BIT_ULL(id); + } +} + #define set_power_wells(power_domains, __power_wells) ({ \ (power_domains)->power_wells = (__power_wells); \ (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ @@ -2585,6 +2506,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) set_power_wells(power_domains, i9xx_always_on_power_well); } + assert_power_well_ids_unique(dev_priv); + return 0; } @@ -2820,7 +2743,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 2. Enable Comp */ val = I915_READ(CHICKEN_MISC_2); - val &= ~COMP_PWR_DOWN; + val &= ~CNL_COMP_PWR_DOWN; I915_WRITE(CHICKEN_MISC_2, val); val = I915_READ(CNL_PORT_COMP_DW3); @@ -2894,7 +2817,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) /* 5. Disable Comp */ val = I915_READ(CHICKEN_MISC_2); - val |= COMP_PWR_DOWN; + val |= CNL_COMP_PWR_DOWN; I915_WRITE(CHICKEN_MISC_2, val); } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index bea8152ae859..3dc38c2ef4c3 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -451,23 +451,24 @@ static const char * const cmd_status_names[] = { "Scaling not supported" }; -static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, - const void *args, int args_len) +static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, + const void *args, int args_len, + bool unlocked) { u8 *buf, status; struct i2c_msg *msgs; int i, ret = true; - /* Would be simpler to allocate both in one go ? */ + /* Would be simpler to allocate both in one go ? */ buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); if (!buf) return false; msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); if (!msgs) { - kfree(buf); + kfree(buf); return false; - } + } intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); @@ -498,7 +499,10 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, msgs[i+2].len = 1; msgs[i+2].buf = &status; - ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); + if (unlocked) + ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); + else + ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); if (ret < 0) { DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); ret = false; @@ -516,6 +520,12 @@ out: return ret; } +static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, + const void *args, int args_len) +{ + return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true); +} + static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, void *response, int response_len) { @@ -602,13 +612,13 @@ static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjust return 4; } -static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, - u8 ddc_bus) +static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, + u8 ddc_bus) { /* This must be the immediately preceding write before the i2c xfer */ - return intel_sdvo_write_cmd(intel_sdvo, - SDVO_CMD_SET_CONTROL_BUS_SWITCH, - &ddc_bus, 1); + return __intel_sdvo_write_cmd(intel_sdvo, + SDVO_CMD_SET_CONTROL_BUS_SWITCH, + &ddc_bus, 1, false); } static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) @@ -1349,8 +1359,10 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, else sdvox |= SDVO_PIPE_SEL(crtc->pipe); - if (crtc_state->has_audio) + if (crtc_state->has_audio) { + WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4); sdvox |= SDVO_AUDIO_ENABLE; + } if (INTEL_GEN(dev_priv) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ @@ -1480,6 +1492,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, if (sdvox & HDMI_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; + if (sdvox & SDVO_AUDIO_ENABLE) + pipe_config->has_audio = true; + if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, &val, 1)) { if (val == SDVO_ENCODE_HDMI) @@ -2453,6 +2468,7 @@ static bool intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) { struct drm_encoder *encoder = &intel_sdvo->base.base; + struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct drm_connector *connector; struct intel_encoder *intel_encoder = to_intel_encoder(encoder); struct intel_connector *intel_connector; @@ -2488,7 +2504,9 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) encoder->encoder_type = DRM_MODE_ENCODER_TMDS; connector->connector_type = DRM_MODE_CONNECTOR_DVID; - if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { + /* gen3 doesn't do the hdmi bits in the SDVO register */ + if (INTEL_GEN(dev_priv) >= 4 && + intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; intel_sdvo->is_hdmi = true; } @@ -2924,7 +2942,7 @@ static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, { struct intel_sdvo *sdvo = adapter->algo_data; - if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) + if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) return -EIO; return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); @@ -2941,6 +2959,33 @@ static const struct i2c_algorithm intel_sdvo_ddc_proxy = { .functionality = intel_sdvo_ddc_proxy_func }; +static void proxy_lock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); +} + +static int proxy_trylock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); +} + +static void proxy_unlock_bus(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct intel_sdvo *sdvo = adapter->algo_data; + sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); +} + +const struct i2c_lock_operations proxy_lock_ops = { + .lock_bus = proxy_lock_bus, + .trylock_bus = proxy_trylock_bus, + .unlock_bus = proxy_unlock_bus, +}; + static bool intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_i915_private *dev_priv) @@ -2953,6 +2998,7 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, sdvo->ddc.dev.parent = &pdev->dev; sdvo->ddc.algo_data = sdvo; sdvo->ddc.algo = &intel_sdvo_ddc_proxy; + sdvo->ddc.lock_ops = &proxy_lock_ops; return i2c_add_adapter(&sdvo->ddc) == 0; } diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 4c6b387fa9dc..524933b01483 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -30,6 +30,7 @@ * support. */ #include <drm/drmP.h> +#include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_fourcc.h> #include <drm/drm_rect.h> @@ -176,7 +177,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc) * re-enables interrupts and verifies the update was actually completed * before a vblank using the value of @start_vbl_count. */ -void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) +void intel_pipe_update_end(struct intel_crtc *crtc) { enum pipe pipe = crtc->pipe; int scanline_end = intel_get_crtc_scanline(crtc); @@ -184,12 +185,6 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work ktime_t end_vbl_time = ktime_get(); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (work) { - work->flip_queued_vblank = end_vbl_count; - smp_mb__before_atomic(); - atomic_set(&work->pending, 1); - } - trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); /* We're still in the vblank-evade critical section, this can't race. @@ -244,6 +239,7 @@ skl_update_plane(struct intel_plane *plane, u32 surf_addr = plane_state->main.offset; unsigned int rotation = plane_state->base.rotation; u32 stride = skl_plane_stride(fb, 0, rotation); + u32 aux_stride = skl_plane_stride(fb, 1, rotation); int crtc_x = plane_state->base.dst.x1; int crtc_y = plane_state->base.dst.y1; uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); @@ -278,6 +274,10 @@ skl_update_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), + (plane_state->aux.offset - surf_addr) | aux_stride); + I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->aux.y << 16) | plane_state->aux.x); /* program plane scaler */ if (plane_state->scaler_id >= 0) { @@ -1038,6 +1038,12 @@ static const uint32_t g4x_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t i9xx_plane_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint32_t snb_plane_formats[] = { DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, @@ -1073,6 +1079,122 @@ static uint32_t skl_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_plane_format_modifiers[] = { + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + +static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + switch (format) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + /* This is the same as primary plane since SKL has universal planes */ + switch (format) { + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_RGB565: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + if (modifier == I915_FORMAT_MOD_Yf_TILED) + return true; + /* fall through */ + case DRM_FORMAT_C8: + if (modifier == DRM_FORMAT_MOD_LINEAR || + modifier == I915_FORMAT_MOD_X_TILED || + modifier == I915_FORMAT_MOD_Y_TILED) + return true; + /* fall through */ + default: + return false; + } +} + +static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, + uint32_t format, + uint64_t modifier) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) + return false; + + if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && + modifier != DRM_FORMAT_MOD_LINEAR) + return false; + + if (INTEL_GEN(dev_priv) >= 9) + return skl_sprite_plane_format_mod_supported(plane, format, modifier); + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + return vlv_sprite_plane_format_mod_supported(plane, format, modifier); + else + return g4x_sprite_plane_format_mod_supported(plane, format, modifier); + + unreachable(); +} + +static const struct drm_plane_funcs intel_sprite_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = intel_plane_destroy, + .atomic_get_property = intel_plane_atomic_get_property, + .atomic_set_property = intel_plane_atomic_set_property, + .atomic_duplicate_state = intel_plane_duplicate_state, + .atomic_destroy_state = intel_plane_destroy_state, + .format_mod_supported = intel_sprite_plane_format_mod_supported, +}; + struct intel_plane * intel_sprite_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, int plane) @@ -1081,6 +1203,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, struct intel_plane_state *state = NULL; unsigned long possible_crtcs; const uint32_t *plane_formats; + const uint64_t *modifiers; unsigned int supported_rotations; int num_plane_formats; int ret; @@ -1098,7 +1221,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } intel_plane->base.state = &state->base; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10) { + intel_plane->can_scale = true; + state->scaler_id = -1; + + intel_plane->update_plane = skl_update_plane; + intel_plane->disable_plane = skl_disable_plane; + + plane_formats = skl_plane_formats; + num_plane_formats = ARRAY_SIZE(skl_plane_formats); + modifiers = skl_plane_format_modifiers; + } else if (INTEL_GEN(dev_priv) >= 9) { intel_plane->can_scale = true; state->scaler_id = -1; @@ -1107,6 +1240,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); + modifiers = skl_plane_format_modifiers; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_plane->can_scale = false; intel_plane->max_downscale = 1; @@ -1116,6 +1250,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = vlv_plane_formats; num_plane_formats = ARRAY_SIZE(vlv_plane_formats); + modifiers = i9xx_plane_format_modifiers; } else if (INTEL_GEN(dev_priv) >= 7) { if (IS_IVYBRIDGE(dev_priv)) { intel_plane->can_scale = true; @@ -1130,6 +1265,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); + modifiers = i9xx_plane_format_modifiers; } else { intel_plane->can_scale = true; intel_plane->max_downscale = 16; @@ -1137,6 +1273,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, intel_plane->update_plane = g4x_update_plane; intel_plane->disable_plane = g4x_disable_plane; + modifiers = i9xx_plane_format_modifiers; if (IS_GEN6(dev_priv)) { plane_formats = snb_plane_formats; num_plane_formats = ARRAY_SIZE(snb_plane_formats); @@ -1169,15 +1306,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 9) ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, - possible_crtcs, &intel_plane_funcs, + possible_crtcs, &intel_sprite_plane_funcs, plane_formats, num_plane_formats, - NULL, DRM_PLANE_TYPE_OVERLAY, + modifiers, + DRM_PLANE_TYPE_OVERLAY, "plane %d%c", plane + 2, pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base, - possible_crtcs, &intel_plane_funcs, + possible_crtcs, &intel_sprite_plane_funcs, plane_formats, num_plane_formats, - NULL, DRM_PLANE_TYPE_OVERLAY, + modifiers, + DRM_PLANE_TYPE_OVERLAY, "sprite %c", sprite_name(pipe, plane)); if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 27e072cc96eb..0178ba42a0e5 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -94,7 +94,7 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv); } -static void guc_write_irq_trigger(struct intel_guc *guc) +static void gen8_guc_raise_irq(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -109,7 +109,7 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv) mutex_init(&guc->send_mutex); guc->send = intel_guc_send_nop; - guc->notify = guc_write_irq_trigger; + guc->notify = gen8_guc_raise_irq; } static void fetch_uc_fw(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index deb4430541cf..1d7b879cc68c 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1497,7 +1497,6 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, [VECS] = GEN6_GRDOM_VECS, }; u32 hw_mask; - int ret; if (engine_mask == ALL_ENGINES) { hw_mask = GEN6_GRDOM_FULL; @@ -1509,11 +1508,7 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv, hw_mask |= hw_engine_mask[engine->id]; } - ret = gen6_hw_domain_reset(dev_priv, hw_mask); - - intel_uncore_forcewake_reset(dev_priv, true); - - return ret; + return gen6_hw_domain_reset(dev_priv, hw_mask); } /** diff --git a/drivers/gpu/drm/i915/selftests/huge_gem_object.c b/drivers/gpu/drm/i915/selftests/huge_gem_object.c index caf76af36aba..c5c7e8efbdd3 100644 --- a/drivers/gpu/drm/i915/selftests/huge_gem_object.c +++ b/drivers/gpu/drm/i915/selftests/huge_gem_object.c @@ -111,6 +111,7 @@ huge_gem_object(struct drm_i915_private *i915, dma_addr_t dma_size) { struct drm_i915_gem_object *obj; + unsigned int cache_level; GEM_BUG_ON(!phys_size || phys_size > dma_size); GEM_BUG_ON(!IS_ALIGNED(phys_size, PAGE_SIZE)); @@ -128,9 +129,8 @@ huge_gem_object(struct drm_i915_private *i915, obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU; - obj->cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; - obj->cache_coherent = i915_gem_object_is_coherent(obj); - obj->cache_dirty = !obj->cache_coherent; + cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE; + i915_gem_object_set_cache_coherency(obj, cache_level); obj->scratch = phys_size; return obj; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c index 95d4aebc0181..35d778d70626 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c @@ -241,7 +241,7 @@ static bool always_valid(struct drm_i915_private *i915) static bool needs_mi_store_dword(struct drm_i915_private *i915) { - return igt_can_mi_store_dword_imm(i915); + return intel_engine_can_store_dword(i915->engine[RCS]); } static const struct igt_coherency_mode { diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 12b85b3278cd..fb0a58fc8348 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -38,8 +38,6 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value) u32 *cmd; int err; - GEM_BUG_ON(!igt_can_mi_store_dword_imm(vma->vm->i915)); - size = (4 * count + 1) * sizeof(u32); size = round_up(size, PAGE_SIZE); obj = i915_gem_object_create_internal(vma->vm->i915, size); @@ -123,6 +121,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj, int err; GEM_BUG_ON(obj->base.size > vm->total); + GEM_BUG_ON(!intel_engine_can_store_dword(engine)); vma = i915_vma_instance(obj, vm, NULL); if (IS_ERR(vma)) @@ -359,6 +358,9 @@ static int igt_ctx_exec(void *arg) } for_each_engine(engine, i915, id) { + if (!intel_engine_can_store_dword(engine)) + continue; + if (!obj) { obj = create_test_object(ctx, file, &objects); if (IS_ERR(obj)) { diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 7096c3911cd3..02e52a146ed8 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -22,8 +22,13 @@ * */ +#include <linux/kthread.h> + #include "../i915_selftest.h" +#include "mock_context.h" +#include "mock_drm.h" + struct hang { struct drm_i915_private *i915; struct drm_i915_gem_object *hws; @@ -248,9 +253,6 @@ static int igt_hang_sanitycheck(void *arg) /* Basic check that we can execute our hanging batch */ - if (!igt_can_mi_store_dword_imm(i915)) - return 0; - mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); if (err) @@ -259,6 +261,9 @@ static int igt_hang_sanitycheck(void *arg) for_each_engine(engine, i915, id) { long timeout; + if (!intel_engine_can_store_dword(engine)) + continue; + rq = hang_create_request(&h, engine, i915->kernel_context); if (IS_ERR(rq)) { err = PTR_ERR(rq); @@ -292,6 +297,37 @@ unlock: return err; } +static void global_reset_lock(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags)) + wait_event(i915->gpu_error.reset_queue, + !test_bit(I915_RESET_BACKOFF, + &i915->gpu_error.flags)); + + for_each_engine(engine, i915, id) { + while (test_and_set_bit(I915_RESET_ENGINE + id, + &i915->gpu_error.flags)) + wait_on_bit(&i915->gpu_error.flags, + I915_RESET_ENGINE + id, + TASK_UNINTERRUPTIBLE); + } +} + +static void global_reset_unlock(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, i915, id) + clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags); + + clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + wake_up_all(&i915->gpu_error.reset_queue); +} + static int igt_global_reset(void *arg) { struct drm_i915_private *i915 = arg; @@ -300,13 +336,13 @@ static int igt_global_reset(void *arg) /* Check that we can issue a global GPU reset */ - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); mutex_lock(&i915->drm.struct_mutex); reset_count = i915_reset_count(&i915->gpu_error); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); if (i915_reset_count(&i915->gpu_error) == reset_count) { pr_err("No GPU reset recorded!\n"); @@ -315,8 +351,7 @@ static int igt_global_reset(void *arg) mutex_unlock(&i915->drm.struct_mutex); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) err = -EIO; @@ -343,7 +378,7 @@ static int igt_reset_engine(void *arg) reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - err = i915_reset_engine(engine); + err = i915_reset_engine(engine, I915_RESET_QUIET); if (err) { pr_err("i915_reset_engine failed\n"); break; @@ -372,6 +407,164 @@ static int igt_reset_engine(void *arg) return err; } +static int active_engine(void *data) +{ + struct intel_engine_cs *engine = data; + struct drm_i915_gem_request *rq[2] = {}; + struct i915_gem_context *ctx[2]; + struct drm_file *file; + unsigned long count = 0; + int err = 0; + + file = mock_file(engine->i915); + if (IS_ERR(file)) + return PTR_ERR(file); + + mutex_lock(&engine->i915->drm.struct_mutex); + ctx[0] = live_context(engine->i915, file); + mutex_unlock(&engine->i915->drm.struct_mutex); + if (IS_ERR(ctx[0])) { + err = PTR_ERR(ctx[0]); + goto err_file; + } + + mutex_lock(&engine->i915->drm.struct_mutex); + ctx[1] = live_context(engine->i915, file); + mutex_unlock(&engine->i915->drm.struct_mutex); + if (IS_ERR(ctx[1])) { + err = PTR_ERR(ctx[1]); + i915_gem_context_put(ctx[0]); + goto err_file; + } + + while (!kthread_should_stop()) { + unsigned int idx = count++ & 1; + struct drm_i915_gem_request *old = rq[idx]; + struct drm_i915_gem_request *new; + + mutex_lock(&engine->i915->drm.struct_mutex); + new = i915_gem_request_alloc(engine, ctx[idx]); + if (IS_ERR(new)) { + mutex_unlock(&engine->i915->drm.struct_mutex); + err = PTR_ERR(new); + break; + } + + rq[idx] = i915_gem_request_get(new); + i915_add_request(new); + mutex_unlock(&engine->i915->drm.struct_mutex); + + if (old) { + i915_wait_request(old, 0, MAX_SCHEDULE_TIMEOUT); + i915_gem_request_put(old); + } + } + + for (count = 0; count < ARRAY_SIZE(rq); count++) + i915_gem_request_put(rq[count]); + +err_file: + mock_file_free(engine->i915, file); + return err; +} + +static int igt_reset_active_engines(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct intel_engine_cs *engine, *active; + enum intel_engine_id id, tmp; + int err = 0; + + /* Check that issuing a reset on one engine does not interfere + * with any other engine. + */ + + if (!intel_has_reset_engine(i915)) + return 0; + + for_each_engine(engine, i915, id) { + struct task_struct *threads[I915_NUM_ENGINES]; + unsigned long resets[I915_NUM_ENGINES]; + unsigned long global = i915_reset_count(&i915->gpu_error); + IGT_TIMEOUT(end_time); + + memset(threads, 0, sizeof(threads)); + for_each_engine(active, i915, tmp) { + struct task_struct *tsk; + + if (active == engine) + continue; + + resets[tmp] = i915_reset_engine_count(&i915->gpu_error, + active); + + tsk = kthread_run(active_engine, active, + "igt/%s", active->name); + if (IS_ERR(tsk)) { + err = PTR_ERR(tsk); + goto unwind; + } + + threads[tmp] = tsk; + get_task_struct(tsk); + } + + set_bit(I915_RESET_ENGINE + engine->id, &i915->gpu_error.flags); + do { + err = i915_reset_engine(engine, I915_RESET_QUIET); + if (err) { + pr_err("i915_reset_engine(%s) failed, err=%d\n", + engine->name, err); + break; + } + } while (time_before(jiffies, end_time)); + clear_bit(I915_RESET_ENGINE + engine->id, + &i915->gpu_error.flags); + +unwind: + for_each_engine(active, i915, tmp) { + int ret; + + if (!threads[tmp]) + continue; + + ret = kthread_stop(threads[tmp]); + if (ret) { + pr_err("kthread for active engine %s failed, err=%d\n", + active->name, ret); + if (!err) + err = ret; + } + put_task_struct(threads[tmp]); + + if (resets[tmp] != i915_reset_engine_count(&i915->gpu_error, + active)) { + pr_err("Innocent engine %s was reset (count=%ld)\n", + active->name, + i915_reset_engine_count(&i915->gpu_error, + active) - resets[tmp]); + err = -EIO; + } + } + + if (global != i915_reset_count(&i915->gpu_error)) { + pr_err("Global reset (count=%ld)!\n", + i915_reset_count(&i915->gpu_error) - global); + err = -EIO; + } + + if (err) + break; + + cond_resched(); + } + + if (i915_terminally_wedged(&i915->gpu_error)) + err = -EIO; + + return err; +} + static u32 fake_hangcheck(struct drm_i915_gem_request *rq) { u32 reset_count; @@ -406,9 +599,12 @@ static int igt_wait_reset(void *arg) long timeout; int err; + if (!intel_engine_can_store_dword(i915->engine[RCS])) + return 0; + /* Check that we detect a stuck waiter and issue a reset */ - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + global_reset_lock(i915); mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -453,8 +649,7 @@ fini: hang_fini(&h); unlock: mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; @@ -472,10 +667,8 @@ static int igt_reset_queue(void *arg) /* Check that we replay pending requests following a hang */ - if (!igt_can_mi_store_dword_imm(i915)) - return 0; + global_reset_lock(i915); - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); if (err) @@ -486,6 +679,9 @@ static int igt_reset_queue(void *arg) IGT_TIMEOUT(end_time); unsigned int count; + if (!intel_engine_can_store_dword(engine)) + continue; + prev = hang_create_request(&h, engine, i915->kernel_context); if (IS_ERR(prev)) { err = PTR_ERR(prev); @@ -522,7 +718,7 @@ static int igt_reset_queue(void *arg) reset_count = fake_hangcheck(prev); - i915_reset(i915); + i915_reset(i915, I915_RESET_QUIET); GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags)); @@ -569,8 +765,7 @@ fini: hang_fini(&h); unlock: mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + global_reset_unlock(i915); if (i915_terminally_wedged(&i915->gpu_error)) return -EIO; @@ -578,21 +773,23 @@ unlock: return err; } -static int igt_render_engine_reset_fallback(void *arg) +static int igt_handle_error(void *arg) { struct drm_i915_private *i915 = arg; struct intel_engine_cs *engine = i915->engine[RCS]; struct hang h; struct drm_i915_gem_request *rq; - unsigned int reset_count, reset_engine_count; - int err = 0; + struct i915_gpu_state *error; + int err; /* Check that we can issue a global GPU and engine reset */ if (!intel_has_reset_engine(i915)) return 0; - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); + if (!intel_engine_can_store_dword(i915->engine[RCS])) + return 0; + mutex_lock(&i915->drm.struct_mutex); err = hang_init(&h, i915); @@ -608,71 +805,31 @@ static int igt_render_engine_reset_fallback(void *arg) i915_gem_request_get(rq); __i915_add_request(rq, true); - /* make reset engine fail */ - rq->fence.error = -EIO; - if (!wait_for_hang(&h, rq)) { pr_err("Failed to start request %x\n", rq->fence.seqno); err = -EIO; goto err_request; } - reset_engine_count = i915_reset_engine_count(&i915->gpu_error, engine); - reset_count = fake_hangcheck(rq); - - /* unlock since we'll call handle_error */ mutex_unlock(&i915->drm.struct_mutex); - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); - i915_handle_error(i915, intel_engine_flag(engine), "live test"); + /* Temporarily disable error capture */ + error = xchg(&i915->gpu_error.first_error, (void *)-1); - if (i915_reset_engine_count(&i915->gpu_error, engine) != - reset_engine_count) { - pr_err("render engine reset recorded! (full reset expected)\n"); - err = -EINVAL; - goto out_rq; - } + engine->hangcheck.stalled = true; + engine->hangcheck.seqno = intel_engine_get_seqno(engine); - if (i915_reset_count(&i915->gpu_error) == reset_count) { - pr_err("No full GPU reset recorded!\n"); - err = -EINVAL; - goto out_rq; - } + i915_handle_error(i915, intel_engine_flag(engine), "%s", __func__); - /* - * by using fence.error = -EIO, full reset sets the wedged flag, do one - * more full reset to re-enable the hw. - */ - if (i915_terminally_wedged(&i915->gpu_error)) { - set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - rq->fence.error = 0; - - mutex_lock(&i915->drm.struct_mutex); - set_bit(I915_RESET_HANDOFF, &i915->gpu_error.flags); - i915_reset(i915); - GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, - &i915->gpu_error.flags)); - mutex_unlock(&i915->drm.struct_mutex); - - if (i915_reset_count(&i915->gpu_error) == reset_count) { - pr_err("No full GPU reset recorded!\n"); - err = -EINVAL; - goto out_rq; - } - } - -out_rq: - i915_gem_request_put(rq); - hang_fini(&h); -out_backoff: - clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags); - wake_up_all(&i915->gpu_error.reset_queue); + xchg(&i915->gpu_error.first_error, error); - if (i915_terminally_wedged(&i915->gpu_error)) - return -EIO; + mutex_lock(&i915->drm.struct_mutex); - return err; + if (rq->fence.error != -EIO) { + pr_err("Guilty request not identified!\n"); + err = -EINVAL; + goto err_request; + } err_request: i915_gem_request_put(rq); @@ -680,7 +837,7 @@ err_fini: hang_fini(&h); err_unlock: mutex_unlock(&i915->drm.struct_mutex); - goto out_backoff; + return err; } int intel_hangcheck_live_selftests(struct drm_i915_private *i915) @@ -689,9 +846,10 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) SUBTEST(igt_hang_sanitycheck), SUBTEST(igt_global_reset), SUBTEST(igt_reset_engine), + SUBTEST(igt_reset_active_engines), SUBTEST(igt_wait_reset), SUBTEST(igt_reset_queue), - SUBTEST(igt_render_engine_reset_fallback), + SUBTEST(igt_handle_error), }; if (!intel_has_gpu_reset(i915)) diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c b/drivers/gpu/drm/i915/selftests/mock_context.c index 9c7c68181f82..098ce643ad07 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/selftests/mock_context.c @@ -40,18 +40,13 @@ mock_context(struct drm_i915_private *i915, INIT_LIST_HEAD(&ctx->link); ctx->i915 = i915; - ctx->vma_lut.ht_bits = VMA_HT_BITS; - ctx->vma_lut.ht_size = BIT(VMA_HT_BITS); - ctx->vma_lut.ht = kcalloc(ctx->vma_lut.ht_size, - sizeof(*ctx->vma_lut.ht), - GFP_KERNEL); - if (!ctx->vma_lut.ht) - goto err_free; + INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + INIT_LIST_HEAD(&ctx->handles_list); ret = ida_simple_get(&i915->contexts.hw_ida, 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); if (ret < 0) - goto err_vma_ht; + goto err_handles; ctx->hw_id = ret; if (name) { @@ -66,9 +61,7 @@ mock_context(struct drm_i915_private *i915, return ctx; -err_vma_ht: - kvfree(ctx->vma_lut.ht); -err_free: +err_handles: kfree(ctx); return NULL; @@ -95,3 +88,11 @@ void mock_init_contexts(struct drm_i915_private *i915) INIT_WORK(&i915->contexts.free_work, contexts_free_worker); init_llist_head(&i915->contexts.free_list); } + +struct i915_gem_context * +live_context(struct drm_i915_private *i915, struct drm_file *file) +{ + lockdep_assert_held(&i915->drm.struct_mutex); + + return i915_gem_create_context(i915, file->driver_priv); +} diff --git a/drivers/gpu/drm/i915/selftests/mock_context.h b/drivers/gpu/drm/i915/selftests/mock_context.h index 383941a61124..2f432c03d413 100644 --- a/drivers/gpu/drm/i915/selftests/mock_context.h +++ b/drivers/gpu/drm/i915/selftests/mock_context.h @@ -33,4 +33,7 @@ mock_context(struct drm_i915_private *i915, void mock_context_close(struct i915_gem_context *ctx); +struct i915_gem_context * +live_context(struct drm_i915_private *i915, struct drm_file *file); + #endif /* !__MOCK_CONTEXT_H */ diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c b/drivers/gpu/drm/i915/selftests/mock_engine.c index 5b18a2dc19a8..fc0fd7498689 100644 --- a/drivers/gpu/drm/i915/selftests/mock_engine.c +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c @@ -123,10 +123,12 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine) } struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, - const char *name) + const char *name, + int id) { struct mock_engine *engine; - static int id; + + GEM_BUG_ON(id >= I915_NUM_ENGINES); engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL); if (!engine) @@ -141,7 +143,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, /* minimal engine setup for requests */ engine->base.i915 = i915; snprintf(engine->base.name, sizeof(engine->base.name), "%s", name); - engine->base.id = id++; + engine->base.id = id; engine->base.status_page.page_addr = (void *)(engine + 1); engine->base.context_pin = mock_context_pin; diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.h b/drivers/gpu/drm/i915/selftests/mock_engine.h index e5e240216ba3..133d0c21790d 100644 --- a/drivers/gpu/drm/i915/selftests/mock_engine.h +++ b/drivers/gpu/drm/i915/selftests/mock_engine.h @@ -40,7 +40,8 @@ struct mock_engine { }; struct intel_engine_cs *mock_engine(struct drm_i915_private *i915, - const char *name); + const char *name, + int id); void mock_engine_flush(struct intel_engine_cs *engine); void mock_engine_reset(struct intel_engine_cs *engine); void mock_engine_free(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 2f1844c50e7d..678723430d78 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -22,6 +22,7 @@ * */ +#include <linux/pm_domain.h> #include <linux/pm_runtime.h> #include "mock_engine.h" @@ -53,11 +54,12 @@ static void mock_device_release(struct drm_device *dev) mutex_lock(&i915->drm.struct_mutex); mock_device_flush(i915); + i915_gem_contexts_lost(i915); mutex_unlock(&i915->drm.struct_mutex); cancel_delayed_work_sync(&i915->gt.retire_work); cancel_delayed_work_sync(&i915->gt.idle_work); - flush_workqueue(i915->wq); + i915_gem_drain_workqueue(i915); mutex_lock(&i915->drm.struct_mutex); for_each_engine(engine, i915, id) @@ -109,6 +111,23 @@ static void mock_idle_work_handler(struct work_struct *work) { } +static int pm_domain_resume(struct device *dev) +{ + return pm_generic_runtime_resume(dev); +} + +static int pm_domain_suspend(struct device *dev) +{ + return pm_generic_runtime_suspend(dev); +} + +static struct dev_pm_domain pm_domain = { + .ops = { + .runtime_suspend = pm_domain_suspend, + .runtime_resume = pm_domain_resume, + }, +}; + struct drm_i915_private *mock_gem_device(void) { struct drm_i915_private *i915; @@ -127,8 +146,10 @@ struct drm_i915_private *mock_gem_device(void) dev_set_name(&pdev->dev, "mock"); dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + dev_pm_domain_set(&pdev->dev, &pm_domain); + pm_runtime_enable(&pdev->dev); pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); + WARN_ON(pm_runtime_get_sync(&pdev->dev)); i915 = (struct drm_i915_private *)(pdev + 1); pci_set_drvdata(pdev, i915); @@ -205,7 +226,7 @@ struct drm_i915_private *mock_gem_device(void) mutex_unlock(&i915->drm.struct_mutex); mkwrite_device_info(i915)->ring_mask = BIT(0); - i915->engine[RCS] = mock_engine(i915, "mock"); + i915->engine[RCS] = mock_engine(i915, "mock", RCS); if (!i915->engine[RCS]) goto err_priorities; diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c index debde2dae7bf..227309b01206 100644 --- a/drivers/gpu/drm/imx/ipuv3-plane.c +++ b/drivers/gpu/drm/imx/ipuv3-plane.c @@ -496,6 +496,27 @@ static int ipu_chan_assign_axi_id(int ipu_chan) } } +static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride, + u8 *burstsize, u8 *num_bursts) +{ + const unsigned int width_bytes = width * cpp; + unsigned int npb, bursts; + + /* Maximum number of pixels per burst without overshooting stride */ + for (npb = 64 / cpp; npb > 0; --npb) { + if (round_up(width_bytes, npb * cpp) <= stride) + break; + } + *burstsize = npb; + + /* Maximum number of consecutive bursts without overshooting stride */ + for (bursts = 8; bursts > 1; bursts /= 2) { + if (round_up(width_bytes, npb * cpp * bursts) <= stride) + break; + } + *num_bursts = bursts; +} + static void ipu_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { @@ -509,6 +530,9 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, unsigned long alpha_eba = 0; enum ipu_color_space ics; unsigned int axi_id = 0; + const struct drm_format_info *info; + u8 burstsize, num_bursts; + u32 width, height; int active; if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG) @@ -525,8 +549,8 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, drm_rect_width(&state->src) >> 16, drm_rect_height(&state->src) >> 16, - state->fb->pitches[0], - state->fb->format->format, &eba); + fb->pitches[0], + fb->format->format, &eba); } if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) { @@ -553,11 +577,11 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); break; case IPU_DP_FLOW_SYNC_FG: - ics = ipu_drm_fourcc_to_colorspace(state->fb->format->format); + ics = ipu_drm_fourcc_to_colorspace(fb->format->format); ipu_dp_setup_channel(ipu_plane->dp, ics, IPUV3_COLORSPACE_UNKNOWN); /* Enable local alpha on partial plane */ - switch (state->fb->format->format) { + switch (fb->format->format) { case DRM_FORMAT_ARGB1555: case DRM_FORMAT_ABGR1555: case DRM_FORMAT_RGBA5551: @@ -583,15 +607,21 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst)); + width = drm_rect_width(&state->src) >> 16; + height = drm_rect_height(&state->src) >> 16; + info = drm_format_info(fb->format->format); + ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0], + &burstsize, &num_bursts); + ipu_cpmem_zero(ipu_plane->ipu_ch); - ipu_cpmem_set_resolution(ipu_plane->ipu_ch, - drm_rect_width(&state->src) >> 16, - drm_rect_height(&state->src) >> 16); - ipu_cpmem_set_fmt(ipu_plane->ipu_ch, state->fb->format->format); + ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height); + ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format); + ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize); ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); - ipu_cpmem_set_stride(ipu_plane->ipu_ch, state->fb->pitches[0]); + ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id); + switch (fb->format->format) { case DRM_FORMAT_YUV420: case DRM_FORMAT_YVU420: @@ -631,6 +661,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, case DRM_FORMAT_RGBX8888_A8: case DRM_FORMAT_BGRX8888_A8: alpha_eba = drm_plane_state_to_eba(state, 1); + num_bursts = 0; dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d", eba, alpha_eba, state->src.x1 >> 16, state->src.y1 >> 16); @@ -644,8 +675,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8); ipu_cpmem_set_high_priority(ipu_plane->alpha_ch); ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1); - ipu_cpmem_set_stride(ipu_plane->alpha_ch, - state->fb->pitches[1]); + ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]); ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16); ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba); ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba); @@ -657,6 +687,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane, } ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); + ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts); ipu_plane_enable(ipu_plane); } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_fb.c b/drivers/gpu/drm/mediatek/mtk_drm_fb.c index d4246c9dceae..0d8d506695f9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_fb.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_fb.c @@ -58,7 +58,7 @@ static void mtk_drm_fb_destroy(struct drm_framebuffer *fb) drm_framebuffer_cleanup(fb); - drm_gem_object_unreference_unlocked(mtk_fb->gem_obj); + drm_gem_object_put_unlocked(mtk_fb->gem_obj); kfree(mtk_fb); } @@ -160,6 +160,6 @@ struct drm_framebuffer *mtk_drm_mode_fb_create(struct drm_device *dev, return &mtk_fb->base; unreference: - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c index 8ec963fff8b1..f595ac816b55 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c @@ -122,7 +122,7 @@ int mtk_drm_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, goto err_handle_create; /* drop reference from allocate - handle holds it now. */ - drm_gem_object_unreference_unlocked(&mtk_gem->base); + drm_gem_object_put_unlocked(&mtk_gem->base); return 0; diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 5375e6dccdd7..7742c7d81ed8 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -116,8 +116,6 @@ static struct drm_driver meson_driver = { /* GEM Ops */ .dumb_create = drm_gem_cma_dumb_create, - .dumb_destroy = drm_gem_dumb_destroy, - .dumb_map_offset = drm_gem_cma_dumb_map_offset, .gem_free_object_unlocked = drm_gem_cma_free_object, .gem_vm_ops = &drm_gem_cma_vm_ops, diff --git a/drivers/gpu/drm/mgag200/mgag200_cursor.c b/drivers/gpu/drm/mgag200/mgag200_cursor.c index 2ac3fcbfea7b..968e20379d54 100644 --- a/drivers/gpu/drm/mgag200/mgag200_cursor.c +++ b/drivers/gpu/drm/mgag200/mgag200_cursor.c @@ -248,7 +248,7 @@ int mga_crtc_cursor_set(struct drm_crtc *crtc, out_unreserve1: mgag200_bo_unreserve(pixels_2); out_unref: - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c index 4189160af726..74cdde2ee474 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.c +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c @@ -102,7 +102,6 @@ static struct drm_driver driver = { .gem_free_object_unlocked = mgag200_gem_free_object, .dumb_create = mgag200_dumb_create, .dumb_map_offset = mgag200_dumb_mmap_offset, - .dumb_destroy = drm_gem_dumb_destroy, }; static struct pci_driver mgag200_pci_driver = { diff --git a/drivers/gpu/drm/mgag200/mgag200_fb.c b/drivers/gpu/drm/mgag200/mgag200_fb.c index 9d914ca69996..30726c9fe28c 100644 --- a/drivers/gpu/drm/mgag200/mgag200_fb.c +++ b/drivers/gpu/drm/mgag200/mgag200_fb.c @@ -232,7 +232,7 @@ static int mgag200fb_create(struct drm_fb_helper *helper, err_alloc_fbi: vfree(sysram); err_sysram: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return ret; } @@ -245,7 +245,7 @@ static int mga_fbdev_destroy(struct drm_device *dev, drm_fb_helper_unregister_fbi(&mfbdev->helper); if (mfb->obj) { - drm_gem_object_unreference_unlocked(mfb->obj); + drm_gem_object_put_unlocked(mfb->obj); mfb->obj = NULL; } drm_fb_helper_fini(&mfbdev->helper); diff --git a/drivers/gpu/drm/mgag200/mgag200_main.c b/drivers/gpu/drm/mgag200/mgag200_main.c index dce8a3eb5a10..780f983b0294 100644 --- a/drivers/gpu/drm/mgag200/mgag200_main.c +++ b/drivers/gpu/drm/mgag200/mgag200_main.c @@ -18,7 +18,7 @@ static void mga_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct mga_framebuffer *mga_fb = to_mga_framebuffer(fb); - drm_gem_object_unreference_unlocked(mga_fb->obj); + drm_gem_object_put_unlocked(mga_fb->obj); drm_framebuffer_cleanup(fb); kfree(fb); } @@ -59,13 +59,13 @@ mgag200_user_framebuffer_create(struct drm_device *dev, mga_fb = kzalloc(sizeof(*mga_fb), GFP_KERNEL); if (!mga_fb) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(-ENOMEM); } ret = mgag200_framebuffer_init(dev, mga_fb, mode_cmd, obj); if (ret) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); kfree(mga_fb); return ERR_PTR(ret); } @@ -317,7 +317,7 @@ int mgag200_dumb_create(struct drm_file *file, return ret; ret = drm_gem_handle_create(file, gobj, &handle); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (ret) return ret; @@ -366,6 +366,6 @@ mgag200_dumb_mmap_offset(struct drm_file *file, bo = gem_to_mga_bo(obj); *offset = mgag200_bo_mmap_offset(bo); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 0e3828ed1e46..7791313405b5 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -486,8 +486,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) adreno_gpu = &a3xx_gpu->base; gpu = &adreno_gpu->base; - a3xx_gpu->pdev = pdev; - gpu->perfcntrs = perfcntrs; gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h index 85ff66cbddd6..ab60dc9e344e 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h @@ -28,7 +28,6 @@ struct a3xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; /* if OCMEM is used for GMEM: */ uint32_t ocmem_base; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 19abf229b08d..58341ef6f15b 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -568,8 +568,6 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) adreno_gpu = &a4xx_gpu->base; gpu = &adreno_gpu->base; - a4xx_gpu->pdev = pdev; - gpu->perfcntrs = NULL; gpu->num_perfcntrs = 0; diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.h b/drivers/gpu/drm/msm/adreno/a4xx_gpu.h index 01247204ac92..f757184328a3 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.h @@ -23,7 +23,6 @@ struct a4xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; /* if OCMEM is used for GMEM: */ uint32_t ocmem_base; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f9eae03aa1dc..17c59d839e6f 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -284,28 +284,14 @@ static int a5xx_me_init(struct msm_gpu *gpu) static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, const struct firmware *fw, u64 *iova) { - struct drm_device *drm = gpu->dev; struct drm_gem_object *bo; void *ptr; - bo = msm_gem_new_locked(drm, fw->size - 4, MSM_BO_UNCACHED); - if (IS_ERR(bo)) - return bo; + ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, + MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); - ptr = msm_gem_get_vaddr(bo); - if (!ptr) { - drm_gem_object_unreference(bo); - return ERR_PTR(-ENOMEM); - } - - if (iova) { - int ret = msm_gem_get_iova(bo, gpu->aspace, iova); - - if (ret) { - drm_gem_object_unreference(bo); - return ERR_PTR(ret); - } - } + if (IS_ERR(ptr)) + return ERR_CAST(ptr); memcpy(ptr, &fw->data[4], fw->size - 4); @@ -372,8 +358,7 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) { static bool loaded; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); - struct platform_device *pdev = a5xx_gpu->pdev; + struct platform_device *pdev = gpu->pdev; int ret; /* @@ -410,6 +395,7 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT | \ A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW | \ A5XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ + A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT | \ A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP) @@ -812,6 +798,27 @@ static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); } +static void a5xx_fault_detect_irq(struct msm_gpu *gpu) +{ + struct drm_device *dev = gpu->dev; + struct msm_drm_private *priv = dev->dev_private; + + dev_err(dev->dev, "gpu fault fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", + gpu->funcs->last_fence(gpu), + gpu_read(gpu, REG_A5XX_RBBM_STATUS), + gpu_read(gpu, REG_A5XX_CP_RB_RPTR), + gpu_read(gpu, REG_A5XX_CP_RB_WPTR), + gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI), + gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), + gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI), + gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); + + /* Turn off the hangcheck timer to keep it from bothering us */ + del_timer(&gpu->hangcheck_timer); + + queue_work(priv->wq, &gpu->recover_work); +} + #define RBBM_ERROR_MASK \ (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \ A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \ @@ -838,6 +845,9 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu) if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR) a5xx_cp_err_irq(gpu); + if (status & A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT) + a5xx_fault_detect_irq(gpu); + if (status & A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) a5xx_uche_err_irq(gpu); @@ -1015,7 +1025,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) adreno_gpu = &a5xx_gpu->base; gpu = &adreno_gpu->base; - a5xx_gpu->pdev = pdev; adreno_gpu->registers = a5xx_registers; adreno_gpu->reg_offsets = a5xx_register_offsets; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h index 1137092241d5..e94451685bf8 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -23,7 +23,6 @@ struct a5xx_gpu { struct adreno_gpu base; - struct platform_device *pdev; struct drm_gem_object *pm4_bo; uint64_t pm4_iova; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index 87af6eea0483..04aab1dcae2b 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -294,16 +294,10 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) */ bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; - a5xx_gpu->gpmu_bo = msm_gem_new_locked(drm, bosize, MSM_BO_UNCACHED); - if (IS_ERR(a5xx_gpu->gpmu_bo)) - goto err; - - if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->aspace, - &a5xx_gpu->gpmu_iova)) - goto err; - - ptr = msm_gem_get_vaddr(a5xx_gpu->gpmu_bo); - if (!ptr) + ptr = msm_gem_kernel_new_locked(drm, bosize, + MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, + &a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova); + if (IS_ERR(ptr)) goto err; while (cmds_size > 0) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 7414c6bbd582..c8b4ac254bb5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -337,11 +337,6 @@ void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords) DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name); } -static const char *iommu_ports[] = { - "gfx3d_user", "gfx3d_priv", - "gfx3d1_user", "gfx3d1_priv", -}; - int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs) { @@ -373,15 +368,15 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.ringsz = RB_SIZE; + pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, adreno_gpu->info->name, &adreno_gpu_config); if (ret) return ret; - pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); - ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev); if (ret) { dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", @@ -396,37 +391,17 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, return ret; } - if (gpu->aspace && gpu->aspace->mmu) { - struct msm_mmu *mmu = gpu->aspace->mmu; - ret = mmu->funcs->attach(mmu, iommu_ports, - ARRAY_SIZE(iommu_ports)); - if (ret) - return ret; - } + adreno_gpu->memptrs = msm_gem_kernel_new(drm, + sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED, gpu->aspace, + &adreno_gpu->memptrs_bo, &adreno_gpu->memptrs_iova); - adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs), - MSM_BO_UNCACHED); - if (IS_ERR(adreno_gpu->memptrs_bo)) { - ret = PTR_ERR(adreno_gpu->memptrs_bo); - adreno_gpu->memptrs_bo = NULL; - dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); - return ret; - } - - adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo); if (IS_ERR(adreno_gpu->memptrs)) { - dev_err(drm->dev, "could not vmap memptrs\n"); - return -ENOMEM; - } - - ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->aspace, - &adreno_gpu->memptrs_iova); - if (ret) { - dev_err(drm->dev, "could not map memptrs: %d\n", ret); - return ret; + ret = PTR_ERR(adreno_gpu->memptrs); + adreno_gpu->memptrs = NULL; + dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); } - return 0; + return ret; } void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) @@ -446,10 +421,4 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) release_firmware(adreno_gpu->pfp); msm_gpu_cleanup(gpu); - - if (gpu->aspace) { - gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, - iommu_ports, ARRAY_SIZE(iommu_ports)); - msm_gem_address_space_put(gpu->aspace); - } } diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 311c1c1e7d6c..98742d7af6dc 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -161,12 +161,17 @@ static const struct of_device_id dt_match[] = { {} }; +static const struct dev_pm_ops dsi_pm_ops = { + SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, NULL) +}; + static struct platform_driver dsi_driver = { .probe = dsi_dev_probe, .remove = dsi_dev_remove, .driver = { .name = "msm_dsi", .of_match_table = dt_match, + .pm = &dsi_pm_ops, }, }; diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 9e6017387efb..2302046197a8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -179,6 +179,8 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host); int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, struct drm_device *dev); int msm_dsi_host_init(struct msm_dsi *msm_dsi); +int msm_dsi_runtime_suspend(struct device *dev); +int msm_dsi_runtime_resume(struct device *dev); /* dsi phy */ struct msm_dsi_phy; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index c7b612c3d771..dbb31a014419 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -135,7 +135,6 @@ struct msm_dsi_host { struct completion video_comp; struct mutex dev_mutex; struct mutex cmd_mutex; - struct mutex clk_mutex; spinlock_t intr_lock; /* Protect interrupt ctrl register */ u32 err_work_state; @@ -221,6 +220,8 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( goto put_gdsc; } + pm_runtime_get_sync(dev); + ret = regulator_enable(gdsc_reg); if (ret) { pr_err("%s: unable to enable gdsc\n", __func__); @@ -247,6 +248,7 @@ disable_clks: clk_disable_unprepare(ahb_clk); disable_gdsc: regulator_disable(gdsc_reg); + pm_runtime_put_autosuspend(dev); put_clk: clk_put(ahb_clk); put_gdsc: @@ -455,6 +457,34 @@ static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->bus_clks[i]); } +int msm_dsi_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); + struct mipi_dsi_host *host = msm_dsi->host; + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + if (!msm_host->cfg_hnd) + return 0; + + dsi_bus_clk_disable(msm_host); + + return 0; +} + +int msm_dsi_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); + struct mipi_dsi_host *host = msm_dsi->host; + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + if (!msm_host->cfg_hnd) + return 0; + + return dsi_bus_clk_enable(msm_host); +} + static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) { int ret; @@ -596,35 +626,6 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) } } -static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable) -{ - int ret = 0; - - mutex_lock(&msm_host->clk_mutex); - if (enable) { - ret = dsi_bus_clk_enable(msm_host); - if (ret) { - pr_err("%s: Can not enable bus clk, %d\n", - __func__, ret); - goto unlock_ret; - } - ret = dsi_link_clk_enable(msm_host); - if (ret) { - pr_err("%s: Can not enable link clk, %d\n", - __func__, ret); - dsi_bus_clk_disable(msm_host); - goto unlock_ret; - } - } else { - dsi_link_clk_disable(msm_host); - dsi_bus_clk_disable(msm_host); - } - -unlock_ret: - mutex_unlock(&msm_host->clk_mutex); - return ret; -} - static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host) { struct drm_display_mode *mode = msm_host->mode; @@ -1699,6 +1700,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) } msm_host->pdev = pdev; + msm_dsi->host = &msm_host->base; ret = dsi_host_parse_dt(msm_host); if (ret) { @@ -1713,6 +1715,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } + pm_runtime_enable(&pdev->dev); + msm_host->cfg_hnd = dsi_get_config(msm_host); if (!msm_host->cfg_hnd) { ret = -EINVAL; @@ -1753,7 +1757,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) init_completion(&msm_host->video_comp); mutex_init(&msm_host->dev_mutex); mutex_init(&msm_host->cmd_mutex); - mutex_init(&msm_host->clk_mutex); spin_lock_init(&msm_host->intr_lock); /* setup workqueue */ @@ -1761,7 +1764,6 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) INIT_WORK(&msm_host->err_work, dsi_err_worker); INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); - msm_dsi->host = &msm_host->base; msm_dsi->id = msm_host->id; DBG("Dsi Host %d initialized", msm_host->id); @@ -1783,9 +1785,10 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) msm_host->workqueue = NULL; } - mutex_destroy(&msm_host->clk_mutex); mutex_destroy(&msm_host->cmd_mutex); mutex_destroy(&msm_host->dev_mutex); + + pm_runtime_disable(&msm_host->pdev->dev); } int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, @@ -1881,7 +1884,8 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, * mdss interrupt is generated in mdp core clock domain * mdp clock need to be enabled to receive dsi interrupt */ - dsi_clk_ctrl(msm_host, 1); + pm_runtime_get_sync(&msm_host->pdev->dev); + dsi_link_clk_enable(msm_host); /* TODO: vote for bus bandwidth */ @@ -1911,7 +1915,8 @@ void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, /* TODO: unvote for bus bandwidth */ - dsi_clk_ctrl(msm_host, 0); + dsi_link_clk_disable(msm_host); + pm_runtime_put_autosuspend(&msm_host->pdev->dev); } int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, @@ -2160,8 +2165,11 @@ int msm_dsi_host_enable(struct mipi_dsi_host *host) * and only turned on before MDP START. * This part of code should be enabled once mdp driver support it. */ - /* if (msm_panel->mode == MSM_DSI_CMD_MODE) - dsi_clk_ctrl(msm_host, 0); */ + /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { + * dsi_link_clk_disable(msm_host); + * pm_runtime_put_autosuspend(&msm_host->pdev->dev); + * } + */ return 0; } @@ -2217,9 +2225,11 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, goto unlock_ret; } - ret = dsi_clk_ctrl(msm_host, 1); + pm_runtime_get_sync(&msm_host->pdev->dev); + ret = dsi_link_clk_enable(msm_host); if (ret) { - pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret); + pr_err("%s: failed to enable link clocks. ret=%d\n", + __func__, ret); goto fail_disable_reg; } @@ -2243,7 +2253,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host, return 0; fail_disable_clk: - dsi_clk_ctrl(msm_host, 0); + dsi_link_clk_disable(msm_host); + pm_runtime_put_autosuspend(&msm_host->pdev->dev); fail_disable_reg: dsi_host_regulator_disable(msm_host); unlock_ret: @@ -2268,7 +2279,8 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host) pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); - dsi_clk_ctrl(msm_host, 0); + dsi_link_clk_disable(msm_host); + pm_runtime_put_autosuspend(&msm_host->pdev->dev); dsi_host_regulator_disable(msm_host); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 0c2eb9c9a1fc..7c9bf91bc22b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -373,7 +373,7 @@ static int dsi_phy_enable_resource(struct msm_dsi_phy *phy) static void dsi_phy_disable_resource(struct msm_dsi_phy *phy) { clk_disable_unprepare(phy->ahb_clk); - pm_runtime_put_sync(&phy->pdev->dev); + pm_runtime_put_autosuspend(&phy->pdev->dev); } static const struct of_device_id dsi_phy_dt_match[] = { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index a968cad509c2..17e069a133a4 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -239,6 +239,8 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) hdmi->pwr_clks[i] = clk; } + pm_runtime_enable(&pdev->dev); + hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0); hdmi->i2c = msm_hdmi_i2c_init(hdmi); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index 13ac822dee5d..7e357077ed26 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -35,6 +35,8 @@ static void msm_hdmi_power_on(struct drm_bridge *bridge) const struct hdmi_platform_config *config = hdmi->config; int i, ret; + pm_runtime_get_sync(&hdmi->pdev->dev); + for (i = 0; i < config->pwr_reg_cnt; i++) { ret = regulator_enable(hdmi->pwr_regs[i]); if (ret) { @@ -84,6 +86,8 @@ static void power_off(struct drm_bridge *bridge) config->pwr_reg_names[i], ret); } } + + pm_runtime_put_autosuspend(&hdmi->pdev->dev); } #define AVI_IFRAME_LINE_NUMBER 1 diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c index 71536d9c7fe8..c0848dfedd50 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c @@ -137,6 +137,36 @@ err: return ret; } +static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) +{ + const struct hdmi_platform_config *config = hdmi->config; + struct device *dev = &hdmi->pdev->dev; + int i, ret; + + if (enable) { + for (i = 0; i < config->hpd_clk_cnt; i++) { + if (config->hpd_freq && config->hpd_freq[i]) { + ret = clk_set_rate(hdmi->hpd_clks[i], + config->hpd_freq[i]); + if (ret) + dev_warn(dev, + "failed to set clk %s (%d)\n", + config->hpd_clk_names[i], ret); + } + + ret = clk_prepare_enable(hdmi->hpd_clks[i]); + if (ret) { + dev_err(dev, + "failed to enable hpd clk: %s (%d)\n", + config->hpd_clk_names[i], ret); + } + } + } else { + for (i = config->hpd_clk_cnt - 1; i >= 0; i--) + clk_disable_unprepare(hdmi->hpd_clks[i]); + } +} + static int hpd_enable(struct hdmi_connector *hdmi_connector) { struct hdmi *hdmi = hdmi_connector->hdmi; @@ -167,22 +197,8 @@ static int hpd_enable(struct hdmi_connector *hdmi_connector) goto fail; } - for (i = 0; i < config->hpd_clk_cnt; i++) { - if (config->hpd_freq && config->hpd_freq[i]) { - ret = clk_set_rate(hdmi->hpd_clks[i], - config->hpd_freq[i]); - if (ret) - dev_warn(dev, "failed to set clk %s (%d)\n", - config->hpd_clk_names[i], ret); - } - - ret = clk_prepare_enable(hdmi->hpd_clks[i]); - if (ret) { - dev_err(dev, "failed to enable hpd clk: %s (%d)\n", - config->hpd_clk_names[i], ret); - goto fail; - } - } + pm_runtime_get_sync(dev); + enable_hpd_clocks(hdmi, true); msm_hdmi_set_mode(hdmi, false); msm_hdmi_phy_reset(hdmi); @@ -225,8 +241,8 @@ static void hdp_disable(struct hdmi_connector *hdmi_connector) msm_hdmi_set_mode(hdmi, false); - for (i = 0; i < config->hpd_clk_cnt; i++) - clk_disable_unprepare(hdmi->hpd_clks[i]); + enable_hpd_clocks(hdmi, false); + pm_runtime_put_autosuspend(dev); ret = gpio_config(hdmi, false); if (ret) @@ -285,7 +301,16 @@ void msm_hdmi_connector_irq(struct drm_connector *connector) static enum drm_connector_status detect_reg(struct hdmi *hdmi) { - uint32_t hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); + uint32_t hpd_int_status; + + pm_runtime_get_sync(&hdmi->pdev->dev); + enable_hpd_clocks(hdmi, true); + + hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); + + enable_hpd_clocks(hdmi, false); + pm_runtime_put_autosuspend(&hdmi->pdev->dev); + return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? connector_status_connected : connector_status_disconnected; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c index aa7402e03f67..60790df91bfa 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c @@ -192,6 +192,7 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, { struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); struct mdp5_kms *mdp5_kms; + struct device *dev; int intf_num; u32 data = 0; @@ -214,14 +215,16 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, /* Smart Panel, Sync mode */ data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; + dev = &mdp5_kms->pdev->dev; + /* Make sure clocks are on when connectors calling this function. */ - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, MDP5_SPLIT_DPL_LOWER_SMART_PANEL); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 3a81e26629c7..6fcb58ab718c 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -415,6 +415,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); struct mdp5_kms *mdp5_kms = get_kms(crtc); + struct device *dev = &mdp5_kms->pdev->dev; DBG("%s", crtc->name); @@ -425,7 +426,7 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); mdp5_crtc->enabled = false; } @@ -436,13 +437,17 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); struct mdp5_kms *mdp5_kms = get_kms(crtc); + struct device *dev = &mdp5_kms->pdev->dev; DBG("%s", crtc->name); if (WARN_ON(mdp5_crtc->enabled)) return; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); + + mdp5_crtc_mode_set_nofb(crtc); + mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); if (mdp5_cstate->cmd_mode) @@ -533,7 +538,7 @@ static bool is_fullscreen(struct drm_crtc_state *cstate, ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); } -enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, +static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, struct drm_crtc_state *new_crtc_state, struct drm_plane_state *bpstate) { @@ -727,6 +732,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; struct drm_device *dev = crtc->dev; struct mdp5_kms *mdp5_kms = get_kms(crtc); + struct platform_device *pdev = mdp5_kms->pdev; struct msm_kms *kms = &mdp5_kms->base.base; struct drm_gem_object *cursor_bo, *old_bo = NULL; uint32_t blendcfg, stride; @@ -755,7 +761,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, if (!handle) { DBG("Cursor off"); cursor_enable = false; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(&pdev->dev); goto set_cursor; } @@ -770,6 +776,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, lm = mdp5_cstate->pipeline.mixer->lm; stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0); + pm_runtime_get_sync(&pdev->dev); + spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); old_bo = mdp5_crtc->cursor.scanout_bo; @@ -779,8 +787,6 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, get_roi(crtc, &roi_w, &roi_h); - mdp5_enable(mdp5_kms); - mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); @@ -798,6 +804,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); + pm_runtime_put_autosuspend(&pdev->dev); + set_cursor: ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); if (ret) { @@ -809,7 +817,7 @@ set_cursor: crtc_flush(crtc, flush_mask); end: - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(&pdev->dev); if (old_bo) { drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo); /* enable vblank to complete cursor work: */ @@ -842,7 +850,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) get_roi(crtc, &roi_w, &roi_h); - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(&mdp5_kms->pdev->dev); spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), @@ -855,7 +863,7 @@ static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) crtc_flush(crtc, flush_mask); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(&mdp5_kms->pdev->dev); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index 70bef51245af..5b851380d3f2 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -297,6 +297,10 @@ static void mdp5_encoder_enable(struct drm_encoder *encoder) { struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); struct mdp5_interface *intf = mdp5_encoder->intf; + /* this isn't right I think */ + struct drm_crtc_state *cstate = encoder->crtc->state; + + mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode); if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) mdp5_cmd_encoder_enable(encoder); @@ -320,7 +324,6 @@ static int mdp5_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = { - .mode_set = mdp5_encoder_mode_set, .disable = mdp5_encoder_disable, .enable = mdp5_encoder_enable, .atomic_check = mdp5_encoder_atomic_check, @@ -350,6 +353,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder); struct mdp5_kms *mdp5_kms; + struct device *dev; int intf_num; u32 data = 0; @@ -369,8 +373,10 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, else return -EINVAL; + dev = &mdp5_kms->pdev->dev; /* Make sure clocks are on when connectors calling this function. */ - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); + /* Dumb Panel, Sync mode */ mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); @@ -378,7 +384,7 @@ int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c index 3ce8b9dec9c1..bb5deb00c899 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c @@ -49,16 +49,19 @@ static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) void mdp5_irq_preinstall(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - mdp5_enable(mdp5_kms); + struct device *dev = &mdp5_kms->pdev->dev; + + pm_runtime_get_sync(dev); mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } int mdp5_irq_postinstall(struct msm_kms *kms) { struct mdp_kms *mdp_kms = to_mdp_kms(kms); struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); + struct device *dev = &mdp5_kms->pdev->dev; struct mdp_irq *error_handler = &mdp5_kms->error_handler; error_handler->irq = mdp5_irq_error_handler; @@ -67,9 +70,9 @@ int mdp5_irq_postinstall(struct msm_kms *kms) MDP5_IRQ_INTF2_UNDER_RUN | MDP5_IRQ_INTF3_UNDER_RUN; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp_irq_register(mdp_kms, error_handler); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } @@ -77,9 +80,11 @@ int mdp5_irq_postinstall(struct msm_kms *kms) void mdp5_irq_uninstall(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - mdp5_enable(mdp5_kms); + struct device *dev = &mdp5_kms->pdev->dev; + + pm_runtime_get_sync(dev); mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } irqreturn_t mdp5_irq(struct msm_kms *kms) @@ -109,11 +114,12 @@ irqreturn_t mdp5_irq(struct msm_kms *kms) int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp_update_vblank_mask(to_mdp_kms(kms), mdp5_crtc_vblank(crtc), true); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); return 0; } @@ -121,9 +127,10 @@ int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); mdp_update_vblank_mask(to_mdp_kms(kms), mdp5_crtc_vblank(crtc), false); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index 1c603aef3c59..f7c0698fec40 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -30,11 +30,10 @@ static const char *iommu_ports[] = { static int mdp5_hw_init(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - struct platform_device *pdev = mdp5_kms->pdev; + struct device *dev = &mdp5_kms->pdev->dev; unsigned long flags; - pm_runtime_get_sync(&pdev->dev); - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); /* Magic unknown register writes: * @@ -66,8 +65,7 @@ static int mdp5_hw_init(struct msm_kms *kms) mdp5_ctlm_hw_reset(mdp5_kms->ctlm); - mdp5_disable(mdp5_kms); - pm_runtime_put_sync(&pdev->dev); + pm_runtime_put_sync(dev); return 0; } @@ -111,8 +109,9 @@ static void mdp5_swap_state(struct msm_kms *kms, struct drm_atomic_state *state) static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); if (mdp5_kms->smp) mdp5_smp_prepare_commit(mdp5_kms->smp, &mdp5_kms->state->smp); @@ -121,11 +120,12 @@ static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *st static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + struct device *dev = &mdp5_kms->pdev->dev; if (mdp5_kms->smp) mdp5_smp_complete_commit(mdp5_kms->smp, &mdp5_kms->state->smp); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); } static void mdp5_wait_for_crtc_commit_done(struct msm_kms *kms, @@ -249,6 +249,9 @@ int mdp5_disable(struct mdp5_kms *mdp5_kms) { DBG(""); + mdp5_kms->enable_count--; + WARN_ON(mdp5_kms->enable_count < 0); + clk_disable_unprepare(mdp5_kms->ahb_clk); clk_disable_unprepare(mdp5_kms->axi_clk); clk_disable_unprepare(mdp5_kms->core_clk); @@ -262,6 +265,8 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms) { DBG(""); + mdp5_kms->enable_count++; + clk_prepare_enable(mdp5_kms->ahb_clk); clk_prepare_enable(mdp5_kms->axi_clk); clk_prepare_enable(mdp5_kms->core_clk); @@ -486,11 +491,12 @@ fail: static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, u32 *major, u32 *minor) { + struct device *dev = &mdp5_kms->pdev->dev; u32 version; - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(dev); version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); - mdp5_disable(mdp5_kms); + pm_runtime_put_autosuspend(dev); *major = FIELD(version, MDP5_HW_VERSION_MAJOR); *minor = FIELD(version, MDP5_HW_VERSION_MINOR); @@ -643,7 +649,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) * have left things on, in which case we'll start getting faults if * we don't disable): */ - mdp5_enable(mdp5_kms); + pm_runtime_get_sync(&pdev->dev); for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || !config->hw->intf.base[i]) @@ -652,7 +658,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); } - mdp5_disable(mdp5_kms); mdelay(16); if (config->platform.iommu) { @@ -678,6 +683,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) aspace = NULL;; } + pm_runtime_put_autosuspend(&pdev->dev); + ret = modeset_init(mdp5_kms); if (ret) { dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); @@ -1005,6 +1012,30 @@ static int mdp5_dev_remove(struct platform_device *pdev) return 0; } +static __maybe_unused int mdp5_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); + + DBG(""); + + return mdp5_disable(mdp5_kms); +} + +static __maybe_unused int mdp5_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); + + DBG(""); + + return mdp5_enable(mdp5_kms); +} + +static const struct dev_pm_ops mdp5_pm_ops = { + SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) +}; + static const struct of_device_id mdp5_dt_match[] = { { .compatible = "qcom,mdp5", }, /* to support downstream DT files */ @@ -1019,6 +1050,7 @@ static struct platform_driver mdp5_driver = { .driver = { .name = "msm_mdp", .of_match_table = mdp5_dt_match, + .pm = &mdp5_pm_ops, }, }; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 17caa0e8c8ae..9b3fe01089d1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -76,6 +76,8 @@ struct mdp5_kms { bool rpm_enabled; struct mdp_irq error_handler; + + int enable_count; }; #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) @@ -167,11 +169,13 @@ struct mdp5_encoder { static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) { + WARN_ON(mdp5_kms->enable_count <= 0); msm_writel(data, mdp5_kms->mmio + reg); } static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) { + WARN_ON(mdp5_kms->enable_count <= 0); return msm_readl(mdp5_kms->mmio + reg); } @@ -255,9 +259,6 @@ static inline uint32_t lm2ppdone(struct mdp5_hw_mixer *mixer) return MDP5_IRQ_PING_PONG_0_DONE << mixer->pp; } -int mdp5_disable(struct mdp5_kms *mdp5_kms); -int mdp5_enable(struct mdp5_kms *mdp5_kms); - void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t old_irqmask); void mdp5_irq_preinstall(struct msm_kms *kms); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c index 9c34d7824988..f2a0db7a8a03 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c @@ -31,6 +31,10 @@ struct msm_mdss { struct regulator *vdd; + struct clk *ahb_clk; + struct clk *axi_clk; + struct clk *vsync_clk; + struct { volatile unsigned long enabled_mask; struct irq_domain *domain; @@ -140,6 +144,51 @@ static int mdss_irq_domain_init(struct msm_mdss *mdss) return 0; } +int msm_mdss_enable(struct msm_mdss *mdss) +{ + DBG(""); + + clk_prepare_enable(mdss->ahb_clk); + if (mdss->axi_clk) + clk_prepare_enable(mdss->axi_clk); + if (mdss->vsync_clk) + clk_prepare_enable(mdss->vsync_clk); + + return 0; +} + +int msm_mdss_disable(struct msm_mdss *mdss) +{ + DBG(""); + + if (mdss->vsync_clk) + clk_disable_unprepare(mdss->vsync_clk); + if (mdss->axi_clk) + clk_disable_unprepare(mdss->axi_clk); + clk_disable_unprepare(mdss->ahb_clk); + + return 0; +} + +static int msm_mdss_get_clocks(struct msm_mdss *mdss) +{ + struct platform_device *pdev = to_platform_device(mdss->dev->dev); + + mdss->ahb_clk = msm_clk_get(pdev, "iface"); + if (IS_ERR(mdss->ahb_clk)) + mdss->ahb_clk = NULL; + + mdss->axi_clk = msm_clk_get(pdev, "bus"); + if (IS_ERR(mdss->axi_clk)) + mdss->axi_clk = NULL; + + mdss->vsync_clk = msm_clk_get(pdev, "vsync"); + if (IS_ERR(mdss->vsync_clk)) + mdss->vsync_clk = NULL; + + return 0; +} + void msm_mdss_destroy(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -153,8 +202,6 @@ void msm_mdss_destroy(struct drm_device *dev) regulator_disable(mdss->vdd); - pm_runtime_put_sync(dev->dev); - pm_runtime_disable(dev->dev); } @@ -190,6 +237,12 @@ int msm_mdss_init(struct drm_device *dev) goto fail; } + ret = msm_mdss_get_clocks(mdss); + if (ret) { + dev_err(dev->dev, "failed to get clocks: %d\n", ret); + goto fail; + } + /* Regulator to enable GDSCs in downstream kernels */ mdss->vdd = devm_regulator_get(dev->dev, "vdd"); if (IS_ERR(mdss->vdd)) { @@ -221,12 +274,6 @@ int msm_mdss_init(struct drm_device *dev) pm_runtime_enable(dev->dev); - /* - * TODO: This is needed as the MDSS GDSC is only tied to MDSS's power - * domain. Remove this once runtime PM is adapted for all the devices. - */ - pm_runtime_get_sync(dev->dev); - return 0; fail_irq: regulator_disable(mdss->vdd); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c index 58f712d37e7f..ae4983d9d0a5 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c @@ -28,6 +28,13 @@ struct mdp5_smp { int blk_cnt; int blk_size; + + /* register cache */ + u32 alloc_w[22]; + u32 alloc_r[22]; + u32 pipe_reqprio_fifo_wm0[SSPP_MAX]; + u32 pipe_reqprio_fifo_wm1[SSPP_MAX]; + u32 pipe_reqprio_fifo_wm2[SSPP_MAX]; }; static inline @@ -98,16 +105,15 @@ static int smp_request_block(struct mdp5_smp *smp, static void set_fifo_thresholds(struct mdp5_smp *smp, enum mdp5_pipe pipe, int nblks) { - struct mdp5_kms *mdp5_kms = get_kms(smp); u32 smp_entries_per_blk = smp->blk_size / (128 / BITS_PER_BYTE); u32 val; /* 1/4 of SMP pool that is being fetched */ val = (nblks * smp_entries_per_blk) / 4; - mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), val * 1); - mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), val * 2); - mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), val * 3); + smp->pipe_reqprio_fifo_wm0[pipe] = val * 1; + smp->pipe_reqprio_fifo_wm1[pipe] = val * 2; + smp->pipe_reqprio_fifo_wm2[pipe] = val * 3; } /* @@ -222,7 +228,6 @@ void mdp5_smp_release(struct mdp5_smp *smp, struct mdp5_smp_state *state, static unsigned update_smp_state(struct mdp5_smp *smp, u32 cid, mdp5_smp_state_t *assigned) { - struct mdp5_kms *mdp5_kms = get_kms(smp); int cnt = smp->blk_cnt; unsigned nblks = 0; u32 blk, val; @@ -231,7 +236,7 @@ static unsigned update_smp_state(struct mdp5_smp *smp, int idx = blk / 3; int fld = blk % 3; - val = mdp5_read(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx)); + val = smp->alloc_w[idx]; switch (fld) { case 0: @@ -248,8 +253,8 @@ static unsigned update_smp_state(struct mdp5_smp *smp, break; } - mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val); - mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val); + smp->alloc_w[idx] = val; + smp->alloc_r[idx] = val; nblks++; } @@ -257,6 +262,39 @@ static unsigned update_smp_state(struct mdp5_smp *smp, return nblks; } +static void write_smp_alloc_regs(struct mdp5_smp *smp) +{ + struct mdp5_kms *mdp5_kms = get_kms(smp); + int i, num_regs; + + num_regs = smp->blk_cnt / 3 + 1; + + for (i = 0; i < num_regs; i++) { + mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(i), + smp->alloc_w[i]); + mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(i), + smp->alloc_r[i]); + } +} + +static void write_smp_fifo_regs(struct mdp5_smp *smp) +{ + struct mdp5_kms *mdp5_kms = get_kms(smp); + int i; + + for (i = 0; i < mdp5_kms->num_hwpipes; i++) { + struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; + enum mdp5_pipe pipe = hwpipe->pipe; + + mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(pipe), + smp->pipe_reqprio_fifo_wm0[pipe]); + mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(pipe), + smp->pipe_reqprio_fifo_wm1[pipe]); + mdp5_write(mdp5_kms, REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(pipe), + smp->pipe_reqprio_fifo_wm2[pipe]); + } +} + void mdp5_smp_prepare_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state) { enum mdp5_pipe pipe; @@ -277,6 +315,9 @@ void mdp5_smp_prepare_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state) set_fifo_thresholds(smp, pipe, nblks); } + write_smp_alloc_regs(smp); + write_smp_fifo_regs(smp); + state->assigned = 0; } @@ -289,6 +330,8 @@ void mdp5_smp_complete_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state set_fifo_thresholds(smp, pipe, 0); } + write_smp_fifo_regs(smp); + state->released = 0; } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index f49f6ac5585c..606df7bea97b 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -73,6 +73,10 @@ bool dumpstate = false; MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); module_param(dumpstate, bool, 0600); +static bool modeset = true; +MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); +module_param(modeset, bool, 0600); + /* * Util/helpers: */ @@ -832,7 +836,6 @@ static struct drm_driver msm_driver = { .gem_vm_ops = &vm_ops, .dumb_create = msm_gem_dumb_create, .dumb_map_offset = msm_gem_dumb_map_offset, - .dumb_destroy = drm_gem_dumb_destroy, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_export = drm_gem_prime_export, @@ -879,8 +882,37 @@ static int msm_pm_resume(struct device *dev) } #endif +#ifdef CONFIG_PM +static int msm_runtime_suspend(struct device *dev) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct msm_drm_private *priv = ddev->dev_private; + + DBG(""); + + if (priv->mdss) + return msm_mdss_disable(priv->mdss); + + return 0; +} + +static int msm_runtime_resume(struct device *dev) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct msm_drm_private *priv = ddev->dev_private; + + DBG(""); + + if (priv->mdss) + return msm_mdss_enable(priv->mdss); + + return 0; +} +#endif + static const struct dev_pm_ops msm_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) + SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) }; /* @@ -1104,6 +1136,9 @@ static struct platform_driver msm_platform_driver = { static int __init msm_drm_register(void) { + if (!modeset) + return -EINVAL; + DBG("init"); msm_mdp_register(); msm_dsi_register(); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index fc8d24f7c084..5e8109c07560 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -55,8 +55,6 @@ struct msm_fence_cb; struct msm_gem_address_space; struct msm_gem_vma; -#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ - struct msm_file_private { /* currently we don't do anything useful with this.. but when * per-context address spaces are supported we'd keep track of @@ -237,6 +235,12 @@ struct drm_gem_object *msm_gem_new(struct drm_device *dev, uint32_t size, uint32_t flags); struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev, uint32_t size, uint32_t flags); +void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova); +void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova); struct drm_gem_object *msm_gem_import(struct drm_device *dev, struct dma_buf *dmabuf, struct sg_table *sgt); @@ -248,10 +252,10 @@ uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, struct msm_gem_address_space *aspace, int plane); struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); -struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); +struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, + int w, int h, int p, uint32_t format); struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); void msm_fbdev_free(struct drm_device *dev); diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index 6ecb7b170316..fc175e724ad6 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -20,6 +20,7 @@ #include "msm_drv.h" #include "msm_kms.h" +#include "msm_gem.h" struct msm_framebuffer { struct drm_framebuffer base; @@ -28,6 +29,8 @@ struct msm_framebuffer { }; #define to_msm_framebuffer(x) container_of(x, struct msm_framebuffer, base) +static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, + const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); static int msm_framebuffer_create_handle(struct drm_framebuffer *fb, struct drm_file *file_priv, @@ -161,7 +164,7 @@ out_unref: return ERR_PTR(ret); } -struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, +static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos) { struct msm_drm_private *priv = dev->dev_private; @@ -237,3 +240,43 @@ fail: return ERR_PTR(ret); } + +struct drm_framebuffer * +msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format) +{ + struct drm_mode_fb_cmd2 mode_cmd = { + .pixel_format = format, + .width = w, + .height = h, + .pitches = { p }, + }; + struct drm_gem_object *bo; + struct drm_framebuffer *fb; + int size; + + /* allocate backing bo */ + size = mode_cmd.pitches[0] * mode_cmd.height; + DBG("allocating %d bytes for fb %d", size, dev->primary->index); + bo = msm_gem_new(dev, size, MSM_BO_SCANOUT | MSM_BO_WC | MSM_BO_STOLEN); + if (IS_ERR(bo)) { + dev_warn(dev->dev, "could not allocate stolen bo\n"); + /* try regular bo: */ + bo = msm_gem_new(dev, size, MSM_BO_SCANOUT | MSM_BO_WC); + } + if (IS_ERR(bo)) { + dev_err(dev->dev, "failed to allocate buffer object\n"); + return ERR_CAST(bo); + } + + fb = msm_framebuffer_init(dev, &mode_cmd, &bo); + if (IS_ERR(fb)) { + dev_err(dev->dev, "failed to allocate fb\n"); + /* note: if fb creation failed, we can't rely on fb destroy + * to unref the bo: + */ + drm_gem_object_unreference_unlocked(bo); + return ERR_CAST(fb); + } + + return fb; +} diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index 9c00fedfc741..c178563fcd4d 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c @@ -19,7 +19,6 @@ #include <drm/drm_fb_helper.h> #include "msm_drv.h" -#include "msm_gem.h" #include "msm_kms.h" extern int msm_gem_mmap_obj(struct drm_gem_object *obj, @@ -35,7 +34,6 @@ static int msm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma); struct msm_fbdev { struct drm_fb_helper base; struct drm_framebuffer *fb; - struct drm_gem_object *bo; }; static struct fb_ops msm_fb_ops = { @@ -57,16 +55,16 @@ static int msm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) { struct drm_fb_helper *helper = (struct drm_fb_helper *)info->par; struct msm_fbdev *fbdev = to_msm_fbdev(helper); - struct drm_gem_object *drm_obj = fbdev->bo; + struct drm_gem_object *bo = msm_framebuffer_bo(fbdev->fb, 0); int ret = 0; - ret = drm_gem_mmap_obj(drm_obj, drm_obj->size, vma); + ret = drm_gem_mmap_obj(bo, bo->size, vma); if (ret) { pr_err("%s:drm_gem_mmap_obj fail\n", __func__); return ret; } - return msm_gem_mmap_obj(drm_obj, vma); + return msm_gem_mmap_obj(bo, vma); } static int msm_fbdev_create(struct drm_fb_helper *helper, @@ -76,47 +74,30 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, struct drm_device *dev = helper->dev; struct msm_drm_private *priv = dev->dev_private; struct drm_framebuffer *fb = NULL; + struct drm_gem_object *bo; struct fb_info *fbi = NULL; - struct drm_mode_fb_cmd2 mode_cmd = {0}; uint64_t paddr; - int ret, size; + uint32_t format; + int ret, pitch; + + format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth); DBG("create fbdev: %dx%d@%d (%dx%d)", sizes->surface_width, sizes->surface_height, sizes->surface_bpp, sizes->fb_width, sizes->fb_height); - mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, - sizes->surface_depth); - - mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; - - mode_cmd.pitches[0] = align_pitch( - mode_cmd.width, sizes->surface_bpp); + pitch = align_pitch(sizes->surface_width, sizes->surface_bpp); + fb = msm_alloc_stolen_fb(dev, sizes->surface_width, + sizes->surface_height, pitch, format); - /* allocate backing bo */ - size = mode_cmd.pitches[0] * mode_cmd.height; - DBG("allocating %d bytes for fb %d", size, dev->primary->index); - fbdev->bo = msm_gem_new(dev, size, MSM_BO_SCANOUT | - MSM_BO_WC | MSM_BO_STOLEN); - if (IS_ERR(fbdev->bo)) { - ret = PTR_ERR(fbdev->bo); - fbdev->bo = NULL; - dev_err(dev->dev, "failed to allocate buffer object: %d\n", ret); - goto fail; - } - - fb = msm_framebuffer_init(dev, &mode_cmd, &fbdev->bo); if (IS_ERR(fb)) { dev_err(dev->dev, "failed to allocate fb\n"); - /* note: if fb creation failed, we can't rely on fb destroy - * to unref the bo: - */ - drm_gem_object_unreference_unlocked(fbdev->bo); ret = PTR_ERR(fb); goto fail; } + bo = msm_framebuffer_bo(fb, 0); + mutex_lock(&dev->struct_mutex); /* @@ -124,7 +105,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, * in panic (ie. lock-safe, etc) we could avoid pinning the * buffer now: */ - ret = msm_gem_get_iova(fbdev->bo, priv->kms->aspace, &paddr); + ret = msm_gem_get_iova(bo, priv->kms->aspace, &paddr); if (ret) { dev_err(dev->dev, "failed to get buffer obj iova: %d\n", ret); goto fail_unlock; @@ -152,14 +133,14 @@ static int msm_fbdev_create(struct drm_fb_helper *helper, dev->mode_config.fb_base = paddr; - fbi->screen_base = msm_gem_get_vaddr(fbdev->bo); + fbi->screen_base = msm_gem_get_vaddr(bo); if (IS_ERR(fbi->screen_base)) { ret = PTR_ERR(fbi->screen_base); goto fail_unlock; } - fbi->screen_size = fbdev->bo->size; + fbi->screen_size = bo->size; fbi->fix.smem_start = paddr; - fbi->fix.smem_len = fbdev->bo->size; + fbi->fix.smem_len = bo->size; DBG("par=%p, %dx%d", fbi->par, fbi->var.xres, fbi->var.yres); DBG("allocated %dx%d fb", fbdev->fb->width, fbdev->fb->height); @@ -241,7 +222,9 @@ void msm_fbdev_free(struct drm_device *dev) /* this will free the backing object */ if (fbdev->fb) { - msm_gem_put_vaddr(fbdev->bo); + struct drm_gem_object *bo = + msm_framebuffer_bo(fbdev->fb, 0); + msm_gem_put_vaddr(bo); drm_framebuffer_remove(fbdev->fb); } diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index a0c60e738db8..f15821a0d900 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -1024,3 +1024,49 @@ fail: drm_gem_object_unreference_unlocked(obj); return ERR_PTR(ret); } + +static void *_msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova, bool locked) +{ + void *vaddr; + struct drm_gem_object *obj = _msm_gem_new(dev, size, flags, locked); + int ret; + + if (IS_ERR(obj)) + return ERR_CAST(obj); + + if (iova) { + ret = msm_gem_get_iova(obj, aspace, iova); + if (ret) { + drm_gem_object_unreference(obj); + return ERR_PTR(ret); + } + } + + vaddr = msm_gem_get_vaddr(obj); + if (!vaddr) { + msm_gem_put_iova(obj, aspace); + drm_gem_object_unreference(obj); + return ERR_PTR(-ENOMEM); + } + + if (bo) + *bo = obj; + + return vaddr; +} + +void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova) +{ + return _msm_gem_kernel_new(dev, size, flags, aspace, bo, iova, false); +} + +void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size, + uint32_t flags, struct msm_gem_address_space *aspace, + struct drm_gem_object **bo, uint64_t *iova) +{ + return _msm_gem_kernel_new(dev, size, flags, aspace, bo, iova, true); +} diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 9f3dbc236ab3..ffbff27600e0 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -562,11 +562,49 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) return 0; } +static struct msm_gem_address_space * +msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev, + uint64_t va_start, uint64_t va_end) +{ + struct iommu_domain *iommu; + struct msm_gem_address_space *aspace; + int ret; + + /* + * Setup IOMMU.. eventually we will (I think) do this once per context + * and have separate page tables per context. For now, to keep things + * simple and to get something working, just use a single address space: + */ + iommu = iommu_domain_alloc(&platform_bus_type); + if (!iommu) + return NULL; + + iommu->geometry.aperture_start = va_start; + iommu->geometry.aperture_end = va_end; + + dev_info(gpu->dev->dev, "%s: using IOMMU\n", gpu->name); + + aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu"); + if (IS_ERR(aspace)) { + dev_err(gpu->dev->dev, "failed to init iommu: %ld\n", + PTR_ERR(aspace)); + iommu_domain_free(iommu); + return ERR_CAST(aspace); + } + + ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0); + if (ret) { + msm_gem_address_space_put(aspace); + return ERR_PTR(ret); + } + + return aspace; +} + int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, const char *name, struct msm_gpu_config *config) { - struct iommu_domain *iommu; int ret; if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) @@ -636,28 +674,19 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (IS_ERR(gpu->gpu_cx)) gpu->gpu_cx = NULL; - /* Setup IOMMU.. eventually we will (I think) do this once per context - * and have separate page tables per context. For now, to keep things - * simple and to get something working, just use a single address space: - */ - iommu = iommu_domain_alloc(&platform_bus_type); - if (iommu) { - iommu->geometry.aperture_start = config->va_start; - iommu->geometry.aperture_end = config->va_end; - - dev_info(drm->dev, "%s: using IOMMU\n", name); - gpu->aspace = msm_gem_address_space_create(&pdev->dev, - iommu, "gpu"); - if (IS_ERR(gpu->aspace)) { - ret = PTR_ERR(gpu->aspace); - dev_err(drm->dev, "failed to init iommu: %d\n", ret); - gpu->aspace = NULL; - iommu_domain_free(iommu); - goto fail; - } + gpu->pdev = pdev; + platform_set_drvdata(pdev, gpu); + + bs_init(gpu); - } else { + gpu->aspace = msm_gpu_create_address_space(gpu, pdev, + config->va_start, config->va_end); + + if (gpu->aspace == NULL) dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); + else if (IS_ERR(gpu->aspace)) { + ret = PTR_ERR(gpu->aspace); + goto fail; } /* Create ringbuffer: */ @@ -669,14 +698,10 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, goto fail; } - gpu->pdev = pdev; - platform_set_drvdata(pdev, gpu); - - bs_init(gpu); - return 0; fail: + platform_set_drvdata(pdev, NULL); return ret; } @@ -693,7 +718,9 @@ void msm_gpu_cleanup(struct msm_gpu *gpu) msm_gem_put_iova(gpu->rb->bo, gpu->aspace); msm_ringbuffer_destroy(gpu->rb); } - - if (gpu->fctx) - msm_fence_context_free(gpu->fctx); + if (gpu->aspace) { + gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu, + NULL, 0); + msm_gem_address_space_put(gpu->aspace); + } } diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index a8f2ba5e5f07..17d5824417ad 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -99,5 +99,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev); struct msm_kms *mdp5_kms_init(struct drm_device *dev); int msm_mdss_init(struct drm_device *dev); void msm_mdss_destroy(struct drm_device *dev); +int msm_mdss_enable(struct msm_mdss *mdss); +int msm_mdss_disable(struct msm_mdss *mdss); #endif /* __MSM_KMS_H__ */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 791bca3c6a9c..bf065a540130 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -33,16 +33,14 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int size) } ring->gpu = gpu; - ring->bo = msm_gem_new(gpu->dev, size, MSM_BO_WC); - if (IS_ERR(ring->bo)) { - ret = PTR_ERR(ring->bo); - ring->bo = NULL; - goto fail; - } - ring->start = msm_gem_get_vaddr(ring->bo); + /* Pass NULL for the iova pointer - we will map it later */ + ring->start = msm_gem_kernel_new(gpu->dev, size, MSM_BO_WC, + gpu->aspace, &ring->bo, NULL); + if (IS_ERR(ring->start)) { ret = PTR_ERR(ring->start); + ring->start = 0; goto fail; } ring->end = ring->start + (size / 4); diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 93c38eb6d187..7fbad9cb656e 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -337,8 +337,6 @@ static struct drm_driver mxsfb_driver = { .gem_free_object_unlocked = drm_gem_cma_free_object, .gem_vm_ops = &drm_gem_cma_vm_ops, .dumb_create = drm_gem_cma_dumb_create, - .dumb_map_offset = drm_gem_cma_dumb_map_offset, - .dumb_destroy = drm_gem_dumb_destroy, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_export = drm_gem_prime_export, diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 8f689f1f6122..6aa6ee16dcbd 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -1096,6 +1096,38 @@ static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { .disable = nv_crtc_disable, }; +static const uint32_t modeset_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB1555, +}; + +static struct drm_plane * +create_primary_plane(struct drm_device *dev) +{ + struct drm_plane *primary; + int ret; + + primary = kzalloc(sizeof(*primary), GFP_KERNEL); + if (primary == NULL) { + DRM_DEBUG_KMS("Failed to allocate primary plane\n"); + return NULL; + } + + /* possible_crtc's will be filled in later by crtc_init */ + ret = drm_universal_plane_init(dev, primary, 0, + &drm_primary_helper_funcs, + modeset_formats, + ARRAY_SIZE(modeset_formats), NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) { + kfree(primary); + primary = NULL; + } + + return primary; +} + int nv04_crtc_create(struct drm_device *dev, int crtc_num) { @@ -1114,7 +1146,9 @@ nv04_crtc_create(struct drm_device *dev, int crtc_num) nv_crtc->save = nv_crtc_save; nv_crtc->restore = nv_crtc_restore; - drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); + drm_crtc_init_with_planes(dev, &nv_crtc->base, + create_primary_plane(dev), NULL, + &nv04_crtc_funcs, NULL); drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index e54944d23268..c8c2333f24ee 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -63,6 +63,7 @@ static uint32_t formats[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_NV12, + DRM_FORMAT_NV21, }; /* Sine can be approximated with @@ -90,6 +91,26 @@ cos_mul(int degrees, int factor) } static int +verify_scaling(const struct drm_framebuffer *fb, uint8_t shift, + uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, + uint32_t crtc_w, uint32_t crtc_h) +{ + if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { + DRM_DEBUG_KMS("Unsuitable framebuffer scaling: %dx%d -> %dx%d\n", + src_w, src_h, crtc_w, crtc_h); + return -ERANGE; + } + + if (src_x != 0 || src_y != 0) { + DRM_DEBUG_KMS("Unsuitable framebuffer offset: %d,%d\n", + src_x, src_y); + return -ERANGE; + } + + return 0; +} + +static int nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, @@ -107,7 +128,9 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool flip = nv_plane->flip; int soff = NV_PCRTC0_SIZE * nv_crtc->index; int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index; - int format, ret; + unsigned shift = drm->client.device.info.chipset >= 0x30 ? 1 : 3; + unsigned format = 0; + int ret; /* Source parameters given in 16.16 fixed point, ignore fractional. */ src_x >>= 16; @@ -115,18 +138,9 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, src_w >>= 16; src_h >>= 16; - format = ALIGN(src_w * 4, 0x100); - - if (format > 0xffff) - return -ERANGE; - - if (drm->client.device.info.chipset >= 0x30) { - if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) - return -ERANGE; - } else { - if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3)) - return -ERANGE; - } + ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); + if (ret) + return ret; ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false); if (ret) @@ -146,21 +160,23 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); - if (fb->format->format != DRM_FORMAT_UYVY) + if (fb->format->format == DRM_FORMAT_YUYV || + fb->format->format == DRM_FORMAT_NV12) format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; - if (fb->format->format == DRM_FORMAT_NV12) + if (fb->format->format == DRM_FORMAT_NV12 || + fb->format->format == DRM_FORMAT_NV21) format |= NV_PVIDEO_FORMAT_PLANAR; if (nv_plane->iturbt_709) format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; if (nv_plane->colorkey & (1 << 24)) format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; - if (fb->format->format == DRM_FORMAT_NV12) { + if (format & NV_PVIDEO_FORMAT_PLANAR) { nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset + fb->offsets[1]); } - nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format); + nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]); nvif_wr32(dev, NV_PVIDEO_STOP, 0); /* TODO: wait for vblank? */ nvif_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1); @@ -357,7 +373,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct nouveau_bo *cur = nv_plane->cur; uint32_t overlay = 1; int brightness = (nv_plane->brightness - 512) * 62 / 512; - int pitch, ret, i; + int ret, i; /* Source parameters given in 16.16 fixed point, ignore fractional. */ src_x >>= 16; @@ -365,17 +381,9 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, src_w >>= 16; src_h >>= 16; - pitch = ALIGN(src_w * 4, 0x100); - - if (pitch > 0xffff) - return -ERANGE; - - /* TODO: Compute an offset? Not sure how to do this for YUYV. */ - if (src_x != 0 || src_y != 0) - return -ERANGE; - - if (crtc_w < src_w || crtc_h < src_h) - return -ERANGE; + ret = verify_scaling(fb, 0, src_x, src_y, src_w, src_h, crtc_w, crtc_h); + if (ret) + return ret; ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM, false); if (ret) @@ -389,8 +397,9 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, for (i = 0; i < 2; i++) { nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, - nv_fb->nvbo->bo.offset); - nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch); + nv_fb->nvbo->bo.offset); + nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, + fb->pitches[0]); nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); } nvif_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h index e8e77ee24776..deb477282dde 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h @@ -18,6 +18,7 @@ enum dcb_connector_type { DCB_CONNECTOR_HDMI_C = 0x63, DCB_CONNECTOR_DMS59_DP0 = 0x64, DCB_CONNECTOR_DMS59_DP1 = 0x65, + DCB_CONNECTOR_WFD = 0x70, DCB_CONNECTOR_NONE = 0xff }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h index 4892a65ddd48..903d117603d8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h @@ -6,6 +6,7 @@ enum dcb_output_type { DCB_OUTPUT_TMDS = 0x2, DCB_OUTPUT_LVDS = 0x3, DCB_OUTPUT_DP = 0x6, + DCB_OUTPUT_WFD = 0x8, DCB_OUTPUT_EOL = 0xe, DCB_OUTPUT_UNUSED = 0xf, DCB_OUTPUT_ANY = -1, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h index b268b96faece..1bfd93b85575 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -96,4 +96,5 @@ int g84_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gt215_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **); int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **); +int gm200_therm_new(struct nvkm_device *, int, struct nvkm_therm **); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index b998c33af18a..dd6fba55ad5d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -351,11 +351,8 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) struct lvdstableheader lth; if (bios->fp.fptablepointer == 0x0) { - /* Apple cards don't have the fp table; the laptops use DDC */ - /* The table is also missing on some x86 IGPs */ -#ifndef __powerpc__ - NV_ERROR(drm, "Pointer to flat panel table invalid\n"); -#endif + /* Most laptop cards lack an fp table. They use DDC. */ + NV_DEBUG(drm, "Pointer to flat panel table invalid\n"); bios->digital_min_front_porch = 0x4b; return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 5137155bf3c0..70d8e0d69ad5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -1184,6 +1184,7 @@ drm_conntype_from_dcb(enum dcb_connector_type dcb) case DCB_CONNECTOR_HDMI_0 : case DCB_CONNECTOR_HDMI_1 : case DCB_CONNECTOR_HDMI_C : return DRM_MODE_CONNECTOR_HDMIA; + case DCB_CONNECTOR_WFD : return DRM_MODE_CONNECTOR_VIRTUAL; default: break; } diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index d66640047913..2e7785f49e6d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -231,9 +231,30 @@ nouveau_framebuffer_new(struct drm_device *dev, struct nouveau_bo *nvbo, struct nouveau_framebuffer **pfb) { + struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_framebuffer *fb; int ret; + /* YUV overlays have special requirements pre-NV50 */ + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA && + + (mode_cmd->pixel_format == DRM_FORMAT_YUYV || + mode_cmd->pixel_format == DRM_FORMAT_UYVY || + mode_cmd->pixel_format == DRM_FORMAT_NV12 || + mode_cmd->pixel_format == DRM_FORMAT_NV21) && + (mode_cmd->pitches[0] & 0x3f || /* align 64 */ + mode_cmd->pitches[0] >= 0x10000 || /* at most 64k pitch */ + (mode_cmd->pitches[1] && /* pitches for planes must match */ + mode_cmd->pitches[0] != mode_cmd->pitches[1]))) { + struct drm_format_name_buf format_name; + DRM_DEBUG_KMS("Unsuitable framebuffer: format: %s; pitches: 0x%x\n 0x%x\n", + drm_get_format_name(mode_cmd->pixel_format, + &format_name), + mode_cmd->pitches[0], + mode_cmd->pitches[1]); + return -EINVAL; + } + if (!(fb = *pfb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index df7e2037031a..595630d1fb9e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -585,18 +585,18 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) nouveau_led_suspend(dev); if (dev->mode_config.num_crtc) { - NV_INFO(drm, "suspending console...\n"); + NV_DEBUG(drm, "suspending console...\n"); nouveau_fbcon_set_suspend(dev, 1); - NV_INFO(drm, "suspending display...\n"); + NV_DEBUG(drm, "suspending display...\n"); ret = nouveau_display_suspend(dev, runtime); if (ret) return ret; } - NV_INFO(drm, "evicting buffers...\n"); + NV_DEBUG(drm, "evicting buffers...\n"); ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); - NV_INFO(drm, "waiting for kernel channels to go idle...\n"); + NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); if (drm->cechan) { ret = nouveau_channel_idle(drm->cechan); if (ret) @@ -609,7 +609,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) goto fail_display; } - NV_INFO(drm, "suspending fence...\n"); + NV_DEBUG(drm, "suspending fence...\n"); if (drm->fence && nouveau_fence(drm)->suspend) { if (!nouveau_fence(drm)->suspend(drm)) { ret = -ENOMEM; @@ -617,7 +617,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) } } - NV_INFO(drm, "suspending object tree...\n"); + NV_DEBUG(drm, "suspending object tree...\n"); ret = nvif_client_suspend(&drm->client.base); if (ret) goto fail_client; @@ -630,7 +630,7 @@ fail_client: fail_display: if (dev->mode_config.num_crtc) { - NV_INFO(drm, "resuming display...\n"); + NV_DEBUG(drm, "resuming display...\n"); nouveau_display_resume(dev, runtime); } return ret; @@ -641,19 +641,19 @@ nouveau_do_resume(struct drm_device *dev, bool runtime) { struct nouveau_drm *drm = nouveau_drm(dev); - NV_INFO(drm, "resuming object tree...\n"); + NV_DEBUG(drm, "resuming object tree...\n"); nvif_client_resume(&drm->client.base); - NV_INFO(drm, "resuming fence...\n"); + NV_DEBUG(drm, "resuming fence...\n"); if (drm->fence && nouveau_fence(drm)->resume) nouveau_fence(drm)->resume(drm); nouveau_run_vbios_init(dev); if (dev->mode_config.num_crtc) { - NV_INFO(drm, "resuming display...\n"); + NV_DEBUG(drm, "resuming display...\n"); nouveau_display_resume(dev, runtime); - NV_INFO(drm, "resuming console...\n"); + NV_DEBUG(drm, "resuming console...\n"); nouveau_fbcon_set_suspend(dev, 0); } diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 999c35a25498..b0ad7fcefcf5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -179,7 +179,8 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, } static void -nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, + struct drm_printer *printer) { } @@ -252,7 +253,8 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, } static void -nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +nv04_gart_manager_debug(struct ttm_mem_type_manager *man, + struct drm_printer *printer) { } diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 2efcfb18024d..2dbf62a2ac41 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -3141,7 +3141,7 @@ nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, mstc->connector.funcs->reset(&mstc->connector); nouveau_conn_attach_properties(&mstc->connector); - for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++) + for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++) drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); @@ -3897,7 +3897,7 @@ static void nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; - struct drm_crtc_state *new_crtc_state; + struct drm_crtc_state *new_crtc_state, *old_crtc_state; struct drm_crtc *crtc; struct drm_plane_state *new_plane_state; struct drm_plane *plane; @@ -3918,13 +3918,13 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) mutex_lock(&disp->mutex); /* Disable head(s). */ - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); struct nv50_head *head = nv50_head(crtc); NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, asyh->clr.mask, asyh->set.mask); - if (new_crtc_state->active && !asyh->state.active) + if (old_crtc_state->active && !new_crtc_state->active) drm_crtc_vblank_off(crtc); if (asyh->clr.mask) { @@ -4000,7 +4000,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) } /* Update head(s). */ - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); struct nv50_head *head = nv50_head(crtc); @@ -4012,10 +4012,10 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) interlock_core = 1; } - if (asyh->state.active) { - if (!new_crtc_state->active) + if (new_crtc_state->active) { + if (!old_crtc_state->active) drm_crtc_vblank_on(crtc); - if (asyh->state.event) + if (new_crtc_state->event) drm_crtc_vblank_get(crtc); } } @@ -4064,13 +4064,14 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) if (new_crtc_state->event) { unsigned long flags; /* Get correct count/ts if racing with vblank irq */ - if (crtc->state->active) + if (new_crtc_state->active) drm_crtc_accurate_vblank_count(crtc); spin_lock_irqsave(&crtc->dev->event_lock, flags); drm_crtc_send_vblank_event(crtc, new_crtc_state->event); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + new_crtc_state->event = NULL; - if (crtc->state->active) + if (new_crtc_state->active) drm_crtc_vblank_put(crtc); } } @@ -4450,11 +4451,13 @@ nv50_display_create(struct drm_device *dev) /* create crtc objects to represent the hw heads */ if (disp->disp->oclass >= GF110_DISP) - crtcs = nvif_rd32(&device->object, 0x022448); + crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; else - crtcs = 2; + crtcs = 0x3; - for (i = 0; i < crtcs; i++) { + for (i = 0; i < fls(crtcs); i++) { + if (!(crtcs & (1 << i))) + continue; ret = nv50_head_create(dev, i); if (ret) goto out; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7bdc7a5ae723..e096a5d9c292 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2043,6 +2043,7 @@ nv120_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2077,6 +2078,7 @@ nv124_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2111,6 +2113,7 @@ nv126_chipset = { .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gm107_pmu_new, + .therm = gm200_therm_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2321,6 +2324,35 @@ nv137_chipset = { }; static const struct nvkm_device_chip +nv138_chipset = { + .name = "GP108", + .bar = gf100_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .devinit = gm200_devinit_new, + .fb = gp102_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gm200_i2c_new, + .ibus = gm200_ibus_new, + .imem = nv50_instmem_new, + .ltc = gp100_ltc_new, + .mc = gp100_mc_new, + .mmu = gf100_mmu_new, + .pci = gp100_pci_new, + .pmu = gp102_pmu_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, + .ce[0] = gp102_ce_new, + .ce[1] = gp102_ce_new, + .ce[2] = gp102_ce_new, + .ce[3] = gp102_ce_new, + .disp = gp102_disp_new, + .dma = gf119_dma_new, + .fifo = gp100_fifo_new, +}; + +static const struct nvkm_device_chip nv13b_chipset = { .name = "GP10B", .bar = gk20a_bar_new, @@ -2782,6 +2814,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x134: device->chip = &nv134_chipset; break; case 0x136: device->chip = &nv136_chipset; break; case 0x137: device->chip = &nv137_chipset; break; + case 0x138: device->chip = &nv138_chipset; break; case 0x13b: device->chip = &nv13b_chipset; break; default: nvdev_error(device, "unknown chipset (%08x)\n", boot0); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 88582af8bd89..93a75e5b2791 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -285,6 +285,10 @@ nvkm_disp_oneinit(struct nvkm_engine *engine) case DCB_OUTPUT_DP: ret = nvkm_dp_new(disp, i, &dcbE, &outp); break; + case DCB_OUTPUT_WFD: + /* No support for WFD yet. */ + ret = -ENODEV; + continue; default: nvkm_warn(subdev, "dcb %d type %d unknown\n", i, dcbE.type); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c index b33552757647..9fd7ae331308 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/headgf119.c @@ -92,5 +92,8 @@ gf119_head = { int gf119_head_new(struct nvkm_disp *disp, int id) { + struct nvkm_device *device = disp->engine.subdev.device; + if (!(nvkm_rd32(device, 0x612004) & (0x00000001 << id))) + return 0; return nvkm_head_new_(&gf119_head, disp, id); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 8a8895246d26..7fea7d45202f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -124,6 +124,8 @@ nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) static bool nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) { + struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg); + struct nvkm_subdev *subdev = &mpeg->engine.subdev; u32 inst = data << 4; u32 dma0 = nvkm_rd32(device, 0x700000 + inst); u32 dma1 = nvkm_rd32(device, 0x700004 + inst); @@ -132,8 +134,11 @@ nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) u32 size = dma1 + 1; /* only allow linear DMA objects */ - if (!(dma0 & 0x00002000)) + if (!(dma0 & 0x00002000)) { + nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n", + inst, dma0, dma1, dma2); return false; + } if (mthd == 0x0190) { /* DMA_CMD */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index 16de5bd94b14..b5ec7c504dc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -31,6 +31,8 @@ bool nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) { struct nvkm_instmem *imem = device->imem; + struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg); + struct nvkm_subdev *subdev = &mpeg->engine.subdev; u32 inst = data << 4; u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); u32 dma1 = nvkm_instmem_rd32(imem, inst + 4); @@ -39,8 +41,11 @@ nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) u32 size = dma1 + 1; /* only allow linear DMA objects */ - if (!(dma0 & 0x00002000)) + if (!(dma0 & 0x00002000)) { + nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n", + inst, dma0, dma1, dma2); return false; + } if (mthd == 0x0190) { /* DMA_CMD */ diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c index d45d7947a964..77273b53672c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue.c @@ -251,7 +251,7 @@ cmd_write(struct nvkm_msgqueue *priv, struct nvkm_msgqueue_hdr *cmd, struct nvkm_msgqueue_queue *queue) { const struct nvkm_subdev *subdev = priv->falcon->owner; - static unsigned long timeout = ~0; + static unsigned timeout = 2000; unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); int ret = -EAGAIN; bool commit = true; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 6d8f21290aa2..676c167c95b9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -24,6 +24,7 @@ #include "gf100.h" #include <core/gpuobj.h> +#include <core/option.h> #include <subdev/fb.h> #include <subdev/mmu.h> @@ -59,6 +60,8 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, return ret; bar_len = device->func->resource_size(device, bar_nr); + if (bar_nr == 3 && bar->bar2_halve) + bar_len >>= 1; ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm); if (ret) @@ -129,6 +132,8 @@ gf100_bar_init(struct nvkm_bar *base) if (bar->bar[0].mem) { addr = nvkm_memory_addr(bar->bar[0].mem) >> 12; + if (bar->bar2_halve) + addr |= 0x40000000; nvkm_wr32(device, 0x001714, 0x80000000 | addr); } @@ -161,6 +166,7 @@ gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) return -ENOMEM; nvkm_bar_ctor(func, device, index, &bar->base); + bar->bar2_halve = nvkm_boolopt(device->cfgopt, "NvBar2Halve", false); *pbar = &bar->base; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h index f7dea69640d8..20a5255362ba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h @@ -11,6 +11,7 @@ struct gf100_bar_vm { struct gf100_bar { struct nvkm_bar base; + bool bar2_halve; struct gf100_bar_vm bar[2]; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 3841ad6be99e..a239e73562c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -60,12 +60,12 @@ gf100_fb_oneinit(struct nvkm_fb *base) size = min(size, 0x1000); ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, - false, &fb->base.mmu_rd); + true, &fb->base.mmu_rd); if (ret) return ret; ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, size, 0x1000, - false, &fb->base.mmu_wr); + true, &fb->base.mmu_wr); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index d2c4d6033abb..f93766418056 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -27,6 +27,7 @@ static const struct nvkm_mc_map gf100_mc_reset[] = { { 0x00020000, NVKM_ENGINE_MSPDEC }, { 0x00008000, NVKM_ENGINE_MSVLD }, + { 0x00002000, NVKM_SUBDEV_PMU, true }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, { 0x00000080, NVKM_ENGINE_CE1 }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index eb9b278198b2..a4cb82495cee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -192,6 +192,10 @@ nvkm_pci_new_(const struct nvkm_pci_func *func, struct nvkm_device *device, } } +#ifdef __BIG_ENDIAN + pci->msi = false; +#endif + pci->msi = nvkm_boolopt(device->cfgopt, "NvMSI", pci->msi); if (pci->msi && func->msi_rearm) { pci->msi = pci_enable_msi(pci->pdev) == 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index 3306f9fe7140..ce70a193caa7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -75,7 +75,7 @@ nvkm_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; - if (!(nvkm_rd32(device, 0x000200) & 0x00002000)) + if (!pmu->func->enabled(pmu)) return 0; /* Inhibit interrupts, and wait for idle. */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c index 0e36d4cb7201..0b458656e870 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c @@ -24,13 +24,30 @@ #include "priv.h" #include "fuc/gf100.fuc3.h" +#include <subdev/mc.h> + +void +gf100_pmu_reset(struct nvkm_pmu *pmu) +{ + struct nvkm_device *device = pmu->subdev.device; + nvkm_mc_disable(device, NVKM_SUBDEV_PMU); + nvkm_mc_enable(device, NVKM_SUBDEV_PMU); +} + +bool +gf100_pmu_enabled(struct nvkm_pmu *pmu) +{ + return nvkm_mc_enabled(pmu->subdev.device, NVKM_SUBDEV_PMU); +} + static const struct nvkm_pmu_func gf100_pmu = { .code.data = gf100_pmu_code, .code.size = sizeof(gf100_pmu_code), .data.data = gf100_pmu_data, .data.size = sizeof(gf100_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c index 0e4ba4248b15..3dfa79d4fb13 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c @@ -30,7 +30,8 @@ gf119_pmu = { .code.size = sizeof(gf119_pmu_code), .data.data = gf119_pmu_data, .data.size = sizeof(gf119_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index 2ad858d825ac..8f7ec10fd2a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -109,7 +109,8 @@ gk104_pmu = { .code.size = sizeof(gk104_pmu_code), .data.data = gk104_pmu_data, .data.size = sizeof(gk104_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c index fc4b8ecfdaeb..345741d55a56 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c @@ -88,7 +88,8 @@ gk110_pmu = { .code.size = sizeof(gk110_pmu_code), .data.data = gk110_pmu_data, .data.size = sizeof(gk110_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c index e9a91277683a..e4acf7876ea1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c @@ -30,7 +30,8 @@ gk208_pmu = { .code.size = sizeof(gk208_pmu_code), .data.data = gk208_pmu_data, .data.size = sizeof(gk208_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index 978aae3c1001..05e81855c367 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -196,9 +196,10 @@ gk20a_dvfs_data= { static const struct nvkm_pmu_func gk20a_pmu = { + .enabled = gf100_pmu_enabled, .init = gk20a_pmu_init, .fini = gk20a_pmu_fini, - .reset = gt215_pmu_reset, + .reset = gf100_pmu_reset, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c index 9a248ed75f09..459df1ef9e70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c @@ -32,7 +32,8 @@ gm107_pmu = { .code.size = sizeof(gm107_pmu_code), .data.data = gm107_pmu_data, .data.size = sizeof(gm107_pmu_data), - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, .intr = gt215_pmu_intr, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 44bef22bce52..31c843145c7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -38,6 +38,7 @@ gm20b_pmu_recv(struct nvkm_pmu *pmu) static const struct nvkm_pmu_func gm20b_pmu = { + .enabled = gf100_pmu_enabled, .intr = gt215_pmu_intr, .recv = gm20b_pmu_recv, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c index 6c41c20c85a7..e210cd6af816 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c @@ -25,7 +25,8 @@ static const struct nvkm_pmu_func gp100_pmu = { - .reset = gt215_pmu_reset, + .enabled = gf100_pmu_enabled, + .reset = gf100_pmu_reset, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c index f017352206c9..98c7a2a8afc4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c @@ -31,8 +31,15 @@ gp102_pmu_reset(struct nvkm_pmu *pmu) nvkm_mask(device, 0x10a3c0, 0x00000001, 0x00000000); } +static bool +gp102_pmu_enabled(struct nvkm_pmu *pmu) +{ + return !(nvkm_rd32(pmu->subdev.device, 0x10a3c0) & 0x00000001); +} + static const struct nvkm_pmu_func gp102_pmu = { + .enabled = gp102_pmu_enabled, .reset = gp102_pmu_reset, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c index 90d428b3be97..e04216daea58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -180,13 +180,19 @@ gt215_pmu_fini(struct nvkm_pmu *pmu) nvkm_wr32(pmu->subdev.device, 0x10a014, 0x00000060); } -void +static void gt215_pmu_reset(struct nvkm_pmu *pmu) { struct nvkm_device *device = pmu->subdev.device; - nvkm_mask(device, 0x000200, 0x00002000, 0x00000000); - nvkm_mask(device, 0x000200, 0x00002000, 0x00002000); - nvkm_rd32(device, 0x000200); + nvkm_mask(device, 0x022210, 0x00000001, 0x00000000); + nvkm_mask(device, 0x022210, 0x00000001, 0x00000001); + nvkm_rd32(device, 0x022210); +} + +static bool +gt215_pmu_enabled(struct nvkm_pmu *pmu) +{ + return nvkm_rd32(pmu->subdev.device, 0x022210) & 0x00000001; } int @@ -241,6 +247,7 @@ gt215_pmu = { .code.size = sizeof(gt215_pmu_code), .data.data = gt215_pmu_data, .data.size = sizeof(gt215_pmu_data), + .enabled = gt215_pmu_enabled, .reset = gt215_pmu_reset, .init = gt215_pmu_init, .fini = gt215_pmu_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index 096cba069f72..a4c48a10cd47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -20,6 +20,7 @@ struct nvkm_pmu_func { u32 size; } data; + bool (*enabled)(struct nvkm_pmu *); void (*reset)(struct nvkm_pmu *); int (*init)(struct nvkm_pmu *); void (*fini)(struct nvkm_pmu *); @@ -30,12 +31,14 @@ struct nvkm_pmu_func { void (*pgob)(struct nvkm_pmu *, bool); }; -void gt215_pmu_reset(struct nvkm_pmu *); int gt215_pmu_init(struct nvkm_pmu *); void gt215_pmu_fini(struct nvkm_pmu *); void gt215_pmu_intr(struct nvkm_pmu *); void gt215_pmu_recv(struct nvkm_pmu *); int gt215_pmu_send(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); +bool gf100_pmu_enabled(struct nvkm_pmu *); +void gf100_pmu_reset(struct nvkm_pmu *); + void gk110_pmu_pgob(struct nvkm_pmu *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild index 135758ba3e28..2bafcc1d1818 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/Kbuild @@ -11,3 +11,4 @@ nvkm-y += nvkm/subdev/therm/g84.o nvkm-y += nvkm/subdev/therm/gt215.o nvkm-y += nvkm/subdev/therm/gf119.o nvkm-y += nvkm/subdev/therm/gm107.o +nvkm-y += nvkm/subdev/therm/gm200.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c index 86e81930d8ee..96f8da40ac82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c @@ -203,7 +203,7 @@ g84_therm_fini(struct nvkm_therm *therm) nvkm_wr32(device, 0x1100, 0x10000); /* PBUS */ } -static void +void g84_therm_init(struct nvkm_therm *therm) { g84_sensor_setup(therm); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c new file mode 100644 index 000000000000..73dc78093d5d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.c @@ -0,0 +1,39 @@ +/* + * Copyright 2017 Karol Herbst + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Karol Herbst + */ +#include "priv.h" + +static const struct nvkm_therm_func +gm200_therm = { + .init = g84_therm_init, + .fini = g84_therm_fini, + .temp_get = g84_temp_get, + .program_alarms = nvkm_therm_program_alarms_polling, +}; + +int +gm200_therm_new(struct nvkm_device *device, int index, + struct nvkm_therm **ptherm) +{ + return nvkm_therm_new_(&gm200_therm, device, index, ptherm); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h index 235a5d8daff6..1f46e371d7c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/priv.h @@ -111,6 +111,7 @@ void g84_therm_fini(struct nvkm_therm *); int gt215_therm_fan_sense(struct nvkm_therm *); +void g84_therm_init(struct nvkm_therm *); void gf119_therm_init(struct nvkm_therm *); int nvkm_fanpwm_create(struct nvkm_therm *, struct dcb_gpio_func *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c index e93b2410c38b..ddb2b2c600ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c @@ -83,7 +83,7 @@ nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, { struct nvkm_subdev *subdev = &therm->subdev; bool active; - const char *thresolds[] = { + static const char * const thresholds[] = { "fanboost", "downclock", "critical", "shutdown" }; int temperature = therm->func->temp_get(therm); @@ -94,10 +94,10 @@ nvkm_therm_sensor_event(struct nvkm_therm *therm, enum nvkm_therm_thrs thrs, if (dir == NVKM_THERM_THRS_FALLING) nvkm_info(subdev, "temperature (%i C) went below the '%s' threshold\n", - temperature, thresolds[thrs]); + temperature, thresholds[thrs]); else nvkm_info(subdev, "temperature (%i C) hit the '%s' threshold\n", - temperature, thresolds[thrs]); + temperature, thresholds[thrs]); active = (dir == NVKM_THERM_THRS_RISING); switch (thrs) { diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index f0139fa58d55..b58c988d9da0 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -23,6 +23,7 @@ #include <drm/drmP.h> #include <drm/drm_panel.h> #include <drm/drm_gem_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_fb_cma_helper.h> #include "pl111_drm.h" @@ -274,7 +275,7 @@ void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc) static int pl111_display_prepare_fb(struct drm_simple_display_pipe *pipe, struct drm_plane_state *plane_state) { - return drm_fb_cma_prepare_fb(&pipe->plane, plane_state); + return drm_gem_fb_prepare_fb(&pipe->plane, plane_state); } static const struct drm_simple_display_pipe_funcs pl111_display_funcs = { diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl111_drv.c index 29653fe5285c..581c452cede1 100644 --- a/drivers/gpu/drm/pl111/pl111_drv.c +++ b/drivers/gpu/drm/pl111/pl111_drv.c @@ -66,14 +66,15 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_gem_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_fb_cma_helper.h> #include "pl111_drm.h" #define DRIVER_DESC "DRM module for PL111" -static struct drm_mode_config_funcs mode_config_funcs = { - .fb_create = drm_fb_cma_create, +static const struct drm_mode_config_funcs mode_config_funcs = { + .fb_create = drm_gem_fb_create, .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index 403e135895bf..2445e75cf7ea 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -263,7 +263,6 @@ static struct drm_driver qxl_driver = { .dumb_create = qxl_mode_dumb_create, .dumb_map_offset = qxl_mode_dumb_mmap, - .dumb_destroy = drm_gem_dumb_destroy, #if defined(CONFIG_DEBUG_FS) .debugfs_init = qxl_debugfs_init, #endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 5008f3d4cccc..ec63bc5e9de7 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -464,7 +464,7 @@ struct radeon_bo_list { struct radeon_bo *robj; struct ttm_validate_buffer tv; uint64_t gpu_offset; - unsigned prefered_domains; + unsigned preferred_domains; unsigned allowed_domains; uint32_t tiling_flags; }; @@ -2327,7 +2327,7 @@ struct radeon_device { uint8_t *bios; bool is_atom_bios; uint16_t bios_header_start; - struct radeon_bo *stollen_vga_memory; + struct radeon_bo *stolen_vga_memory; /* Register mmio */ resource_size_t rmmio_base; resource_size_t rmmio_size; diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c index 6efbd65c929e..8d3251a10cd4 100644 --- a/drivers/gpu/drm/radeon/radeon_acpi.c +++ b/drivers/gpu/drm/radeon/radeon_acpi.c @@ -351,7 +351,7 @@ out: * handles it. * Returns NOTIFY code */ -int radeon_atif_handler(struct radeon_device *rdev, +static int radeon_atif_handler(struct radeon_device *rdev, struct acpi_bus_event *event) { struct radeon_atif *atif = &rdev->atif; diff --git a/drivers/gpu/drm/radeon/radeon_acpi.h b/drivers/gpu/drm/radeon/radeon_acpi.h index 7af1977c2c68..35202a453e66 100644 --- a/drivers/gpu/drm/radeon/radeon_acpi.h +++ b/drivers/gpu/drm/radeon/radeon_acpi.h @@ -27,9 +27,6 @@ struct radeon_device; struct acpi_bus_event; -int radeon_atif_handler(struct radeon_device *rdev, - struct acpi_bus_event *event); - /* AMD hw uses four ACPI control methods: * 1. ATIF * ARG0: (ACPI_INTEGER) function code diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 00b22af70f5c..1ae31dbc61c6 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -130,7 +130,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) p->rdev->family == CHIP_RS880)) { /* TODO: is this still needed for NI+ ? */ - p->relocs[i].prefered_domains = + p->relocs[i].preferred_domains = RADEON_GEM_DOMAIN_VRAM; p->relocs[i].allowed_domains = @@ -148,14 +148,14 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) return -EINVAL; } - p->relocs[i].prefered_domains = domain; + p->relocs[i].preferred_domains = domain; if (domain == RADEON_GEM_DOMAIN_VRAM) domain |= RADEON_GEM_DOMAIN_GTT; p->relocs[i].allowed_domains = domain; } if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) { - uint32_t domain = p->relocs[i].prefered_domains; + uint32_t domain = p->relocs[i].preferred_domains; if (!(domain & RADEON_GEM_DOMAIN_GTT)) { DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is " "allowed for userptr BOs\n"); @@ -163,7 +163,7 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) } need_mmap_lock = true; domain = RADEON_GEM_DOMAIN_GTT; - p->relocs[i].prefered_domains = domain; + p->relocs[i].preferred_domains = domain; p->relocs[i].allowed_domains = domain; } @@ -437,7 +437,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bo if (bo == NULL) continue; - drm_gem_object_unreference_unlocked(&bo->gem_base); + drm_gem_object_put_unlocked(&bo->gem_base); } } kfree(parser->track); diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index 4a4f9533c53b..91952277557e 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c @@ -307,7 +307,7 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc, robj = gem_to_radeon_bo(obj); ret = radeon_bo_reserve(robj, false); if (ret != 0) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } /* Only 27 bit offset for legacy cursor */ @@ -317,7 +317,7 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc, radeon_bo_unreserve(robj); if (ret) { DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } @@ -352,7 +352,7 @@ unpin: radeon_bo_unpin(robj); radeon_bo_unreserve(robj); } - drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); + drm_gem_object_put_unlocked(radeon_crtc->cursor_bo); } radeon_crtc->cursor_bo = obj; diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index ee274c6e374d..ddfe91efa61e 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -267,7 +267,7 @@ static void radeon_unpin_work_func(struct work_struct *__work) } else DRM_ERROR("failed to reserve buffer after flip\n"); - drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); + drm_gem_object_put_unlocked(&work->old_rbo->gem_base); kfree(work); } @@ -504,7 +504,7 @@ static int radeon_crtc_page_flip_target(struct drm_crtc *crtc, obj = old_radeon_fb->obj; /* take a reference to the old object */ - drm_gem_object_reference(obj); + drm_gem_object_get(obj); work->old_rbo = gem_to_radeon_bo(obj); new_radeon_fb = to_radeon_framebuffer(fb); @@ -603,7 +603,7 @@ pflip_cleanup: radeon_bo_unreserve(new_rbo); cleanup: - drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base); + drm_gem_object_put_unlocked(&work->old_rbo->gem_base); dma_fence_put(work->fence); kfree(work); return r; @@ -1288,7 +1288,7 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); - drm_gem_object_unreference_unlocked(radeon_fb->obj); + drm_gem_object_put_unlocked(radeon_fb->obj); drm_framebuffer_cleanup(fb); kfree(radeon_fb); } @@ -1348,14 +1348,14 @@ radeon_user_framebuffer_create(struct drm_device *dev, radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); if (radeon_fb == NULL) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(-ENOMEM); } ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); if (ret) { kfree(radeon_fb); - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index af6ee7d9b465..fd25361ac681 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -118,7 +118,7 @@ static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) radeon_bo_unpin(rbo); radeon_bo_unreserve(rbo); } - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); } static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, @@ -299,7 +299,7 @@ out: } if (fb && ret) { - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); drm_framebuffer_unregister_private(fb); drm_framebuffer_cleanup(fb); kfree(fb); diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index 574bf7e6b118..3386452bd2f0 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -271,7 +271,7 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data, } r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (r) { up_read(&rdev->exclusive_lock); r = radeon_gem_handle_lockup(rdev, r); @@ -352,7 +352,7 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (r) goto handle_lockup; @@ -361,7 +361,7 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, return 0; release_object: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); handle_lockup: up_read(&rdev->exclusive_lock); @@ -395,7 +395,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); up_read(&rdev->exclusive_lock); r = radeon_gem_handle_lockup(robj->rdev, r); return r; @@ -414,11 +414,11 @@ int radeon_mode_dumb_mmap(struct drm_file *filp, } robj = gem_to_radeon_bo(gobj); if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) { - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return -EPERM; } *offset_p = radeon_bo_mmap_offset(robj); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return 0; } @@ -453,7 +453,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type); args->domain = radeon_mem_type_to_domain(cur_placement); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -485,7 +485,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, if (rdev->asic->mmio_hdp_flush && radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) robj->rdev->asic->mmio_hdp_flush(rdev); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); r = radeon_gem_handle_lockup(rdev, r); return r; } @@ -504,7 +504,7 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, return -ENOENT; robj = gem_to_radeon_bo(gobj); r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -527,7 +527,7 @@ int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); radeon_bo_unreserve(rbo); out: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -661,14 +661,14 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void *data, r = radeon_bo_reserve(rbo, false); if (r) { args->operation = RADEON_VA_RESULT_ERROR; - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } bo_va = radeon_vm_bo_find(&fpriv->vm, rbo); if (!bo_va) { args->operation = RADEON_VA_RESULT_ERROR; radeon_bo_unreserve(rbo); - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return -ENOENT; } @@ -695,7 +695,7 @@ int radeon_gem_va_ioctl(struct drm_device *dev, void *data, args->operation = RADEON_VA_RESULT_ERROR; } out: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -736,7 +736,7 @@ int radeon_gem_op_ioctl(struct drm_device *dev, void *data, radeon_bo_unreserve(robj); out: - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); return r; } @@ -762,7 +762,7 @@ int radeon_mode_dumb_create(struct drm_file *file_priv, r = drm_gem_handle_create(file_priv, gobj, &handle); /* drop reference from allocate - handle holds it now */ - drm_gem_object_unreference_unlocked(gobj); + drm_gem_object_put_unlocked(gobj); if (r) { return r; } diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index a2ab6dcdf4a2..f6578c96925c 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -75,12 +75,14 @@ static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr); static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr); + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm); static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd); static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id); -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id); static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); @@ -482,7 +484,9 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) } static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, - uint32_t queue_id, uint32_t __user *wptr) + uint32_t queue_id, uint32_t __user *wptr, + uint32_t wptr_shift, uint32_t wptr_mask, + struct mm_struct *mm) { uint32_t wptr_shadow, is_wptr_shadow_valid; struct cik_mqd *m; @@ -636,7 +640,7 @@ static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) return false; } -static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type, +static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id) { @@ -785,7 +789,8 @@ static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, unsigned int watch_point_id, unsigned int reg_offset) { - return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; + return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset] + / 4; } static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 8b722297a05c..093594976126 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -445,7 +445,7 @@ void radeon_bo_force_delete(struct radeon_device *rdev) list_del_init(&bo->list); mutex_unlock(&bo->rdev->gem.mutex); /* this should unref the ttm bo */ - drm_gem_object_unreference_unlocked(&bo->gem_base); + drm_gem_object_put_unlocked(&bo->gem_base); } } @@ -546,7 +546,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, list_for_each_entry(lobj, head, tv.head) { struct radeon_bo *bo = lobj->robj; if (!bo->pin_count) { - u32 domain = lobj->prefered_domains; + u32 domain = lobj->preferred_domains; u32 allowed = lobj->allowed_domains; u32 current_domain = radeon_mem_type_to_domain(bo->tbo.mem.mem_type); diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 2804b4a15896..bf69bf9086bf 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -907,17 +907,17 @@ int radeon_ttm_init(struct radeon_device *rdev) r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 0, NULL, - NULL, &rdev->stollen_vga_memory); + NULL, &rdev->stolen_vga_memory); if (r) { return r; } - r = radeon_bo_reserve(rdev->stollen_vga_memory, false); + r = radeon_bo_reserve(rdev->stolen_vga_memory, false); if (r) return r; - r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); - radeon_bo_unreserve(rdev->stollen_vga_memory); + r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); + radeon_bo_unreserve(rdev->stolen_vga_memory); if (r) { - radeon_bo_unref(&rdev->stollen_vga_memory); + radeon_bo_unref(&rdev->stolen_vga_memory); return r; } DRM_INFO("radeon: %uM of VRAM memory ready\n", @@ -946,13 +946,13 @@ void radeon_ttm_fini(struct radeon_device *rdev) if (!rdev->mman.initialized) return; radeon_ttm_debugfs_fini(rdev); - if (rdev->stollen_vga_memory) { - r = radeon_bo_reserve(rdev->stollen_vga_memory, false); + if (rdev->stolen_vga_memory) { + r = radeon_bo_reserve(rdev->stolen_vga_memory, false); if (r == 0) { - radeon_bo_unpin(rdev->stollen_vga_memory); - radeon_bo_unreserve(rdev->stollen_vga_memory); + radeon_bo_unpin(rdev->stolen_vga_memory); + radeon_bo_unreserve(rdev->stolen_vga_memory); } - radeon_bo_unref(&rdev->stollen_vga_memory); + radeon_bo_unref(&rdev->stolen_vga_memory); } ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); @@ -1030,19 +1030,17 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma) static int radeon_mm_dump_table(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; - unsigned ttm_pl = *(int *)node->info_ent->data; + unsigned ttm_pl = *(int*)node->info_ent->data; struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; - struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; - struct ttm_bo_global *glob = rdev->mman.bdev.glob; + struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl]; struct drm_printer p = drm_seq_file_printer(m); - spin_lock(&glob->lru_lock); - drm_mm_print(mm, &p); - spin_unlock(&glob->lru_lock); + man->func->debug(man, &p); return 0; } + static int ttm_pl_vram = TTM_PL_VRAM; static int ttm_pl_tt = TTM_PL_TT; diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index 5f68245579a3..5e82b408d522 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c @@ -139,7 +139,7 @@ struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, /* add the vm page table to the list */ list[0].robj = vm->page_directory; - list[0].prefered_domains = RADEON_GEM_DOMAIN_VRAM; + list[0].preferred_domains = RADEON_GEM_DOMAIN_VRAM; list[0].allowed_domains = RADEON_GEM_DOMAIN_VRAM; list[0].tv.bo = &vm->page_directory->tbo; list[0].tv.shared = true; @@ -151,7 +151,7 @@ struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, continue; list[idx].robj = vm->page_tables[i].bo; - list[idx].prefered_domains = RADEON_GEM_DOMAIN_VRAM; + list[idx].preferred_domains = RADEON_GEM_DOMAIN_VRAM; list[idx].allowed_domains = RADEON_GEM_DOMAIN_VRAM; list[idx].tv.bo = &list[idx].robj->tbo; list[idx].tv.shared = true; diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index bd87768dd549..7a251a54e792 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -592,7 +592,7 @@ static void inno_hdmi_connector_destroy(struct drm_connector *connector) drm_connector_cleanup(connector); } -static struct drm_connector_funcs inno_hdmi_connector_funcs = { +static const struct drm_connector_funcs inno_hdmi_connector_funcs = { .fill_modes = inno_hdmi_probe_single_connector_modes, .detect = inno_hdmi_connector_detect, .destroy = inno_hdmi_connector_destroy, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 8a0f75612d4b..70773041785b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -48,7 +48,7 @@ static void rockchip_drm_fb_destroy(struct drm_framebuffer *fb) int i; for (i = 0; i < ROCKCHIP_MAX_FB_BUFFER; i++) - drm_gem_object_unreference_unlocked(rockchip_fb->obj[i]); + drm_gem_object_put_unlocked(rockchip_fb->obj[i]); drm_framebuffer_cleanup(fb); kfree(rockchip_fb); @@ -144,7 +144,7 @@ rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, width * drm_format_plane_cpp(mode_cmd->pixel_format, i); if (obj->size < min_size) { - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); ret = -EINVAL; goto err_gem_object_unreference; } @@ -161,7 +161,7 @@ rockchip_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, err_gem_object_unreference: for (i--; i >= 0; i--) - drm_gem_object_unreference_unlocked(objs[i]); + drm_gem_object_put_unlocked(objs[i]); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c index ce946b9c57a9..724579ebf947 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c @@ -173,7 +173,7 @@ void rockchip_drm_fbdev_fini(struct drm_device *dev) drm_fb_helper_unregister_fbi(helper); if (helper->fb) - drm_framebuffer_unreference(helper->fb); + drm_framebuffer_put(helper->fb); drm_fb_helper_fini(helper); } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index f74333efe4bb..1869c8bb76c8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -383,7 +383,7 @@ rockchip_gem_create_with_handle(struct drm_file *file_priv, goto err_handle_create; /* drop reference from allocate - handle holds it now. */ - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return rk_obj; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 948719dddc36..bf9ed0e63973 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1026,7 +1026,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, if (old_plane_state->fb == new_plane_state->fb) continue; - drm_framebuffer_reference(old_plane_state->fb); + drm_framebuffer_get(old_plane_state->fb); drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb); set_bit(VOP_PENDING_FB_UNREF, &vop->pending); WARN_ON(drm_crtc_vblank_get(crtc) != 0); @@ -1150,7 +1150,7 @@ static void vop_fb_unref_worker(struct drm_flip_work *work, void *val) struct drm_framebuffer *fb = val; drm_crtc_vblank_put(&vop->crtc); - drm_framebuffer_unreference(fb); + drm_framebuffer_put(fb); } static void vop_handle_vblank(struct vop *vop) diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index 5bcad8f5fb4f..06f05302ee75 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -13,17 +13,26 @@ config DRM_SUN4I Display Engine. If M is selected the module will be called sun4i-drm. +if DRM_SUN4I + config DRM_SUN4I_HDMI tristate "Allwinner A10 HDMI Controller Support" - depends on DRM_SUN4I default DRM_SUN4I help Choose this option if you have an Allwinner SoC with an HDMI controller. +config DRM_SUN4I_HDMI_CEC + bool "Allwinner A10 HDMI CEC Support" + depends on DRM_SUN4I_HDMI + select CEC_CORE + depends on CEC_PIN + help + Choose this option if you have an Allwinner SoC with an HDMI + controller and want to use CEC. + config DRM_SUN4I_BACKEND tristate "Support for Allwinner A10 Display Engine Backend" - depends on DRM_SUN4I default DRM_SUN4I help Choose this option if you have an Allwinner SoC with the @@ -33,10 +42,11 @@ config DRM_SUN4I_BACKEND config DRM_SUN8I_MIXER tristate "Support for Allwinner Display Engine 2.0 Mixer" - depends on DRM_SUN4I default MACH_SUN8I help Choose this option if you have an Allwinner SoC with the Allwinner Display Engine 2.0, which has a mixer to do some graphics mixture and feed graphics to TCON, If M is selected the module will be called sun8i-mixer. + +endif diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index e29fd3a2ba9c..43c753cafc88 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -2,6 +2,7 @@ sun4i-drm-y += sun4i_drv.o sun4i-drm-y += sun4i_framebuffer.o sun4i-drm-hdmi-y += sun4i_hdmi_enc.o +sun4i-drm-hdmi-y += sun4i_hdmi_i2c.o sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h index 2f2f2ff1ea63..1457750988da 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h @@ -15,6 +15,8 @@ #include <drm/drm_connector.h> #include <drm/drm_encoder.h> +#include <media/cec.h> + #define SUN4I_HDMI_CTRL_REG 0x004 #define SUN4I_HDMI_CTRL_ENABLE BIT(31) @@ -86,6 +88,11 @@ #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 +#define SUN4I_HDMI_CEC 0x214 +#define SUN4I_HDMI_CEC_ENABLE BIT(11) +#define SUN4I_HDMI_CEC_TX BIT(9) +#define SUN4I_HDMI_CEC_RX BIT(8) + #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) #define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) @@ -96,6 +103,7 @@ #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) +#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8) #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8) #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) @@ -105,14 +113,34 @@ #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff) +#define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c +#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) +#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) +#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) +#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) +#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) +#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) +#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) +#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) + #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510 #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) +#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4) +#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4) +#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1) +#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf) +#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0) +#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1) #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 + #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c +#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1) #define SUN4I_HDMI_DDC_CMD_REG 0x520 #define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 +#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5 +#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3 #define SUN4I_HDMI_DDC_CLK_REG 0x528 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3) @@ -146,12 +174,16 @@ struct sun4i_hdmi { struct clk *ddc_clk; struct clk *tmds_clk; + struct i2c_adapter *i2c; + struct sun4i_drv *drv; bool hdmi_monitor; + struct cec_adapter *cec_adap; }; int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); int sun4i_tmds_create(struct sun4i_hdmi *hdmi); +int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi); #endif /* _SUN4I_HDMI_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index f5d0d6bd1084..9ea6cd5a1370 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -29,8 +29,6 @@ #include "sun4i_hdmi.h" #include "sun4i_tcon.h" -#define DDC_SEGMENT_ADDR 0x30 - static inline struct sun4i_hdmi * drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) { @@ -184,93 +182,13 @@ static const struct drm_encoder_funcs sun4i_hdmi_funcs = { .destroy = drm_encoder_cleanup, }; -static int sun4i_hdmi_read_sub_block(struct sun4i_hdmi *hdmi, - unsigned int blk, unsigned int offset, - u8 *buf, unsigned int count) -{ - unsigned long reg; - int i; - - reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK; - writel(reg | SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ, - hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - - writel(SUN4I_HDMI_DDC_ADDR_SEGMENT(offset >> 8) | - SUN4I_HDMI_DDC_ADDR_EDDC(DDC_SEGMENT_ADDR << 1) | - SUN4I_HDMI_DDC_ADDR_OFFSET(offset) | - SUN4I_HDMI_DDC_ADDR_SLAVE(DDC_ADDR), - hdmi->base + SUN4I_HDMI_DDC_ADDR_REG); - - reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); - writel(reg | SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR, - hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); - - writel(count, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG); - writel(SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ, - hdmi->base + SUN4I_HDMI_DDC_CMD_REG); - - reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD, - hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - - if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg, - !(reg & SUN4I_HDMI_DDC_CTRL_START_CMD), - 100, 100000)) - return -EIO; - - for (i = 0; i < count; i++) - buf[i] = readb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG); - - return 0; -} - -static int sun4i_hdmi_read_edid_block(void *data, u8 *buf, unsigned int blk, - size_t length) -{ - struct sun4i_hdmi *hdmi = data; - int retry = 2, i; - - do { - for (i = 0; i < length; i += SUN4I_HDMI_DDC_FIFO_SIZE) { - unsigned char offset = blk * EDID_LENGTH + i; - unsigned int count = min((unsigned int)SUN4I_HDMI_DDC_FIFO_SIZE, - length - i); - int ret; - - ret = sun4i_hdmi_read_sub_block(hdmi, blk, offset, - buf + i, count); - if (ret) - return ret; - } - } while (!drm_edid_block_valid(buf, blk, true, NULL) && (retry--)); - - return 0; -} - static int sun4i_hdmi_get_modes(struct drm_connector *connector) { struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); - unsigned long reg; struct edid *edid; int ret; - /* Reset i2c controller */ - writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET, - hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); - if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg, - !(reg & SUN4I_HDMI_DDC_CTRL_RESET), - 100, 2000)) - return -EIO; - - writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE | - SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE, - hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG); - - clk_prepare_enable(hdmi->ddc_clk); - clk_set_rate(hdmi->ddc_clk, 100000); - - edid = drm_do_get_edid(connector, sun4i_hdmi_read_edid_block, hdmi); + edid = drm_get_edid(connector, hdmi->i2c); if (!edid) return 0; @@ -279,11 +197,10 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector) hdmi->hdmi_monitor ? "an HDMI" : "a DVI"); drm_mode_connector_update_edid_property(connector, edid); + cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); ret = drm_add_edid_modes(connector, edid); kfree(edid); - clk_disable_unprepare(hdmi->ddc_clk); - return ret; } @@ -299,8 +216,10 @@ sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, reg & SUN4I_HDMI_HPD_HIGH, - 0, 500000)) + 0, 500000)) { + cec_phys_addr_invalidate(hdmi->cec_adap); return connector_status_disconnected; + } return connector_status_connected; } @@ -314,6 +233,40 @@ static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; +#ifdef CONFIG_DRM_SUN4I_HDMI_CEC +static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) +{ + struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); + + return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; +} + +static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) +{ + struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); + + /* Start driving the CEC pin low */ + writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); +} + +static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) +{ + struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); + + /* + * Stop driving the CEC pin, the pull up will take over + * unless another CEC device is driving the pin low. + */ + writel(0, hdmi->base + SUN4I_HDMI_CEC); +} + +static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { + .read = sun4i_hdmi_cec_pin_read, + .low = sun4i_hdmi_cec_pin_low, + .high = sun4i_hdmi_cec_pin_high, +}; +#endif + static int sun4i_hdmi_bind(struct device *dev, struct device *master, void *data) { @@ -406,9 +359,9 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master, SUN4I_HDMI_PLL_CTRL_PLL_EN; writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); - ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk); + ret = sun4i_hdmi_i2c_create(dev, hdmi); if (ret) { - dev_err(dev, "Couldn't create the DDC clock\n"); + dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); return ret; } @@ -421,13 +374,26 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master, NULL); if (ret) { dev_err(dev, "Couldn't initialise the HDMI encoder\n"); - return ret; + goto err_del_i2c_adapter; } hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - if (!hdmi->encoder.possible_crtcs) - return -EPROBE_DEFER; + if (!hdmi->encoder.possible_crtcs) { + ret = -EPROBE_DEFER; + goto err_del_i2c_adapter; + } + +#ifdef CONFIG_DRM_SUN4I_HDMI_CEC + hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, + hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS | + CEC_CAP_PASSTHROUGH | CEC_CAP_RC); + ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); + if (ret < 0) + goto err_cleanup_connector; + writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, + hdmi->base + SUN4I_HDMI_CEC); +#endif drm_connector_helper_add(&hdmi->connector, &sun4i_hdmi_connector_helper_funcs); @@ -444,12 +410,18 @@ static int sun4i_hdmi_bind(struct device *dev, struct device *master, hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; + ret = cec_register_adapter(hdmi->cec_adap, dev); + if (ret < 0) + goto err_cleanup_connector; drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); return 0; err_cleanup_connector: + cec_delete_adapter(hdmi->cec_adap); drm_encoder_cleanup(&hdmi->encoder); +err_del_i2c_adapter: + i2c_del_adapter(hdmi->i2c); return ret; } @@ -458,8 +430,10 @@ static void sun4i_hdmi_unbind(struct device *dev, struct device *master, { struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); + cec_unregister_adapter(hdmi->cec_adap); drm_connector_cleanup(&hdmi->connector); drm_encoder_cleanup(&hdmi->encoder); + i2c_del_adapter(hdmi->i2c); } static const struct component_ops sun4i_hdmi_ops = { diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c new file mode 100644 index 000000000000..2e42d09ab42e --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> + * Copyright (C) 2017 Jonathan Liu <net147@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <linux/clk.h> +#include <linux/i2c.h> +#include <linux/iopoll.h> + +#include "sun4i_hdmi.h" + +#define SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ( \ + SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW | \ + SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR | \ + SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR \ +) + +/* FIFO request bit is set when FIFO level is above RX_THRESHOLD during read */ +#define RX_THRESHOLD SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX +/* FIFO request bit is set when FIFO level is below TX_THRESHOLD during write */ +#define TX_THRESHOLD 1 + +static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) +{ + /* + * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz + * clock. As clock rate is fixed, just round it up to 100 us. + */ + const unsigned long byte_time_ns = 100; + const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | + SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST | + SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE; + u32 reg; + + /* Limit transfer length by FIFO threshold */ + len = min_t(int, len, read ? (RX_THRESHOLD + 1) : + (SUN4I_HDMI_DDC_FIFO_SIZE - TX_THRESHOLD + 1)); + + /* Wait until error, FIFO request bit set or transfer complete */ + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG, reg, + reg & mask, len * byte_time_ns, 100000)) + return -ETIMEDOUT; + + if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) + return -EIO; + + if (read) + readsb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len); + else + writesb(hdmi->base + SUN4I_HDMI_DDC_FIFO_DATA_REG, buf, len); + + /* Clear FIFO request bit */ + writel(SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST, + hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG); + + return len; +} + +static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg) +{ + int i, len; + u32 reg; + + /* Set FIFO direction */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK; + reg |= (msg->flags & I2C_M_RD) ? + SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ : + SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE; + writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + + /* Set I2C address */ + writel(SUN4I_HDMI_DDC_ADDR_SLAVE(msg->addr), + hdmi->base + SUN4I_HDMI_DDC_ADDR_REG); + + /* Set FIFO RX/TX thresholds and clear FIFO */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); + reg |= SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR; + reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK; + reg |= SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(RX_THRESHOLD); + reg &= ~SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK; + reg |= SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(TX_THRESHOLD); + writel(reg, hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG); + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_FIFO_CTRL_REG, + reg, + !(reg & SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR), + 100, 2000)) + return -EIO; + + /* Set transfer length */ + writel(msg->len, hdmi->base + SUN4I_HDMI_DDC_BYTE_COUNT_REG); + + /* Set command */ + writel(msg->flags & I2C_M_RD ? + SUN4I_HDMI_DDC_CMD_IMPLICIT_READ : + SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE, + hdmi->base + SUN4I_HDMI_DDC_CMD_REG); + + /* Clear interrupt status bits */ + writel(SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | + SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST | + SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE, + hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG); + + /* Start command */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + writel(reg | SUN4I_HDMI_DDC_CTRL_START_CMD, + hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + + /* Transfer bytes */ + for (i = 0; i < msg->len; i += len) { + len = fifo_transfer(hdmi, msg->buf + i, msg->len - i, + msg->flags & I2C_M_RD); + if (len <= 0) + return len; + } + + /* Wait for command to finish */ + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, + reg, + !(reg & SUN4I_HDMI_DDC_CTRL_START_CMD), + 100, 100000)) + return -EIO; + + /* Check for errors */ + reg = readl(hdmi->base + SUN4I_HDMI_DDC_INT_STATUS_REG); + if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) || + !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) { + return -EIO; + } + + return 0; +} + +static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct sun4i_hdmi *hdmi = i2c_get_adapdata(adap); + u32 reg; + int err, i, ret = num; + + for (i = 0; i < num; i++) { + if (!msgs[i].len) + return -EINVAL; + if (msgs[i].len > SUN4I_HDMI_DDC_BYTE_COUNT_MAX) + return -EINVAL; + } + + /* Reset I2C controller */ + writel(SUN4I_HDMI_DDC_CTRL_ENABLE | SUN4I_HDMI_DDC_CTRL_RESET, + hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); + if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG, reg, + !(reg & SUN4I_HDMI_DDC_CTRL_RESET), + 100, 2000)) + return -EIO; + + writel(SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE | + SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE, + hdmi->base + SUN4I_HDMI_DDC_LINE_CTRL_REG); + + clk_prepare_enable(hdmi->ddc_clk); + clk_set_rate(hdmi->ddc_clk, 100000); + + for (i = 0; i < num; i++) { + err = xfer_msg(hdmi, &msgs[i]); + if (err) { + ret = err; + break; + } + } + + clk_disable_unprepare(hdmi->ddc_clk); + return ret; +} + +static u32 sun4i_hdmi_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm sun4i_hdmi_i2c_algorithm = { + .master_xfer = sun4i_hdmi_i2c_xfer, + .functionality = sun4i_hdmi_i2c_func, +}; + +int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi) +{ + struct i2c_adapter *adap; + int ret = 0; + + ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk); + if (ret) + return ret; + + adap = devm_kzalloc(dev, sizeof(*adap), GFP_KERNEL); + if (!adap) + return -ENOMEM; + + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_DDC; + adap->algo = &sun4i_hdmi_i2c_algorithm; + strlcpy(adap->name, "sun4i_hdmi_i2c adapter", sizeof(adap->name)); + i2c_set_adapdata(adap, hdmi); + + ret = i2c_add_adapter(adap); + if (ret) + return ret; + + hdmi->i2c = adap; + + return ret; +} diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c index d45f3a1a0a29..7bddf12548d3 100644 --- a/drivers/gpu/drm/sun4i/sun4i_layer.c +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c @@ -25,12 +25,6 @@ struct sun4i_plane_desc { uint32_t nformats; }; -static int sun4i_backend_layer_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) -{ - return 0; -} - static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { @@ -52,8 +46,7 @@ static void sun4i_backend_layer_atomic_update(struct drm_plane *plane, sun4i_backend_layer_enable(backend, layer->id, true); } -static struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = { - .atomic_check = sun4i_backend_layer_atomic_check, +static const struct drm_plane_helper_funcs sun4i_backend_layer_helper_funcs = { .atomic_disable = sun4i_backend_layer_atomic_disable, .atomic_update = sun4i_backend_layer_atomic_update, }; diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c index 550bb262943f..7cd7090ad63a 100644 --- a/drivers/gpu/drm/sun4i/sun4i_rgb.c +++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c @@ -119,7 +119,7 @@ sun4i_rgb_connector_destroy(struct drm_connector *connector) drm_connector_cleanup(connector); } -static struct drm_connector_funcs sun4i_rgb_con_funcs = { +static const struct drm_connector_funcs sun4i_rgb_con_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = sun4i_rgb_connector_destroy, .reset = drm_atomic_helper_connector_reset, @@ -127,13 +127,6 @@ static struct drm_connector_funcs sun4i_rgb_con_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; -static int sun4i_rgb_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - return 0; -} - static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder) { struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder); @@ -181,7 +174,6 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder *encoder, } static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = { - .atomic_check = sun4i_rgb_atomic_check, .mode_set = sun4i_rgb_encoder_mode_set, .disable = sun4i_rgb_encoder_disable, .enable = sun4i_rgb_encoder_enable, diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index e3c50ecdcd04..552c88ec16be 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -194,8 +194,6 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel); void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable); /* Mode Related Controls */ -void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon, - bool enable); void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, struct drm_encoder *encoder); void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c index 7b45ac9383ea..050cfd43c7a0 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tv.c +++ b/drivers/gpu/drm/sun4i/sun4i_tv.c @@ -341,13 +341,6 @@ static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode, mode->vtotal = mode->vsync_end + tv_mode->vback_porch; } -static int sun4i_tv_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - return 0; -} - static void sun4i_tv_disable(struct drm_encoder *encoder) { struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder); @@ -489,7 +482,6 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder, } static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = { - .atomic_check = sun4i_tv_atomic_check, .disable = sun4i_tv_disable, .enable = sun4i_tv_enable, .mode_set = sun4i_tv_mode_set, @@ -545,7 +537,7 @@ sun4i_tv_comp_connector_destroy(struct drm_connector *connector) drm_connector_cleanup(connector); } -static struct drm_connector_funcs sun4i_tv_comp_connector_funcs = { +static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = sun4i_tv_comp_connector_destroy, .reset = drm_atomic_helper_connector_reset, diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig index 2db29d67193d..dc58ab140151 100644 --- a/drivers/gpu/drm/tegra/Kconfig +++ b/drivers/gpu/drm/tegra/Kconfig @@ -3,6 +3,7 @@ config DRM_TEGRA depends on ARCH_TEGRA || (ARM && COMPILE_TEST) depends on COMMON_CLK depends on DRM + depends on OF select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 6af3a9ad6565..8927784396e8 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -17,4 +17,6 @@ tegra-drm-y := \ falcon.o \ vic.o +tegra-drm-y += trace.o + obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 2fde44c3a1b3..e4da041ba89b 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -25,6 +25,7 @@ #include "dpaux.h" #include "drm.h" +#include "trace.h" static DEFINE_MUTEX(dpaux_lock); static LIST_HEAD(dpaux_list); @@ -65,14 +66,19 @@ static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work) } static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, - unsigned long offset) + unsigned int offset) { - return readl(dpaux->regs + (offset << 2)); + u32 value = readl(dpaux->regs + (offset << 2)); + + trace_dpaux_readl(dpaux->dev, offset, value); + + return value; } static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, - u32 value, unsigned long offset) + u32 value, unsigned int offset) { + trace_dpaux_writel(dpaux->dev, offset, value); writel(value, dpaux->regs + (offset << 2)); } diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 3ba659a5940d..597d563d636a 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -306,8 +306,6 @@ host1x_bo_lookup(struct drm_file *file, u32 handle) if (!gem) return NULL; - drm_gem_object_unreference_unlocked(gem); - bo = to_tegra_bo(gem); return &bo->base; } @@ -396,8 +394,10 @@ int tegra_drm_submit(struct tegra_drm_context *context, (void __user *)(uintptr_t)args->waitchks; struct drm_tegra_syncpt syncpt; struct host1x *host1x = dev_get_drvdata(drm->dev->parent); + struct drm_gem_object **refs; struct host1x_syncpt *sp; struct host1x_job *job; + unsigned int num_refs; int err; /* We don't yet support other than one syncpt_incr struct per submit */ @@ -419,6 +419,21 @@ int tegra_drm_submit(struct tegra_drm_context *context, job->class = context->client->base.class; job->serialize = true; + /* + * Track referenced BOs so that they can be unreferenced after the + * submission is complete. + */ + num_refs = num_cmdbufs + num_relocs * 2 + num_waitchks; + + refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); + if (!refs) { + err = -ENOMEM; + goto put; + } + + /* reuse as an iterator later */ + num_refs = 0; + while (num_cmdbufs) { struct drm_tegra_cmdbuf cmdbuf; struct host1x_bo *bo; @@ -447,6 +462,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); obj = host1x_to_tegra_bo(bo); + refs[num_refs++] = &obj->gem; /* * Gather buffer base address must be 4-bytes aligned, @@ -476,6 +492,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, reloc = &job->relocarray[num_relocs]; obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); + refs[num_refs++] = &obj->gem; /* * The unaligned cmdbuf offset will cause an unaligned write @@ -489,6 +506,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, } obj = host1x_to_tegra_bo(reloc->target.bo); + refs[num_refs++] = &obj->gem; if (reloc->target.offset >= obj->gem.size) { err = -EINVAL; @@ -508,6 +526,7 @@ int tegra_drm_submit(struct tegra_drm_context *context, goto fail; obj = host1x_to_tegra_bo(wait->bo); + refs[num_refs++] = &obj->gem; /* * The unaligned offset will cause an unaligned write during @@ -547,17 +566,20 @@ int tegra_drm_submit(struct tegra_drm_context *context, goto fail; err = host1x_job_submit(job); - if (err) - goto fail_submit; + if (err) { + host1x_job_unpin(job); + goto fail; + } args->fence = job->syncpt_end; - host1x_job_put(job); - return 0; - -fail_submit: - host1x_job_unpin(job); fail: + while (num_refs--) + drm_gem_object_put_unlocked(refs[num_refs]); + + kfree(refs); + +put: host1x_job_put(job); return err; } @@ -593,7 +615,7 @@ static int tegra_gem_mmap(struct drm_device *drm, void *data, args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -860,7 +882,7 @@ static int tegra_gem_set_tiling(struct drm_device *drm, void *data, bo->tiling.mode = mode; bo->tiling.value = value; - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -900,7 +922,7 @@ static int tegra_gem_get_tiling(struct drm_device *drm, void *data, break; } - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return err; } @@ -925,7 +947,7 @@ static int tegra_gem_set_flags(struct drm_device *drm, void *data, if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) bo->flags |= TEGRA_BO_BOTTOM_UP; - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -947,7 +969,7 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data, if (bo->flags & TEGRA_BO_BOTTOM_UP) args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; - drm_gem_object_unreference_unlocked(gem); + drm_gem_object_put_unlocked(gem); return 0; } @@ -955,20 +977,34 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data, static const struct drm_ioctl_desc tegra_drm_ioctls[] = { #ifdef CONFIG_DRM_TEGRA_STAGING - DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), - DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), - DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), - DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, + DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, + DRM_UNLOCKED | DRM_RENDER_ALLOW), #endif }; @@ -1035,9 +1071,11 @@ static int tegra_debugfs_iova(struct seq_file *s, void *data) struct tegra_drm *tegra = drm->dev_private; struct drm_printer p = drm_seq_file_printer(s); - mutex_lock(&tegra->mm_lock); - drm_mm_print(&tegra->mm, &p); - mutex_unlock(&tegra->mm_lock); + if (tegra->domain) { + mutex_lock(&tegra->mm_lock); + drm_mm_print(&tegra->mm, &p); + mutex_unlock(&tegra->mm_lock); + } return 0; } @@ -1057,7 +1095,7 @@ static int tegra_debugfs_init(struct drm_minor *minor) static struct drm_driver tegra_drm_driver = { .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | - DRIVER_ATOMIC, + DRIVER_ATOMIC | DRIVER_RENDER, .load = tegra_drm_load, .unload = tegra_drm_unload, .open = tegra_drm_open, @@ -1077,8 +1115,6 @@ static struct drm_driver tegra_drm_driver = { .gem_prime_import = tegra_gem_prime_import, .dumb_create = tegra_bo_dumb_create, - .dumb_map_offset = tegra_bo_dumb_map_offset, - .dumb_destroy = drm_gem_dumb_destroy, .ioctls = tegra_drm_ioctls, .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 6d6da01282f3..063f5d397526 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -23,6 +23,7 @@ #include <drm/drm_fixed.h> #include "gem.h" +#include "trace.h" struct reset_control; @@ -172,14 +173,19 @@ static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) } static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, - unsigned long offset) + unsigned int offset) { + trace_dc_writel(dc->dev, offset, value); writel(value, dc->regs + (offset << 2)); } -static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned long offset) +static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) { - return readl(dc->regs + (offset << 2)); + u32 value = readl(dc->regs + (offset << 2)); + + trace_dc_readl(dc->dev, offset, value); + + return value; } struct tegra_dc_window { diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c index e4b5aedfdbd4..046649ec9441 100644 --- a/drivers/gpu/drm/tegra/dsi.c +++ b/drivers/gpu/drm/tegra/dsi.c @@ -28,6 +28,7 @@ #include "drm.h" #include "dsi.h" #include "mipi-phy.h" +#include "trace.h" struct tegra_dsi_state { struct drm_connector_state base; @@ -105,15 +106,20 @@ static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) return to_dsi_state(dsi->output.connector.state); } -static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg) +static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) { - return readl(dsi->regs + (reg << 2)); + u32 value = readl(dsi->regs + (offset << 2)); + + trace_dsi_readl(dsi->dev, offset, value); + + return value; } static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, - unsigned long reg) + unsigned int offset) { - writel(value, dsi->regs + (reg << 2)); + trace_dsi_writel(dsi->dev, offset, value); + writel(value, dsi->regs + (offset << 2)); } static int tegra_dsi_show_regs(struct seq_file *s, void *data) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 25acb73ee728..80540c1c66dc 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -88,7 +88,7 @@ static void tegra_fb_destroy(struct drm_framebuffer *framebuffer) if (bo->pages) vunmap(bo->vaddr); - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); } } @@ -195,7 +195,7 @@ struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, unreference: while (i--) - drm_gem_object_unreference_unlocked(&planes[i]->gem); + drm_gem_object_put_unlocked(&planes[i]->gem); return ERR_PTR(err); } @@ -242,7 +242,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper, info = drm_fb_helper_alloc_fbi(helper); if (IS_ERR(info)) { dev_err(drm->dev, "failed to allocate framebuffer info\n"); - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); return PTR_ERR(info); } @@ -251,7 +251,7 @@ static int tegra_fbdev_probe(struct drm_fb_helper *helper, err = PTR_ERR(fbdev->fb); dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n", err); - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); return PTR_ERR(fbdev->fb); } diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c index 7a39a355678a..ab1e53d434e8 100644 --- a/drivers/gpu/drm/tegra/gem.c +++ b/drivers/gpu/drm/tegra/gem.c @@ -24,7 +24,7 @@ static void tegra_bo_put(struct host1x_bo *bo) { struct tegra_bo *obj = host1x_to_tegra_bo(bo); - drm_gem_object_unreference_unlocked(&obj->gem); + drm_gem_object_put_unlocked(&obj->gem); } static dma_addr_t tegra_bo_pin(struct host1x_bo *bo, struct sg_table **sgt) @@ -95,7 +95,7 @@ static struct host1x_bo *tegra_bo_get(struct host1x_bo *bo) { struct tegra_bo *obj = host1x_to_tegra_bo(bo); - drm_gem_object_reference(&obj->gem); + drm_gem_object_get(&obj->gem); return bo; } @@ -325,7 +325,7 @@ struct tegra_bo *tegra_bo_create_with_handle(struct drm_file *file, return ERR_PTR(err); } - drm_gem_object_unreference_unlocked(&bo->gem); + drm_gem_object_put_unlocked(&bo->gem); return bo; } @@ -423,27 +423,6 @@ int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm, return 0; } -int tegra_bo_dumb_map_offset(struct drm_file *file, struct drm_device *drm, - u32 handle, u64 *offset) -{ - struct drm_gem_object *gem; - struct tegra_bo *bo; - - gem = drm_gem_object_lookup(file, handle); - if (!gem) { - dev_err(drm->dev, "failed to lookup GEM object\n"); - return -EINVAL; - } - - bo = to_tegra_bo(gem); - - *offset = drm_vma_node_offset_addr(&bo->gem.vma_node); - - drm_gem_object_unreference_unlocked(gem); - - return 0; -} - static int tegra_bo_fault(struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; @@ -481,30 +460,28 @@ const struct vm_operations_struct tegra_bo_vm_ops = { .close = drm_gem_vm_close, }; -int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) +static int tegra_gem_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { - struct drm_gem_object *gem; - struct tegra_bo *bo; - int ret; - - ret = drm_gem_mmap(file, vma); - if (ret) - return ret; - - gem = vma->vm_private_data; - bo = to_tegra_bo(gem); + struct tegra_bo *bo = to_tegra_bo(gem); if (!bo->pages) { unsigned long vm_pgoff = vma->vm_pgoff; + int err; + /* + * Clear the VM_PFNMAP flag that was set by drm_gem_mmap(), + * and set the vm_pgoff (used as a fake buffer offset by DRM) + * to 0 as we want to map the whole buffer. + */ vma->vm_flags &= ~VM_PFNMAP; vma->vm_pgoff = 0; - ret = dma_mmap_wc(gem->dev->dev, vma, bo->vaddr, bo->paddr, + err = dma_mmap_wc(gem->dev->dev, vma, bo->vaddr, bo->paddr, gem->size); - if (ret) { + if (err < 0) { drm_gem_vm_close(vma); - return ret; + return err; } vma->vm_pgoff = vm_pgoff; @@ -520,6 +497,20 @@ int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) return 0; } +int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct drm_gem_object *gem; + int err; + + err = drm_gem_mmap(file, vma); + if (err < 0) + return err; + + gem = vma->vm_private_data; + + return tegra_gem_mmap(gem, vma); +} + static struct sg_table * tegra_gem_prime_map_dma_buf(struct dma_buf_attachment *attach, enum dma_data_direction dir) @@ -603,7 +594,14 @@ static void tegra_gem_prime_kunmap(struct dma_buf *buf, unsigned long page, static int tegra_gem_prime_mmap(struct dma_buf *buf, struct vm_area_struct *vma) { - return -EINVAL; + struct drm_gem_object *gem = buf->priv; + int err; + + err = drm_gem_mmap_obj(gem, gem->size, vma); + if (err < 0) + return err; + + return tegra_gem_mmap(gem, vma); } static void *tegra_gem_prime_vmap(struct dma_buf *buf) @@ -654,7 +652,7 @@ struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm, struct drm_gem_object *gem = buf->priv; if (gem->dev == drm) { - drm_gem_object_reference(gem); + drm_gem_object_get(gem); return gem; } } diff --git a/drivers/gpu/drm/tegra/gem.h b/drivers/gpu/drm/tegra/gem.h index 8b32a6fd586d..8eb9fd24ef0e 100644 --- a/drivers/gpu/drm/tegra/gem.h +++ b/drivers/gpu/drm/tegra/gem.h @@ -67,8 +67,6 @@ struct tegra_bo *tegra_bo_create_with_handle(struct drm_file *file, void tegra_bo_free_object(struct drm_gem_object *gem); int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm, struct drm_mode_create_dumb *args); -int tegra_bo_dumb_map_offset(struct drm_file *file, struct drm_device *drm, - u32 handle, u64 *offset); int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma); diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index a621b0da4092..5b9d83b71943 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -24,6 +24,7 @@ #include "hdmi.h" #include "drm.h" #include "dc.h" +#include "trace.h" #define HDMI_ELD_BUFFER_SIZE 96 @@ -100,14 +101,19 @@ enum { }; static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, - unsigned long offset) + unsigned int offset) { - return readl(hdmi->regs + (offset << 2)); + u32 value = readl(hdmi->regs + (offset << 2)); + + trace_hdmi_readl(hdmi->dev, offset, value); + + return value; } static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, - unsigned long offset) + unsigned int offset) { + trace_hdmi_writel(hdmi->dev, offset, value); writel(value, hdmi->regs + (offset << 2)); } diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index e0642d05a8d3..7ab1d1dc7cd7 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -26,6 +26,7 @@ #include "dc.h" #include "drm.h" #include "sor.h" +#include "trace.h" #define SOR_REKEY 0x38 @@ -232,14 +233,19 @@ static inline struct tegra_sor *to_sor(struct tegra_output *output) return container_of(output, struct tegra_sor, output); } -static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) +static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) { - return readl(sor->regs + (offset << 2)); + u32 value = readl(sor->regs + (offset << 2)); + + trace_sor_readl(sor->dev, offset, value); + + return value; } static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, - unsigned long offset) + unsigned int offset) { + trace_sor_writel(sor->dev, offset, value); writel(value, sor->regs + (offset << 2)); } diff --git a/drivers/gpu/drm/tegra/trace.c b/drivers/gpu/drm/tegra/trace.c new file mode 100644 index 000000000000..006f65c72a34 --- /dev/null +++ b/drivers/gpu/drm/tegra/trace.c @@ -0,0 +1,2 @@ +#define CREATE_TRACE_POINTS +#include "trace.h" diff --git a/drivers/gpu/drm/tegra/trace.h b/drivers/gpu/drm/tegra/trace.h new file mode 100644 index 000000000000..e9b7cdad5c4c --- /dev/null +++ b/drivers/gpu/drm/tegra/trace.h @@ -0,0 +1,68 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM tegra + +#if !defined(DRM_TEGRA_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define DRM_TEGRA_TRACE_H 1 + +#include <linux/device.h> +#include <linux/tracepoint.h> + +DECLARE_EVENT_CLASS(register_access, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value), + TP_STRUCT__entry( + __field(struct device *, dev) + __field(unsigned int, offset) + __field(u32, value) + ), + TP_fast_assign( + __entry->dev = dev; + __entry->offset = offset; + __entry->value = value; + ), + TP_printk("%s %04x %08x", dev_name(__entry->dev), __entry->offset, + __entry->value) +); + +DEFINE_EVENT(register_access, dc_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, dc_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, hdmi_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, hdmi_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, dsi_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, dsi_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, dpaux_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, dpaux_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +DEFINE_EVENT(register_access, sor_writel, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); +DEFINE_EVENT(register_access, sor_readl, + TP_PROTO(struct device *dev, unsigned int offset, u32 value), + TP_ARGS(dev, offset, value)); + +#endif /* DRM_TEGRA_TRACE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace +#include <trace/define_trace.h> diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index 47cb1aaa58b1..2448229fa653 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -258,12 +258,16 @@ static const struct tegra_drm_client_ops vic_ops = { .submit = tegra_drm_submit, }; +#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" + static const struct vic_config vic_t124_config = { - .firmware = "nvidia/tegra124/vic03_ucode.bin", + .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, }; +#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" + static const struct vic_config vic_t210_config = { - .firmware = "nvidia/tegra210/vic04_ucode.bin", + .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, }; static const struct of_device_id vic_match[] = { @@ -394,3 +398,10 @@ struct platform_driver tegra_vic_driver = { .probe = vic_probe, .remove = vic_remove, }; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) +MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); +#endif +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); +#endif diff --git a/drivers/gpu/drm/tinydrm/Kconfig b/drivers/gpu/drm/tinydrm/Kconfig index f17c3caceab2..2e790e7dced5 100644 --- a/drivers/gpu/drm/tinydrm/Kconfig +++ b/drivers/gpu/drm/tinydrm/Kconfig @@ -32,3 +32,13 @@ config TINYDRM_REPAPER 2.71" TFT EPD Panel (E2271CS021) If M is selected the module will be called repaper. + +config TINYDRM_ST7586 + tristate "DRM support for Sitronix ST7586 display panels" + depends on DRM_TINYDRM && SPI + select TINYDRM_MIPI_DBI + help + DRM driver for the following Sitronix ST7586 panels: + * LEGO MINDSTORMS EV3 + + If M is selected the module will be called st7586. diff --git a/drivers/gpu/drm/tinydrm/Makefile b/drivers/gpu/drm/tinydrm/Makefile index 95bb4d4fa785..0c184bd1bb59 100644 --- a/drivers/gpu/drm/tinydrm/Makefile +++ b/drivers/gpu/drm/tinydrm/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_TINYDRM_MIPI_DBI) += mipi-dbi.o # Displays obj-$(CONFIG_TINYDRM_MI0283QT) += mi0283qt.o obj-$(CONFIG_TINYDRM_REPAPER) += repaper.o +obj-$(CONFIG_TINYDRM_ST7586) += st7586.o diff --git a/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c b/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c index 75808bb84c9a..bd6cce093a85 100644 --- a/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c +++ b/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c @@ -185,7 +185,9 @@ EXPORT_SYMBOL(tinydrm_xrgb8888_to_rgb565); /** * tinydrm_xrgb8888_to_gray8 - Convert XRGB8888 to grayscale * @dst: 8-bit grayscale destination buffer + * @vaddr: XRGB8888 source buffer * @fb: DRM framebuffer + * @clip: Clip rectangle area to copy * * Drm doesn't have native monochrome or grayscale support. * Such drivers can announce the commonly supported XR24 format to userspace @@ -195,41 +197,31 @@ EXPORT_SYMBOL(tinydrm_xrgb8888_to_rgb565); * where 1 means foreground color and 0 background color. * * ITU BT.601 is used for the RGB -> luma (brightness) conversion. - * - * Returns: - * Zero on success, negative error code on failure. */ -int tinydrm_xrgb8888_to_gray8(u8 *dst, struct drm_framebuffer *fb) +void tinydrm_xrgb8888_to_gray8(u8 *dst, void *vaddr, struct drm_framebuffer *fb, + struct drm_clip_rect *clip) { - struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0); - struct dma_buf_attachment *import_attach = cma_obj->base.import_attach; - unsigned int x, y, pitch = fb->pitches[0]; - int ret = 0; + unsigned int len = (clip->x2 - clip->x1) * sizeof(u32); + unsigned int x, y; void *buf; u32 *src; if (WARN_ON(fb->format->format != DRM_FORMAT_XRGB8888)) - return -EINVAL; + return; /* * The cma memory is write-combined so reads are uncached. * Speed up by fetching one line at a time. */ - buf = kmalloc(pitch, GFP_KERNEL); + buf = kmalloc(len, GFP_KERNEL); if (!buf) - return -ENOMEM; - - if (import_attach) { - ret = dma_buf_begin_cpu_access(import_attach->dmabuf, - DMA_FROM_DEVICE); - if (ret) - goto err_free; - } + return; - for (y = 0; y < fb->height; y++) { - src = cma_obj->vaddr + (y * pitch); - memcpy(buf, src, pitch); + for (y = clip->y1; y < clip->y2; y++) { + src = vaddr + (y * fb->pitches[0]); + src += clip->x1; + memcpy(buf, src, len); src = buf; - for (x = 0; x < fb->width; x++) { + for (x = clip->x1; x < clip->x2; x++) { u8 r = (*src & 0x00ff0000) >> 16; u8 g = (*src & 0x0000ff00) >> 8; u8 b = *src & 0x000000ff; @@ -240,13 +232,7 @@ int tinydrm_xrgb8888_to_gray8(u8 *dst, struct drm_framebuffer *fb) } } - if (import_attach) - ret = dma_buf_end_cpu_access(import_attach->dmabuf, - DMA_FROM_DEVICE); -err_free: kfree(buf); - - return ret; } EXPORT_SYMBOL(tinydrm_xrgb8888_to_gray8); diff --git a/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c b/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c index f224b54a30f6..177e9d861001 100644 --- a/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c +++ b/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c @@ -56,7 +56,7 @@ static const struct drm_connector_helper_funcs tinydrm_connector_hfuncs = { static enum drm_connector_status tinydrm_connector_detect(struct drm_connector *connector, bool force) { - if (drm_device_is_unplugged(connector->dev)) + if (drm_dev_is_unplugged(connector->dev)) return connector_status_disconnected; return connector->status; diff --git a/drivers/gpu/drm/tinydrm/repaper.c b/drivers/gpu/drm/tinydrm/repaper.c index 3343d3f15a90..30dc97b3ff21 100644 --- a/drivers/gpu/drm/tinydrm/repaper.c +++ b/drivers/gpu/drm/tinydrm/repaper.c @@ -18,6 +18,7 @@ */ #include <linux/delay.h> +#include <linux/dma-buf.h> #include <linux/gpio/consumer.h> #include <linux/module.h> #include <linux/of_device.h> @@ -525,11 +526,20 @@ static int repaper_fb_dirty(struct drm_framebuffer *fb, struct drm_clip_rect *clips, unsigned int num_clips) { + struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0); + struct dma_buf_attachment *import_attach = cma_obj->base.import_attach; struct tinydrm_device *tdev = fb->dev->dev_private; struct repaper_epd *epd = epd_from_tinydrm(tdev); + struct drm_clip_rect clip; u8 *buf = NULL; int ret = 0; + /* repaper can't do partial updates */ + clip.x1 = 0; + clip.x2 = fb->width; + clip.y1 = 0; + clip.y2 = fb->height; + mutex_lock(&tdev->dirty_lock); if (!epd->enabled) @@ -550,9 +560,21 @@ static int repaper_fb_dirty(struct drm_framebuffer *fb, goto out_unlock; } - ret = tinydrm_xrgb8888_to_gray8(buf, fb); - if (ret) - goto out_unlock; + if (import_attach) { + ret = dma_buf_begin_cpu_access(import_attach->dmabuf, + DMA_FROM_DEVICE); + if (ret) + goto out_unlock; + } + + tinydrm_xrgb8888_to_gray8(buf, cma_obj->vaddr, fb, &clip); + + if (import_attach) { + ret = dma_buf_end_cpu_access(import_attach->dmabuf, + DMA_FROM_DEVICE); + if (ret) + goto out_unlock; + } repaper_gray8_to_mono_reversed(buf, fb->width, fb->height); diff --git a/drivers/gpu/drm/tinydrm/st7586.c b/drivers/gpu/drm/tinydrm/st7586.c new file mode 100644 index 000000000000..b439956a07f4 --- /dev/null +++ b/drivers/gpu/drm/tinydrm/st7586.c @@ -0,0 +1,428 @@ +/* + * DRM driver for Sitronix ST7586 panels + * + * Copyright 2017 David Lechner <david@lechnology.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/delay.h> +#include <linux/dma-buf.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/spi/spi.h> +#include <video/mipi_display.h> + +#include <drm/tinydrm/mipi-dbi.h> +#include <drm/tinydrm/tinydrm-helpers.h> + +/* controller-specific commands */ +#define ST7586_DISP_MODE_GRAY 0x38 +#define ST7586_DISP_MODE_MONO 0x39 +#define ST7586_ENABLE_DDRAM 0x3a +#define ST7586_SET_DISP_DUTY 0xb0 +#define ST7586_SET_PART_DISP 0xb4 +#define ST7586_SET_NLINE_INV 0xb5 +#define ST7586_SET_VOP 0xc0 +#define ST7586_SET_BIAS_SYSTEM 0xc3 +#define ST7586_SET_BOOST_LEVEL 0xc4 +#define ST7586_SET_VOP_OFFSET 0xc7 +#define ST7586_ENABLE_ANALOG 0xd0 +#define ST7586_AUTO_READ_CTRL 0xd7 +#define ST7586_OTP_RW_CTRL 0xe0 +#define ST7586_OTP_CTRL_OUT 0xe1 +#define ST7586_OTP_READ 0xe3 + +#define ST7586_DISP_CTRL_MX BIT(6) +#define ST7586_DISP_CTRL_MY BIT(7) + +/* + * The ST7586 controller has an unusual pixel format where 2bpp grayscale is + * packed 3 pixels per byte with the first two pixels using 3 bits and the 3rd + * pixel using only 2 bits. + * + * | D7 | D6 | D5 || | || 2bpp | + * | (D4) | (D3) | (D2) || D1 | D0 || GRAY | + * +------+------+------++------+------++------+ + * | 1 | 1 | 1 || 1 | 1 || 0 0 | black + * | 1 | 0 | 0 || 1 | 0 || 0 1 | dark gray + * | 0 | 1 | 0 || 0 | 1 || 1 0 | light gray + * | 0 | 0 | 0 || 0 | 0 || 1 1 | white + */ + +static const u8 st7586_lookup[] = { 0x7, 0x4, 0x2, 0x0 }; + +static void st7586_xrgb8888_to_gray332(u8 *dst, void *vaddr, + struct drm_framebuffer *fb, + struct drm_clip_rect *clip) +{ + size_t len = (clip->x2 - clip->x1) * (clip->y2 - clip->y1); + unsigned int x, y; + u8 *src, *buf, val; + + buf = kmalloc(len, GFP_KERNEL); + if (!buf) + return; + + tinydrm_xrgb8888_to_gray8(buf, vaddr, fb, clip); + src = buf; + + for (y = clip->y1; y < clip->y2; y++) { + for (x = clip->x1; x < clip->x2; x += 3) { + val = st7586_lookup[*src++ >> 6] << 5; + val |= st7586_lookup[*src++ >> 6] << 2; + val |= st7586_lookup[*src++ >> 6] >> 1; + *dst++ = val; + } + } + + kfree(buf); +} + +static int st7586_buf_copy(void *dst, struct drm_framebuffer *fb, + struct drm_clip_rect *clip) +{ + struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0); + struct dma_buf_attachment *import_attach = cma_obj->base.import_attach; + void *src = cma_obj->vaddr; + int ret = 0; + + if (import_attach) { + ret = dma_buf_begin_cpu_access(import_attach->dmabuf, + DMA_FROM_DEVICE); + if (ret) + return ret; + } + + st7586_xrgb8888_to_gray332(dst, src, fb, clip); + + if (import_attach) + ret = dma_buf_end_cpu_access(import_attach->dmabuf, + DMA_FROM_DEVICE); + + return ret; +} + +static int st7586_fb_dirty(struct drm_framebuffer *fb, + struct drm_file *file_priv, unsigned int flags, + unsigned int color, struct drm_clip_rect *clips, + unsigned int num_clips) +{ + struct tinydrm_device *tdev = fb->dev->dev_private; + struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev); + struct drm_clip_rect clip; + int start, end; + int ret = 0; + + mutex_lock(&tdev->dirty_lock); + + if (!mipi->enabled) + goto out_unlock; + + /* fbdev can flush even when we're not interested */ + if (tdev->pipe.plane.fb != fb) + goto out_unlock; + + tinydrm_merge_clips(&clip, clips, num_clips, flags, fb->width, + fb->height); + + /* 3 pixels per byte, so grow clip to nearest multiple of 3 */ + clip.x1 = rounddown(clip.x1, 3); + clip.x2 = roundup(clip.x2, 3); + + DRM_DEBUG("Flushing [FB:%d] x1=%u, x2=%u, y1=%u, y2=%u\n", fb->base.id, + clip.x1, clip.x2, clip.y1, clip.y2); + + ret = st7586_buf_copy(mipi->tx_buf, fb, &clip); + if (ret) + goto out_unlock; + + /* Pixels are packed 3 per byte */ + start = clip.x1 / 3; + end = clip.x2 / 3; + + mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS, + (start >> 8) & 0xFF, start & 0xFF, + (end >> 8) & 0xFF, (end - 1) & 0xFF); + mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS, + (clip.y1 >> 8) & 0xFF, clip.y1 & 0xFF, + (clip.y2 >> 8) & 0xFF, (clip.y2 - 1) & 0xFF); + + ret = mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START, + (u8 *)mipi->tx_buf, + (end - start) * (clip.y2 - clip.y1)); + +out_unlock: + mutex_unlock(&tdev->dirty_lock); + + if (ret) + dev_err_once(fb->dev->dev, "Failed to update display %d\n", + ret); + + return ret; +} + +static const struct drm_framebuffer_funcs st7586_fb_funcs = { + .destroy = drm_fb_cma_destroy, + .create_handle = drm_fb_cma_create_handle, + .dirty = st7586_fb_dirty, +}; + +static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe, + struct drm_crtc_state *crtc_state) +{ + struct tinydrm_device *tdev = pipe_to_tinydrm(pipe); + struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev); + struct drm_framebuffer *fb = pipe->plane.fb; + struct device *dev = tdev->drm->dev; + int ret; + u8 addr_mode; + + DRM_DEBUG_KMS("\n"); + + mipi_dbi_hw_reset(mipi); + ret = mipi_dbi_command(mipi, ST7586_AUTO_READ_CTRL, 0x9f); + if (ret) { + dev_err(dev, "Error sending command %d\n", ret); + return; + } + + mipi_dbi_command(mipi, ST7586_OTP_RW_CTRL, 0x00); + + msleep(10); + + mipi_dbi_command(mipi, ST7586_OTP_READ); + + msleep(20); + + mipi_dbi_command(mipi, ST7586_OTP_CTRL_OUT); + mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE); + mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_OFF); + + msleep(50); + + mipi_dbi_command(mipi, ST7586_SET_VOP_OFFSET, 0x00); + mipi_dbi_command(mipi, ST7586_SET_VOP, 0xe3, 0x00); + mipi_dbi_command(mipi, ST7586_SET_BIAS_SYSTEM, 0x02); + mipi_dbi_command(mipi, ST7586_SET_BOOST_LEVEL, 0x04); + mipi_dbi_command(mipi, ST7586_ENABLE_ANALOG, 0x1d); + mipi_dbi_command(mipi, ST7586_SET_NLINE_INV, 0x00); + mipi_dbi_command(mipi, ST7586_DISP_MODE_GRAY); + mipi_dbi_command(mipi, ST7586_ENABLE_DDRAM, 0x02); + + switch (mipi->rotation) { + default: + addr_mode = 0x00; + break; + case 90: + addr_mode = ST7586_DISP_CTRL_MY; + break; + case 180: + addr_mode = ST7586_DISP_CTRL_MX | ST7586_DISP_CTRL_MY; + break; + case 270: + addr_mode = ST7586_DISP_CTRL_MX; + break; + } + mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); + + mipi_dbi_command(mipi, ST7586_SET_DISP_DUTY, 0x7f); + mipi_dbi_command(mipi, ST7586_SET_PART_DISP, 0xa0); + mipi_dbi_command(mipi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77); + mipi_dbi_command(mipi, MIPI_DCS_EXIT_INVERT_MODE); + + msleep(100); + + mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON); + + mipi->enabled = true; + + if (fb) + fb->funcs->dirty(fb, NULL, 0, 0, NULL, 0); +} + +static void st7586_pipe_disable(struct drm_simple_display_pipe *pipe) +{ + struct tinydrm_device *tdev = pipe_to_tinydrm(pipe); + struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev); + + DRM_DEBUG_KMS("\n"); + + if (!mipi->enabled) + return; + + mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_OFF); + mipi->enabled = false; +} + +static const u32 st7586_formats[] = { + DRM_FORMAT_XRGB8888, +}; + +static int st7586_init(struct device *dev, struct mipi_dbi *mipi, + const struct drm_simple_display_pipe_funcs *pipe_funcs, + struct drm_driver *driver, const struct drm_display_mode *mode, + unsigned int rotation) +{ + size_t bufsize = (mode->vdisplay + 2) / 3 * mode->hdisplay; + struct tinydrm_device *tdev = &mipi->tinydrm; + int ret; + + mutex_init(&mipi->cmdlock); + + mipi->tx_buf = devm_kmalloc(dev, bufsize, GFP_KERNEL); + if (!mipi->tx_buf) + return -ENOMEM; + + ret = devm_tinydrm_init(dev, tdev, &st7586_fb_funcs, driver); + if (ret) + return ret; + + ret = tinydrm_display_pipe_init(tdev, pipe_funcs, + DRM_MODE_CONNECTOR_VIRTUAL, + st7586_formats, + ARRAY_SIZE(st7586_formats), + mode, rotation); + if (ret) + return ret; + + tdev->drm->mode_config.preferred_depth = 32; + mipi->rotation = rotation; + + drm_mode_config_reset(tdev->drm); + + DRM_DEBUG_KMS("preferred_depth=%u, rotation = %u\n", + tdev->drm->mode_config.preferred_depth, rotation); + + return 0; +} + +static const struct drm_simple_display_pipe_funcs st7586_pipe_funcs = { + .enable = st7586_pipe_enable, + .disable = st7586_pipe_disable, + .update = tinydrm_display_pipe_update, + .prepare_fb = tinydrm_display_pipe_prepare_fb, +}; + +static const struct drm_display_mode st7586_mode = { + TINYDRM_MODE(178, 128, 37, 27), +}; + +DEFINE_DRM_GEM_CMA_FOPS(st7586_fops); + +static struct drm_driver st7586_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | + DRIVER_ATOMIC, + .fops = &st7586_fops, + TINYDRM_GEM_DRIVER_OPS, + .lastclose = tinydrm_lastclose, + .debugfs_init = mipi_dbi_debugfs_init, + .name = "st7586", + .desc = "Sitronix ST7586", + .date = "20170801", + .major = 1, + .minor = 0, +}; + +static const struct of_device_id st7586_of_match[] = { + { .compatible = "lego,ev3-lcd" }, + {}, +}; +MODULE_DEVICE_TABLE(of, st7586_of_match); + +static const struct spi_device_id st7586_id[] = { + { "ev3-lcd", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(spi, st7586_id); + +static int st7586_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct tinydrm_device *tdev; + struct mipi_dbi *mipi; + struct gpio_desc *a0; + u32 rotation = 0; + int ret; + + mipi = devm_kzalloc(dev, sizeof(*mipi), GFP_KERNEL); + if (!mipi) + return -ENOMEM; + + mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(mipi->reset)) { + dev_err(dev, "Failed to get gpio 'reset'\n"); + return PTR_ERR(mipi->reset); + } + + a0 = devm_gpiod_get(dev, "a0", GPIOD_OUT_LOW); + if (IS_ERR(a0)) { + dev_err(dev, "Failed to get gpio 'a0'\n"); + return PTR_ERR(a0); + } + + device_property_read_u32(dev, "rotation", &rotation); + + ret = mipi_dbi_spi_init(spi, mipi, a0); + if (ret) + return ret; + + /* Cannot read from this controller via SPI */ + mipi->read_commands = NULL; + + /* + * we are using 8-bit data, so we are not actually swapping anything, + * but setting mipi->swap_bytes makes mipi_dbi_typec3_command() do the + * right thing and not use 16-bit transfers (which results in swapped + * bytes on little-endian systems and causes out of order data to be + * sent to the display). + */ + mipi->swap_bytes = true; + + ret = st7586_init(&spi->dev, mipi, &st7586_pipe_funcs, &st7586_driver, + &st7586_mode, rotation); + if (ret) + return ret; + + tdev = &mipi->tinydrm; + + ret = devm_tinydrm_register(tdev); + if (ret) + return ret; + + spi_set_drvdata(spi, mipi); + + DRM_DEBUG_DRIVER("Initialized %s:%s @%uMHz on minor %d\n", + tdev->drm->driver->name, dev_name(dev), + spi->max_speed_hz / 1000000, + tdev->drm->primary->index); + + return 0; +} + +static void st7586_shutdown(struct spi_device *spi) +{ + struct mipi_dbi *mipi = spi_get_drvdata(spi); + + tinydrm_shutdown(&mipi->tinydrm); +} + +static struct spi_driver st7586_spi_driver = { + .driver = { + .name = "st7586", + .owner = THIS_MODULE, + .of_match_table = st7586_of_match, + }, + .id_table = st7586_id, + .probe = st7586_probe, + .shutdown = st7586_shutdown, +}; +module_spi_driver(st7586_spi_driver); + +MODULE_DESCRIPTION("Sitronix ST7586 DRM driver"); +MODULE_AUTHOR("David Lechner <david@lechnology.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 22b57020790d..cba11f13d994 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -70,6 +70,7 @@ static inline int ttm_mem_type_from_place(const struct ttm_place *place, static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type) { struct ttm_mem_type_manager *man = &bdev->man[mem_type]; + struct drm_printer p = drm_debug_printer(TTM_PFX); pr_err(" has_type: %d\n", man->has_type); pr_err(" use_type: %d\n", man->use_type); @@ -79,7 +80,7 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type) pr_err(" available_caching: 0x%08X\n", man->available_caching); pr_err(" default_caching: 0x%08X\n", man->default_caching); if (mem_type != TTM_PL_SYSTEM) - (*man->func->debug)(man, TTM_PFX); + (*man->func->debug)(man, &p); } static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, @@ -394,14 +395,33 @@ static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo) ww_mutex_unlock (&bo->resv->lock); } +static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) +{ + int r; + + if (bo->resv == &bo->ttm_resv) + return 0; + + reservation_object_init(&bo->ttm_resv); + BUG_ON(!reservation_object_trylock(&bo->ttm_resv)); + + r = reservation_object_copy_fences(&bo->ttm_resv, bo->resv); + if (r) { + reservation_object_unlock(&bo->ttm_resv); + reservation_object_fini(&bo->ttm_resv); + } + + return r; +} + static void ttm_bo_flush_all_fences(struct ttm_buffer_object *bo) { struct reservation_object_list *fobj; struct dma_fence *fence; int i; - fobj = reservation_object_get_list(bo->resv); - fence = reservation_object_get_excl(bo->resv); + fobj = reservation_object_get_list(&bo->ttm_resv); + fence = reservation_object_get_excl(&bo->ttm_resv); if (fence && !fence->ops->signaled) dma_fence_enable_sw_signaling(fence); @@ -430,8 +450,19 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) ttm_bo_cleanup_memtype_use(bo); return; - } else - ttm_bo_flush_all_fences(bo); + } + + ret = ttm_bo_individualize_resv(bo); + if (ret) { + /* Last resort, if we fail to allocate memory for the + * fences block for the BO to become idle and free it. + */ + spin_unlock(&glob->lru_lock); + ttm_bo_wait(bo, true, true); + ttm_bo_cleanup_memtype_use(bo); + return; + } + ttm_bo_flush_all_fences(bo); /* * Make NO_EVICT bos immediately available to @@ -443,6 +474,8 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) ttm_bo_add_to_lru(bo); } + if (bo->resv != &bo->ttm_resv) + reservation_object_unlock(&bo->ttm_resv); __ttm_bo_unreserve(bo); } @@ -471,17 +504,25 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, bool no_wait_gpu) { struct ttm_bo_global *glob = bo->glob; + struct reservation_object *resv; int ret; - ret = ttm_bo_wait(bo, false, true); + if (unlikely(list_empty(&bo->ddestroy))) + resv = bo->resv; + else + resv = &bo->ttm_resv; + + if (reservation_object_test_signaled_rcu(resv, true)) + ret = 0; + else + ret = -EBUSY; if (ret && !no_wait_gpu) { long lret; ww_mutex_unlock(&bo->resv->lock); spin_unlock(&glob->lru_lock); - lret = reservation_object_wait_timeout_rcu(bo->resv, - true, + lret = reservation_object_wait_timeout_rcu(resv, true, interruptible, 30 * HZ); @@ -505,13 +546,6 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, spin_unlock(&glob->lru_lock); return 0; } - - /* - * remove sync_obj with ttm_bo_wait, the wait should be - * finished, and no new wait object should have been added. - */ - ret = ttm_bo_wait(bo, false, true); - WARN_ON(ret); } if (ret || unlikely(list_empty(&bo->ddestroy))) { diff --git a/drivers/gpu/drm/ttm/ttm_bo_manager.c b/drivers/gpu/drm/ttm/ttm_bo_manager.c index 90a6c0b03afc..a7c232dc39cb 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_manager.c +++ b/drivers/gpu/drm/ttm/ttm_bo_manager.c @@ -136,13 +136,12 @@ static int ttm_bo_man_takedown(struct ttm_mem_type_manager *man) } static void ttm_bo_man_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv; - struct drm_printer p = drm_debug_printer(prefix); spin_lock(&rman->lock); - drm_mm_print(&rman->mm, &p); + drm_mm_print(&rman->mm, printer); spin_unlock(&rman->lock); } diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index eeddc1e48409..871599826773 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -615,7 +615,7 @@ static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool, } else { pr_err("Failed to fill pool (%p)\n", pool); /* If we have any pages left put them to the pool. */ - list_for_each_entry(p, &pool->list, lru) { + list_for_each_entry(p, &new_pages, lru) { ++cpages; } list_splice(&new_pages, &pool->list); diff --git a/drivers/gpu/drm/udl/udl_connector.c b/drivers/gpu/drm/udl/udl_connector.c index d2f57c52f7db..9f9a49748d17 100644 --- a/drivers/gpu/drm/udl/udl_connector.c +++ b/drivers/gpu/drm/udl/udl_connector.c @@ -96,7 +96,7 @@ static int udl_mode_valid(struct drm_connector *connector, static enum drm_connector_status udl_detect(struct drm_connector *connector, bool force) { - if (drm_device_is_unplugged(connector->dev)) + if (drm_dev_is_unplugged(connector->dev)) return connector_status_disconnected; return connector_status_connected; } diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c index 0f02e1acf0ba..31421b6b586e 100644 --- a/drivers/gpu/drm/udl/udl_drv.c +++ b/drivers/gpu/drm/udl/udl_drv.c @@ -54,7 +54,6 @@ static struct drm_driver driver = { .dumb_create = udl_dumb_create, .dumb_map_offset = udl_gem_mmap, - .dumb_destroy = drm_gem_dumb_destroy, .fops = &udl_driver_fops, .prime_handle_to_fd = drm_gem_prime_handle_to_fd, @@ -102,7 +101,7 @@ static void udl_usb_disconnect(struct usb_interface *interface) drm_kms_helper_poll_disable(dev); udl_fbdev_unplug(dev); udl_drop_usb(dev); - drm_unplug_dev(dev); + drm_dev_unplug(dev); } /* @@ -112,7 +111,7 @@ static void udl_usb_disconnect(struct usb_interface *interface) * which is compatible with all known USB 2.0 era graphics chips and firmware, * but allows DisplayLink to increment those for any future incompatible chips */ -static struct usb_device_id id_table[] = { +static const struct usb_device_id id_table[] = { {.idVendor = 0x17e9, .bInterfaceClass = 0xff, .bInterfaceSubClass = 0x00, .bInterfaceProtocol = 0x00, diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c index a5c54dc60def..b7ca90db4e80 100644 --- a/drivers/gpu/drm/udl/udl_fb.c +++ b/drivers/gpu/drm/udl/udl_fb.c @@ -198,7 +198,7 @@ static int udl_fb_open(struct fb_info *info, int user) struct udl_device *udl = dev->dev_private; /* If the USB device is gone, we don't accept new opens */ - if (drm_device_is_unplugged(udl->ddev)) + if (drm_dev_is_unplugged(udl->ddev)) return -ENODEV; ufbdev->fb_count++; @@ -309,7 +309,7 @@ static void udl_user_framebuffer_destroy(struct drm_framebuffer *fb) struct udl_framebuffer *ufb = to_udl_fb(fb); if (ufb->obj) - drm_gem_object_unreference_unlocked(&ufb->obj->base); + drm_gem_object_put_unlocked(&ufb->obj->base); drm_framebuffer_cleanup(fb); kfree(ufb); @@ -403,7 +403,7 @@ static int udlfb_create(struct drm_fb_helper *helper, return ret; out_gfree: - drm_gem_object_unreference_unlocked(&ufbdev->ufb.obj->base); + drm_gem_object_put_unlocked(&ufbdev->ufb.obj->base); out: return ret; } @@ -419,7 +419,7 @@ static void udl_fbdev_destroy(struct drm_device *dev, drm_fb_helper_fini(&ufbdev->helper); drm_framebuffer_unregister_private(&ufbdev->ufb.base); drm_framebuffer_cleanup(&ufbdev->ufb.base); - drm_gem_object_unreference_unlocked(&ufbdev->ufb.obj->base); + drm_gem_object_put_unlocked(&ufbdev->ufb.obj->base); } int udl_fbdev_init(struct drm_device *dev) diff --git a/drivers/gpu/drm/udl/udl_gem.c b/drivers/gpu/drm/udl/udl_gem.c index db9ceceba30e..dee6bd9a3dd1 100644 --- a/drivers/gpu/drm/udl/udl_gem.c +++ b/drivers/gpu/drm/udl/udl_gem.c @@ -52,7 +52,7 @@ udl_gem_create(struct drm_file *file, return ret; } - drm_gem_object_unreference_unlocked(&obj->base); + drm_gem_object_put_unlocked(&obj->base); *handle_p = handle; return 0; } @@ -234,7 +234,7 @@ int udl_gem_mmap(struct drm_file *file, struct drm_device *dev, *offset = drm_vma_node_offset_addr(&gobj->base.vma_node); out: - drm_gem_object_unreference(&gobj->base); + drm_gem_object_put(&gobj->base); unlock: mutex_unlock(&dev->struct_mutex); return ret; diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c index b24dd8685590..3afdbf4bc10b 100644 --- a/drivers/gpu/drm/vc4/vc4_bo.c +++ b/drivers/gpu/drm/vc4/vc4_bo.c @@ -366,7 +366,7 @@ int vc4_dumb_create(struct drm_file *file_priv, return PTR_ERR(bo); ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); - drm_gem_object_unreference_unlocked(&bo->base.base); + drm_gem_object_put_unlocked(&bo->base.base); return ret; } @@ -482,7 +482,7 @@ vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags) struct vc4_bo *bo = to_vc4_bo(obj); if (bo->validated_shader) { - DRM_ERROR("Attempting to export shader BO\n"); + DRM_DEBUG("Attempting to export shader BO\n"); return ERR_PTR(-EINVAL); } @@ -503,7 +503,7 @@ int vc4_mmap(struct file *filp, struct vm_area_struct *vma) bo = to_vc4_bo(gem_obj); if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { - DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); + DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n"); return -EINVAL; } @@ -528,7 +528,7 @@ int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) struct vc4_bo *bo = to_vc4_bo(obj); if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) { - DRM_ERROR("mmaping of shader BOs for writing not allowed.\n"); + DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n"); return -EINVAL; } @@ -540,7 +540,7 @@ void *vc4_prime_vmap(struct drm_gem_object *obj) struct vc4_bo *bo = to_vc4_bo(obj); if (bo->validated_shader) { - DRM_ERROR("mmaping of shader BOs not allowed.\n"); + DRM_DEBUG("mmaping of shader BOs not allowed.\n"); return ERR_PTR(-EINVAL); } @@ -581,7 +581,7 @@ int vc4_create_bo_ioctl(struct drm_device *dev, void *data, return PTR_ERR(bo); ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); - drm_gem_object_unreference_unlocked(&bo->base.base); + drm_gem_object_put_unlocked(&bo->base.base); return ret; } @@ -594,14 +594,14 @@ int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, gem_obj = drm_gem_object_lookup(file_priv, args->handle); if (!gem_obj) { - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle); return -EINVAL; } /* The mmap offset was set up at BO allocation time. */ args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node); - drm_gem_object_unreference_unlocked(gem_obj); + drm_gem_object_put_unlocked(gem_obj); return 0; } @@ -657,7 +657,7 @@ vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); fail: - drm_gem_object_unreference_unlocked(&bo->base.base); + drm_gem_object_put_unlocked(&bo->base.base); return ret; } @@ -698,13 +698,13 @@ int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, gem_obj = drm_gem_object_lookup(file_priv, args->handle); if (!gem_obj) { - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle); return -ENOENT; } bo = to_vc4_bo(gem_obj); bo->t_format = t_format; - drm_gem_object_unreference_unlocked(gem_obj); + drm_gem_object_put_unlocked(gem_obj); return 0; } @@ -729,7 +729,7 @@ int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, gem_obj = drm_gem_object_lookup(file_priv, args->handle); if (!gem_obj) { - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle); return -ENOENT; } bo = to_vc4_bo(gem_obj); @@ -739,7 +739,7 @@ int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, else args->modifier = DRM_FORMAT_MOD_NONE; - drm_gem_object_unreference_unlocked(gem_obj); + drm_gem_object_put_unlocked(gem_obj); return 0; } @@ -830,7 +830,7 @@ int vc4_label_bo_ioctl(struct drm_device *dev, void *data, ret = -ENOMEM; mutex_unlock(&vc4->bo_lock); - drm_gem_object_unreference_unlocked(gem_obj); + drm_gem_object_put_unlocked(gem_obj); return ret; } diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 664a55b45af0..ce1e3b9e14c9 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -763,7 +763,7 @@ vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) } drm_crtc_vblank_put(crtc); - drm_framebuffer_unreference(flip_state->fb); + drm_framebuffer_put(flip_state->fb); kfree(flip_state); up(&vc4->async_modeset); @@ -792,7 +792,7 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, if (!flip_state) return -ENOMEM; - drm_framebuffer_reference(fb); + drm_framebuffer_get(fb); flip_state->fb = fb; flip_state->crtc = crtc; flip_state->event = event; @@ -800,7 +800,7 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, /* Make sure all other async modesetes have landed. */ ret = down_interruptible(&vc4->async_modeset); if (ret) { - drm_framebuffer_unreference(fb); + drm_framebuffer_put(fb); kfree(flip_state); return ret; } diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c index e8f0e1790d5e..1c96edcb302b 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.c +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -99,6 +99,7 @@ static int vc4_get_param_ioctl(struct drm_device *dev, void *data, case DRM_VC4_PARAM_SUPPORTS_BRANCHES: case DRM_VC4_PARAM_SUPPORTS_ETC1: case DRM_VC4_PARAM_SUPPORTS_THREADED_FS: + case DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER: args->value = true; break; default: diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index 629d372633e6..d1e0dc908048 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -1636,14 +1636,10 @@ static void vc4_dsi_unbind(struct device *dev, struct device *master, pm_runtime_disable(dev); - drm_bridge_remove(dsi->bridge); vc4_dsi_encoder_destroy(dsi->encoder); mipi_dsi_host_unregister(&dsi->dsi_host); - clk_disable_unprepare(dsi->pll_phy_clock); - clk_disable_unprepare(dsi->escape_clock); - if (dsi->port == 1) vc4->dsi1 = NULL; } diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c index 209fccd0d3b4..d0c6bfb68c4e 100644 --- a/drivers/gpu/drm/vc4/vc4_gem.c +++ b/drivers/gpu/drm/vc4/vc4_gem.c @@ -55,7 +55,7 @@ vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state) unsigned int i; for (i = 0; i < state->user_state.bo_count; i++) - drm_gem_object_unreference_unlocked(state->bo[i]); + drm_gem_object_put_unlocked(state->bo[i]); kfree(state); } @@ -188,12 +188,12 @@ vc4_save_hang_state(struct drm_device *dev) continue; for (j = 0; j < exec[i]->bo_count; j++) { - drm_gem_object_reference(&exec[i]->bo[j]->base); + drm_gem_object_get(&exec[i]->bo[j]->base); kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base; } list_for_each_entry(bo, &exec[i]->unref_list, unref_head) { - drm_gem_object_reference(&bo->base.base); + drm_gem_object_get(&bo->base.base); kernel_state->bo[j + prev_idx] = &bo->base.base; j++; } @@ -659,7 +659,7 @@ vc4_cl_lookup_bos(struct drm_device *dev, /* See comment on bo_index for why we have to check * this. */ - DRM_ERROR("Rendering requires BOs to validate\n"); + DRM_DEBUG("Rendering requires BOs to validate\n"); return -EINVAL; } @@ -690,13 +690,13 @@ vc4_cl_lookup_bos(struct drm_device *dev, struct drm_gem_object *bo = idr_find(&file_priv->object_idr, handles[i]); if (!bo) { - DRM_ERROR("Failed to look up GEM BO %d: %d\n", + DRM_DEBUG("Failed to look up GEM BO %d: %d\n", i, handles[i]); ret = -EINVAL; spin_unlock(&file_priv->table_lock); goto fail; } - drm_gem_object_reference(bo); + drm_gem_object_get(bo); exec->bo[i] = (struct drm_gem_cma_object *)bo; } spin_unlock(&file_priv->table_lock); @@ -728,7 +728,7 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec) args->shader_rec_count >= (UINT_MAX / sizeof(struct vc4_shader_state)) || temp_size < exec_size) { - DRM_ERROR("overflow in exec arguments\n"); + DRM_DEBUG("overflow in exec arguments\n"); ret = -EINVAL; goto fail; } @@ -834,7 +834,7 @@ vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) if (exec->bo) { for (i = 0; i < exec->bo_count; i++) - drm_gem_object_unreference_unlocked(&exec->bo[i]->base); + drm_gem_object_put_unlocked(&exec->bo[i]->base); kvfree(exec->bo); } @@ -842,7 +842,7 @@ vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec) struct vc4_bo *bo = list_first_entry(&exec->unref_list, struct vc4_bo, unref_head); list_del(&bo->unref_head); - drm_gem_object_unreference_unlocked(&bo->base.base); + drm_gem_object_put_unlocked(&bo->base.base); } /* Free up the allocation of any bin slots we used. */ @@ -973,7 +973,7 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data, gem_obj = drm_gem_object_lookup(file_priv, args->handle); if (!gem_obj) { - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle); + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle); return -EINVAL; } bo = to_vc4_bo(gem_obj); @@ -981,7 +981,7 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data, ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno, &args->timeout_ns); - drm_gem_object_unreference_unlocked(gem_obj); + drm_gem_object_put_unlocked(gem_obj); return ret; } @@ -1007,8 +1007,11 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data, struct ww_acquire_ctx acquire_ctx; int ret = 0; - if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) { - DRM_ERROR("Unknown flags: 0x%02x\n", args->flags); + if ((args->flags & ~(VC4_SUBMIT_CL_USE_CLEAR_COLOR | + VC4_SUBMIT_CL_FIXED_RCL_ORDER | + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X | + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) != 0) { + DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags); return -EINVAL; } @@ -1117,6 +1120,4 @@ vc4_gem_destroy(struct drm_device *dev) if (vc4->hang_state) vc4_free_hang_state(dev, vc4->hang_state); - - vc4_bo_cache_destroy(dev); } diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index ff09b8e2f9ee..937da8dd65b8 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -288,6 +288,7 @@ static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) drm_mode_connector_update_edid_property(connector, edid); ret = drm_add_edid_modes(connector, edid); drm_edid_to_eld(connector, edid); + kfree(edid); return ret; } diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index aeec6e8703d2..50c4959b5bd3 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -20,6 +20,7 @@ #include <drm/drm_crtc_helper.h> #include <drm/drm_plane_helper.h> #include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> #include "vc4_drv.h" static void vc4_output_poll_changed(struct drm_device *dev) @@ -169,7 +170,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, gem_obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); if (!gem_obj) { - DRM_ERROR("Failed to look up GEM BO %d\n", + DRM_DEBUG("Failed to look up GEM BO %d\n", mode_cmd->handles[0]); return ERR_PTR(-ENOENT); } @@ -184,12 +185,12 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE; } - drm_gem_object_unreference_unlocked(gem_obj); + drm_gem_object_put_unlocked(gem_obj); mode_cmd = &mode_cmd_local; } - return drm_fb_cma_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, mode_cmd); } static const struct drm_mode_config_funcs vc4_mode_funcs = { diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c index 4a8051532f00..273984f71ae2 100644 --- a/drivers/gpu/drm/vc4/vc4_render_cl.c +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c @@ -261,8 +261,17 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, uint8_t max_y_tile = args->max_y_tile; uint8_t xtiles = max_x_tile - min_x_tile + 1; uint8_t ytiles = max_y_tile - min_y_tile + 1; - uint8_t x, y; + uint8_t xi, yi; uint32_t size, loop_body_size; + bool positive_x = true; + bool positive_y = true; + + if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) { + if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X)) + positive_x = false; + if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) + positive_y = false; + } size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE; loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE; @@ -354,10 +363,12 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, rcl_u16(setup, args->height); rcl_u16(setup, args->color_write.bits); - for (y = min_y_tile; y <= max_y_tile; y++) { - for (x = min_x_tile; x <= max_x_tile; x++) { - bool first = (x == min_x_tile && y == min_y_tile); - bool last = (x == max_x_tile && y == max_y_tile); + for (yi = 0; yi < ytiles; yi++) { + int y = positive_y ? min_y_tile + yi : max_y_tile - yi; + for (xi = 0; xi < xtiles; xi++) { + int x = positive_x ? min_x_tile + xi : max_x_tile - xi; + bool first = (xi == 0 && yi == 0); + bool last = (xi == xtiles - 1 && yi == ytiles - 1); emit_tile(exec, setup, x, y, first, last); } @@ -378,14 +389,14 @@ static int vc4_full_res_bounds_check(struct vc4_exec_info *exec, u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32); if (surf->offset > obj->base.size) { - DRM_ERROR("surface offset %d > BO size %zd\n", + DRM_DEBUG("surface offset %d > BO size %zd\n", surf->offset, obj->base.size); return -EINVAL; } if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < render_tiles_stride * args->max_y_tile + args->max_x_tile) { - DRM_ERROR("MSAA tile %d, %d out of bounds " + DRM_DEBUG("MSAA tile %d, %d out of bounds " "(bo size %zd, offset %d).\n", args->max_x_tile, args->max_y_tile, obj->base.size, @@ -401,7 +412,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, struct drm_vc4_submit_rcl_surface *surf) { if (surf->flags != 0 || surf->bits != 0) { - DRM_ERROR("MSAA surface had nonzero flags/bits\n"); + DRM_DEBUG("MSAA surface had nonzero flags/bits\n"); return -EINVAL; } @@ -415,7 +426,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; if (surf->offset & 0xf) { - DRM_ERROR("MSAA write must be 16b aligned.\n"); + DRM_DEBUG("MSAA write must be 16b aligned.\n"); return -EINVAL; } @@ -437,7 +448,7 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, int ret; if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { - DRM_ERROR("Extra flags set\n"); + DRM_DEBUG("Extra flags set\n"); return -EINVAL; } @@ -453,12 +464,12 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { if (surf == &exec->args->zs_write) { - DRM_ERROR("general zs write may not be a full-res.\n"); + DRM_DEBUG("general zs write may not be a full-res.\n"); return -EINVAL; } if (surf->bits != 0) { - DRM_ERROR("load/store general bits set with " + DRM_DEBUG("load/store general bits set with " "full res load/store.\n"); return -EINVAL; } @@ -473,19 +484,19 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK | VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) { - DRM_ERROR("Unknown bits in load/store: 0x%04x\n", + DRM_DEBUG("Unknown bits in load/store: 0x%04x\n", surf->bits); return -EINVAL; } if (tiling > VC4_TILING_FORMAT_LT) { - DRM_ERROR("Bad tiling format\n"); + DRM_DEBUG("Bad tiling format\n"); return -EINVAL; } if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) { if (format != 0) { - DRM_ERROR("No color format should be set for ZS\n"); + DRM_DEBUG("No color format should be set for ZS\n"); return -EINVAL; } cpp = 4; @@ -499,16 +510,16 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, cpp = 4; break; default: - DRM_ERROR("Bad tile buffer format\n"); + DRM_DEBUG("Bad tile buffer format\n"); return -EINVAL; } } else { - DRM_ERROR("Bad load/store buffer %d.\n", buffer); + DRM_DEBUG("Bad load/store buffer %d.\n", buffer); return -EINVAL; } if (surf->offset & 0xf) { - DRM_ERROR("load/store buffer must be 16b aligned.\n"); + DRM_DEBUG("load/store buffer must be 16b aligned.\n"); return -EINVAL; } @@ -533,7 +544,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, int cpp; if (surf->flags != 0) { - DRM_ERROR("No flags supported on render config.\n"); + DRM_DEBUG("No flags supported on render config.\n"); return -EINVAL; } @@ -541,7 +552,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, VC4_RENDER_CONFIG_FORMAT_MASK | VC4_RENDER_CONFIG_MS_MODE_4X | VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) { - DRM_ERROR("Unknown bits in render config: 0x%04x\n", + DRM_DEBUG("Unknown bits in render config: 0x%04x\n", surf->bits); return -EINVAL; } @@ -556,7 +567,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; if (tiling > VC4_TILING_FORMAT_LT) { - DRM_ERROR("Bad tiling format\n"); + DRM_DEBUG("Bad tiling format\n"); return -EINVAL; } @@ -569,7 +580,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, cpp = 4; break; default: - DRM_ERROR("Bad tile buffer format\n"); + DRM_DEBUG("Bad tile buffer format\n"); return -EINVAL; } @@ -590,7 +601,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) if (args->min_x_tile > args->max_x_tile || args->min_y_tile > args->max_y_tile) { - DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n", + DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n", args->min_x_tile, args->min_y_tile, args->max_x_tile, args->max_y_tile); return -EINVAL; @@ -599,7 +610,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) if (has_bin && (args->max_x_tile > exec->bin_tiles_x || args->max_y_tile > exec->bin_tiles_y)) { - DRM_ERROR("Render tiles (%d,%d) outside of bin config " + DRM_DEBUG("Render tiles (%d,%d) outside of bin config " "(%d,%d)\n", args->max_x_tile, args->max_y_tile, exec->bin_tiles_x, exec->bin_tiles_y); @@ -642,7 +653,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) */ if (!setup.color_write && !setup.zs_write && !setup.msaa_color_write && !setup.msaa_zs_write) { - DRM_ERROR("RCL requires color or Z/S write\n"); + DRM_DEBUG("RCL requires color or Z/S write\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c index 814b512c6b9a..2db485abb186 100644 --- a/drivers/gpu/drm/vc4/vc4_validate.c +++ b/drivers/gpu/drm/vc4/vc4_validate.c @@ -109,7 +109,7 @@ vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex) struct vc4_bo *bo; if (hindex >= exec->bo_count) { - DRM_ERROR("BO index %d greater than BO count %d\n", + DRM_DEBUG("BO index %d greater than BO count %d\n", hindex, exec->bo_count); return NULL; } @@ -117,7 +117,7 @@ vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex) bo = to_vc4_bo(&obj->base); if (bo->validated_shader) { - DRM_ERROR("Trying to use shader BO as something other than " + DRM_DEBUG("Trying to use shader BO as something other than " "a shader\n"); return NULL; } @@ -172,7 +172,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, * our math. */ if (width > 4096 || height > 4096) { - DRM_ERROR("Surface dimensions (%d,%d) too large", + DRM_DEBUG("Surface dimensions (%d,%d) too large", width, height); return false; } @@ -191,7 +191,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, aligned_height = round_up(height, utile_h); break; default: - DRM_ERROR("buffer tiling %d unsupported\n", tiling_format); + DRM_DEBUG("buffer tiling %d unsupported\n", tiling_format); return false; } @@ -200,7 +200,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, if (size + offset < size || size + offset > fbo->base.size) { - DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n", + DRM_DEBUG("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n", width, height, aligned_width, aligned_height, size, offset, fbo->base.size); @@ -214,7 +214,7 @@ static int validate_flush(VALIDATE_ARGS) { if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) { - DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n"); + DRM_DEBUG("Bin CL must end with VC4_PACKET_FLUSH\n"); return -EINVAL; } exec->found_flush = true; @@ -226,13 +226,13 @@ static int validate_start_tile_binning(VALIDATE_ARGS) { if (exec->found_start_tile_binning_packet) { - DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n"); + DRM_DEBUG("Duplicate VC4_PACKET_START_TILE_BINNING\n"); return -EINVAL; } exec->found_start_tile_binning_packet = true; if (!exec->found_tile_binning_mode_config_packet) { - DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); + DRM_DEBUG("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); return -EINVAL; } @@ -243,7 +243,7 @@ static int validate_increment_semaphore(VALIDATE_ARGS) { if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) { - DRM_ERROR("Bin CL must end with " + DRM_DEBUG("Bin CL must end with " "VC4_PACKET_INCREMENT_SEMAPHORE\n"); return -EINVAL; } @@ -264,7 +264,7 @@ validate_indexed_prim_list(VALIDATE_ARGS) /* Check overflow condition */ if (exec->shader_state_count == 0) { - DRM_ERROR("shader state must precede primitives\n"); + DRM_DEBUG("shader state must precede primitives\n"); return -EINVAL; } shader_state = &exec->shader_state[exec->shader_state_count - 1]; @@ -281,7 +281,7 @@ validate_indexed_prim_list(VALIDATE_ARGS) if (offset > ib->base.size || (ib->base.size - offset) / index_size < length) { - DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n", + DRM_DEBUG("IB access overflow (%d + %d*%d > %zd)\n", offset, length, index_size, ib->base.size); return -EINVAL; } @@ -301,13 +301,13 @@ validate_gl_array_primitive(VALIDATE_ARGS) /* Check overflow condition */ if (exec->shader_state_count == 0) { - DRM_ERROR("shader state must precede primitives\n"); + DRM_DEBUG("shader state must precede primitives\n"); return -EINVAL; } shader_state = &exec->shader_state[exec->shader_state_count - 1]; if (length + base_index < length) { - DRM_ERROR("primitive vertex count overflow\n"); + DRM_DEBUG("primitive vertex count overflow\n"); return -EINVAL; } max_index = length + base_index - 1; @@ -324,7 +324,7 @@ validate_gl_shader_state(VALIDATE_ARGS) uint32_t i = exec->shader_state_count++; if (i >= exec->shader_state_size) { - DRM_ERROR("More requests for shader states than declared\n"); + DRM_DEBUG("More requests for shader states than declared\n"); return -EINVAL; } @@ -332,7 +332,7 @@ validate_gl_shader_state(VALIDATE_ARGS) exec->shader_state[i].max_index = 0; if (exec->shader_state[i].addr & ~0xf) { - DRM_ERROR("high bits set in GL shader rec reference\n"); + DRM_DEBUG("high bits set in GL shader rec reference\n"); return -EINVAL; } @@ -356,7 +356,7 @@ validate_tile_binning_config(VALIDATE_ARGS) int bin_slot; if (exec->found_tile_binning_mode_config_packet) { - DRM_ERROR("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); + DRM_DEBUG("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n"); return -EINVAL; } exec->found_tile_binning_mode_config_packet = true; @@ -368,14 +368,14 @@ validate_tile_binning_config(VALIDATE_ARGS) if (exec->bin_tiles_x == 0 || exec->bin_tiles_y == 0) { - DRM_ERROR("Tile binning config of %dx%d too small\n", + DRM_DEBUG("Tile binning config of %dx%d too small\n", exec->bin_tiles_x, exec->bin_tiles_y); return -EINVAL; } if (flags & (VC4_BIN_CONFIG_DB_NON_MS | VC4_BIN_CONFIG_TILE_BUFFER_64BIT)) { - DRM_ERROR("unsupported binning config flags 0x%02x\n", flags); + DRM_DEBUG("unsupported binning config flags 0x%02x\n", flags); return -EINVAL; } @@ -493,20 +493,20 @@ vc4_validate_bin_cl(struct drm_device *dev, const struct cmd_info *info; if (cmd >= ARRAY_SIZE(cmd_info)) { - DRM_ERROR("0x%08x: packet %d out of bounds\n", + DRM_DEBUG("0x%08x: packet %d out of bounds\n", src_offset, cmd); return -EINVAL; } info = &cmd_info[cmd]; if (!info->name) { - DRM_ERROR("0x%08x: packet %d invalid\n", + DRM_DEBUG("0x%08x: packet %d invalid\n", src_offset, cmd); return -EINVAL; } if (src_offset + info->len > len) { - DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x " + DRM_DEBUG("0x%08x: packet %d (%s) length 0x%08x " "exceeds bounds (0x%08x)\n", src_offset, cmd, info->name, info->len, src_offset + len); @@ -519,7 +519,7 @@ vc4_validate_bin_cl(struct drm_device *dev, if (info->func && info->func(exec, dst_pkt + 1, src_pkt + 1)) { - DRM_ERROR("0x%08x: packet %d (%s) failed to validate\n", + DRM_DEBUG("0x%08x: packet %d (%s) failed to validate\n", src_offset, cmd, info->name); return -EINVAL; } @@ -537,7 +537,7 @@ vc4_validate_bin_cl(struct drm_device *dev, exec->ct0ea = exec->ct0ca + dst_offset; if (!exec->found_start_tile_binning_packet) { - DRM_ERROR("Bin CL missing VC4_PACKET_START_TILE_BINNING\n"); + DRM_DEBUG("Bin CL missing VC4_PACKET_START_TILE_BINNING\n"); return -EINVAL; } @@ -549,7 +549,7 @@ vc4_validate_bin_cl(struct drm_device *dev, * semaphore increment. */ if (!exec->found_increment_semaphore_packet || !exec->found_flush) { - DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + " + DRM_DEBUG("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + " "VC4_PACKET_FLUSH\n"); return -EINVAL; } @@ -588,11 +588,11 @@ reloc_tex(struct vc4_exec_info *exec, uint32_t remaining_size = tex->base.size - p0; if (p0 > tex->base.size - 4) { - DRM_ERROR("UBO offset greater than UBO size\n"); + DRM_DEBUG("UBO offset greater than UBO size\n"); goto fail; } if (p1 > remaining_size - 4) { - DRM_ERROR("UBO clamp would allow reads " + DRM_DEBUG("UBO clamp would allow reads " "outside of UBO\n"); goto fail; } @@ -612,14 +612,14 @@ reloc_tex(struct vc4_exec_info *exec, if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) == VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE) { if (cube_map_stride) { - DRM_ERROR("Cube map stride set twice\n"); + DRM_DEBUG("Cube map stride set twice\n"); goto fail; } cube_map_stride = p3 & VC4_TEX_P2_CMST_MASK; } if (!cube_map_stride) { - DRM_ERROR("Cube map stride not set\n"); + DRM_DEBUG("Cube map stride not set\n"); goto fail; } } @@ -660,7 +660,7 @@ reloc_tex(struct vc4_exec_info *exec, case VC4_TEXTURE_TYPE_RGBA64: case VC4_TEXTURE_TYPE_YUV422R: default: - DRM_ERROR("Texture format %d unsupported\n", type); + DRM_DEBUG("Texture format %d unsupported\n", type); goto fail; } utile_w = utile_width(cpp); @@ -713,7 +713,7 @@ reloc_tex(struct vc4_exec_info *exec, level_size = aligned_width * cpp * aligned_height; if (offset < level_size) { - DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db " + DRM_DEBUG("Level %d (%dx%d -> %dx%d) size %db " "overflowed buffer bounds (offset %d)\n", i, level_width, level_height, aligned_width, aligned_height, @@ -764,7 +764,7 @@ validate_gl_shader_rec(struct drm_device *dev, nr_relocs = ARRAY_SIZE(shader_reloc_offsets) + nr_attributes; if (nr_relocs * 4 > exec->shader_rec_size) { - DRM_ERROR("overflowed shader recs reading %d handles " + DRM_DEBUG("overflowed shader recs reading %d handles " "from %d bytes left\n", nr_relocs, exec->shader_rec_size); return -EINVAL; @@ -774,7 +774,7 @@ validate_gl_shader_rec(struct drm_device *dev, exec->shader_rec_size -= nr_relocs * 4; if (packet_size > exec->shader_rec_size) { - DRM_ERROR("overflowed shader recs copying %db packet " + DRM_DEBUG("overflowed shader recs copying %db packet " "from %d bytes left\n", packet_size, exec->shader_rec_size); return -EINVAL; @@ -794,7 +794,7 @@ validate_gl_shader_rec(struct drm_device *dev, for (i = 0; i < shader_reloc_count; i++) { if (src_handles[i] > exec->bo_count) { - DRM_ERROR("Shader handle %d too big\n", src_handles[i]); + DRM_DEBUG("Shader handle %d too big\n", src_handles[i]); return -EINVAL; } @@ -810,13 +810,13 @@ validate_gl_shader_rec(struct drm_device *dev, if (((*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD) == 0) != to_vc4_bo(&bo[0]->base)->validated_shader->is_threaded) { - DRM_ERROR("Thread mode of CL and FS do not match\n"); + DRM_DEBUG("Thread mode of CL and FS do not match\n"); return -EINVAL; } if (to_vc4_bo(&bo[1]->base)->validated_shader->is_threaded || to_vc4_bo(&bo[2]->base)->validated_shader->is_threaded) { - DRM_ERROR("cs and vs cannot be threaded\n"); + DRM_DEBUG("cs and vs cannot be threaded\n"); return -EINVAL; } @@ -831,7 +831,7 @@ validate_gl_shader_rec(struct drm_device *dev, *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset; if (src_offset != 0) { - DRM_ERROR("Shaders must be at offset 0 of " + DRM_DEBUG("Shaders must be at offset 0 of " "the BO.\n"); return -EINVAL; } @@ -842,7 +842,7 @@ validate_gl_shader_rec(struct drm_device *dev, if (validated_shader->uniforms_src_size > exec->uniforms_size) { - DRM_ERROR("Uniforms src buffer overflow\n"); + DRM_DEBUG("Uniforms src buffer overflow\n"); return -EINVAL; } @@ -900,7 +900,7 @@ validate_gl_shader_rec(struct drm_device *dev, if (vbo->base.size < offset || vbo->base.size - offset < attr_size) { - DRM_ERROR("BO offset overflow (%d + %d > %zu)\n", + DRM_DEBUG("BO offset overflow (%d + %d > %zu)\n", offset, attr_size, vbo->base.size); return -EINVAL; } @@ -909,7 +909,7 @@ validate_gl_shader_rec(struct drm_device *dev, max_index = ((vbo->base.size - offset - attr_size) / stride); if (state->max_index > max_index) { - DRM_ERROR("primitives use index %d out of " + DRM_DEBUG("primitives use index %d out of " "supplied %d\n", state->max_index, max_index); return -EINVAL; diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c index 0b2df5c6efb4..d3f15bf60900 100644 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c @@ -200,7 +200,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader, uint32_t clamp_reg, clamp_offset; if (sig == QPU_SIG_SMALL_IMM) { - DRM_ERROR("direct TMU read used small immediate\n"); + DRM_DEBUG("direct TMU read used small immediate\n"); return false; } @@ -209,7 +209,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader, */ if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) { - DRM_ERROR("direct TMU load wasn't an add\n"); + DRM_DEBUG("direct TMU load wasn't an add\n"); return false; } @@ -220,13 +220,13 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader, */ clamp_reg = raddr_add_a_to_live_reg_index(inst); if (clamp_reg == ~0) { - DRM_ERROR("direct TMU load wasn't clamped\n"); + DRM_DEBUG("direct TMU load wasn't clamped\n"); return false; } clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg]; if (clamp_offset == ~0) { - DRM_ERROR("direct TMU load wasn't clamped\n"); + DRM_DEBUG("direct TMU load wasn't clamped\n"); return false; } @@ -238,7 +238,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader, if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) && !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) { - DRM_ERROR("direct TMU load didn't add to a uniform\n"); + DRM_DEBUG("direct TMU load didn't add to a uniform\n"); return false; } @@ -246,14 +246,14 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader, } else { if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM && raddr_b == QPU_R_UNIF)) { - DRM_ERROR("uniform read in the same instruction as " + DRM_DEBUG("uniform read in the same instruction as " "texture setup.\n"); return false; } } if (validation_state->tmu_write_count[tmu] >= 4) { - DRM_ERROR("TMU%d got too many parameters before dispatch\n", + DRM_DEBUG("TMU%d got too many parameters before dispatch\n", tmu); return false; } @@ -265,7 +265,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader, */ if (!is_direct) { if (validation_state->needs_uniform_address_update) { - DRM_ERROR("Texturing with undefined uniform address\n"); + DRM_DEBUG("Texturing with undefined uniform address\n"); return false; } @@ -336,35 +336,35 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade case QPU_SIG_LOAD_TMU1: break; default: - DRM_ERROR("uniforms address change must be " + DRM_DEBUG("uniforms address change must be " "normal math\n"); return false; } if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) { - DRM_ERROR("Uniform address reset must be an ADD.\n"); + DRM_DEBUG("Uniform address reset must be an ADD.\n"); return false; } if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) { - DRM_ERROR("Uniform address reset must be unconditional.\n"); + DRM_DEBUG("Uniform address reset must be unconditional.\n"); return false; } if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP && !(inst & QPU_PM)) { - DRM_ERROR("No packing allowed on uniforms reset\n"); + DRM_DEBUG("No packing allowed on uniforms reset\n"); return false; } if (add_lri == -1) { - DRM_ERROR("First argument of uniform address write must be " + DRM_DEBUG("First argument of uniform address write must be " "an immediate value.\n"); return false; } if (validation_state->live_immediates[add_lri] != expected_offset) { - DRM_ERROR("Resetting uniforms with offset %db instead of %db\n", + DRM_DEBUG("Resetting uniforms with offset %db instead of %db\n", validation_state->live_immediates[add_lri], expected_offset); return false; @@ -372,7 +372,7 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) && !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) { - DRM_ERROR("Second argument of uniform address write must be " + DRM_DEBUG("Second argument of uniform address write must be " "a uniform.\n"); return false; } @@ -417,7 +417,7 @@ check_reg_write(struct vc4_validated_shader_info *validated_shader, switch (waddr) { case QPU_W_UNIFORMS_ADDRESS: if (is_b) { - DRM_ERROR("relative uniforms address change " + DRM_DEBUG("relative uniforms address change " "unsupported\n"); return false; } @@ -452,11 +452,11 @@ check_reg_write(struct vc4_validated_shader_info *validated_shader, /* XXX: I haven't thought about these, so don't support them * for now. */ - DRM_ERROR("Unsupported waddr %d\n", waddr); + DRM_DEBUG("Unsupported waddr %d\n", waddr); return false; case QPU_W_VPM_ADDR: - DRM_ERROR("General VPM DMA unsupported\n"); + DRM_DEBUG("General VPM DMA unsupported\n"); return false; case QPU_W_VPM: @@ -559,7 +559,7 @@ check_instruction_writes(struct vc4_validated_shader_info *validated_shader, bool ok; if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) { - DRM_ERROR("ADD and MUL both set up textures\n"); + DRM_DEBUG("ADD and MUL both set up textures\n"); return false; } @@ -588,7 +588,7 @@ check_branch(uint64_t inst, * there's no need for it. */ if (waddr_add != QPU_W_NOP || waddr_mul != QPU_W_NOP) { - DRM_ERROR("branch instruction at %d wrote a register.\n", + DRM_DEBUG("branch instruction at %d wrote a register.\n", validation_state->ip); return false; } @@ -614,7 +614,7 @@ check_instruction_reads(struct vc4_validated_shader_info *validated_shader, validated_shader->uniforms_size += 4; if (validation_state->needs_uniform_address_update) { - DRM_ERROR("Uniform read with undefined uniform " + DRM_DEBUG("Uniform read with undefined uniform " "address\n"); return false; } @@ -660,19 +660,19 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state) continue; if (ip - last_branch < 4) { - DRM_ERROR("Branch at %d during delay slots\n", ip); + DRM_DEBUG("Branch at %d during delay slots\n", ip); return false; } last_branch = ip; if (inst & QPU_BRANCH_REG) { - DRM_ERROR("branching from register relative " + DRM_DEBUG("branching from register relative " "not supported\n"); return false; } if (!(inst & QPU_BRANCH_REL)) { - DRM_ERROR("relative branching required\n"); + DRM_DEBUG("relative branching required\n"); return false; } @@ -682,13 +682,13 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state) * end of the shader object. */ if (branch_imm % sizeof(inst) != 0) { - DRM_ERROR("branch target not aligned\n"); + DRM_DEBUG("branch target not aligned\n"); return false; } branch_target_ip = after_delay_ip + (branch_imm >> 3); if (branch_target_ip >= validation_state->max_ip) { - DRM_ERROR("Branch at %d outside of shader (ip %d/%d)\n", + DRM_DEBUG("Branch at %d outside of shader (ip %d/%d)\n", ip, branch_target_ip, validation_state->max_ip); return false; @@ -699,7 +699,7 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state) * the shader. */ if (after_delay_ip >= validation_state->max_ip) { - DRM_ERROR("Branch at %d continues past shader end " + DRM_DEBUG("Branch at %d continues past shader end " "(%d/%d)\n", ip, after_delay_ip, validation_state->max_ip); return false; @@ -709,7 +709,7 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state) } if (max_branch_target > validation_state->max_ip - 3) { - DRM_ERROR("Branch landed after QPU_SIG_PROG_END"); + DRM_DEBUG("Branch landed after QPU_SIG_PROG_END"); return false; } @@ -750,7 +750,7 @@ vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state) return true; if (texturing_in_progress(validation_state)) { - DRM_ERROR("Branch target landed during TMU setup\n"); + DRM_DEBUG("Branch target landed during TMU setup\n"); return false; } @@ -837,7 +837,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) case QPU_SIG_LAST_THREAD_SWITCH: if (!check_instruction_writes(validated_shader, &validation_state)) { - DRM_ERROR("Bad write at ip %d\n", ip); + DRM_DEBUG("Bad write at ip %d\n", ip); goto fail; } @@ -855,7 +855,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) validated_shader->is_threaded = true; if (ip < last_thread_switch_ip + 3) { - DRM_ERROR("Thread switch too soon after " + DRM_DEBUG("Thread switch too soon after " "last switch at ip %d\n", ip); goto fail; } @@ -867,7 +867,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) case QPU_SIG_LOAD_IMM: if (!check_instruction_writes(validated_shader, &validation_state)) { - DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip); + DRM_DEBUG("Bad LOAD_IMM write at ip %d\n", ip); goto fail; } break; @@ -878,14 +878,14 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) goto fail; if (ip < last_thread_switch_ip + 3) { - DRM_ERROR("Branch in thread switch at ip %d", + DRM_DEBUG("Branch in thread switch at ip %d", ip); goto fail; } break; default: - DRM_ERROR("Unsupported QPU signal %d at " + DRM_DEBUG("Unsupported QPU signal %d at " "instruction %d\n", sig, ip); goto fail; } @@ -898,7 +898,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) } if (ip == validation_state.max_ip) { - DRM_ERROR("shader failed to terminate before " + DRM_DEBUG("shader failed to terminate before " "shader BO end at %zd\n", shader_obj->base.size); goto fail; @@ -907,7 +907,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj) /* Might corrupt other thread */ if (validated_shader->is_threaded && validation_state.all_registers_used) { - DRM_ERROR("Shader uses threading, but uses the upper " + DRM_DEBUG("Shader uses threading, but uses the upper " "half of the registers, too\n"); goto fail; } diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c index 12289673f457..2524ff116f00 100644 --- a/drivers/gpu/drm/vgem/vgem_drv.c +++ b/drivers/gpu/drm/vgem/vgem_drv.c @@ -190,7 +190,7 @@ static struct drm_gem_object *vgem_gem_create(struct drm_device *dev, return ERR_CAST(obj); ret = drm_gem_handle_create(file, &obj->base, handle); - drm_gem_object_unreference_unlocked(&obj->base); + drm_gem_object_put_unlocked(&obj->base); if (ret) goto err; @@ -245,7 +245,7 @@ static int vgem_gem_dumb_map(struct drm_file *file, struct drm_device *dev, *offset = drm_vma_node_offset_addr(&obj->vma_node); unref: - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/vgem/vgem_fence.c b/drivers/gpu/drm/vgem/vgem_fence.c index 3109c8308eb5..8fd52f211e9d 100644 --- a/drivers/gpu/drm/vgem/vgem_fence.c +++ b/drivers/gpu/drm/vgem/vgem_fence.c @@ -213,7 +213,7 @@ err_fence: dma_fence_put(fence); } err: - drm_gem_object_unreference_unlocked(obj); + drm_gem_object_put_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.c b/drivers/gpu/drm/virtio/virtgpu_drv.c index 63d35c7e416c..49a3d8d5a249 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.c +++ b/drivers/gpu/drm/virtio/virtgpu_drv.c @@ -122,7 +122,6 @@ static struct drm_driver driver = { .dumb_create = virtio_gpu_mode_dumb_create, .dumb_map_offset = virtio_gpu_mode_dumb_mmap, - .dumb_destroy = virtio_gpu_mode_dumb_destroy, #if defined(CONFIG_DEBUG_FS) .debugfs_init = virtio_gpu_debugfs_init, diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index 3a66abb8fd50..da2fb585fea4 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -236,9 +236,6 @@ struct virtio_gpu_object *virtio_gpu_alloc_object(struct drm_device *dev, int virtio_gpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args); -int virtio_gpu_mode_dumb_destroy(struct drm_file *file_priv, - struct drm_device *dev, - uint32_t handle); int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, struct drm_device *dev, uint32_t handle, uint64_t *offset_p); diff --git a/drivers/gpu/drm/virtio/virtgpu_fb.c b/drivers/gpu/drm/virtio/virtgpu_fb.c index 046e28b69d99..15d18fd0c64b 100644 --- a/drivers/gpu/drm/virtio/virtgpu_fb.c +++ b/drivers/gpu/drm/virtio/virtgpu_fb.c @@ -308,7 +308,7 @@ static int virtio_gpu_fbdev_destroy(struct drm_device *dev, return 0; } -static struct drm_fb_helper_funcs virtio_gpu_fb_helper_funcs = { +static const struct drm_fb_helper_funcs virtio_gpu_fb_helper_funcs = { .fb_probe = virtio_gpufb_create, }; diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c b/drivers/gpu/drm/virtio/virtgpu_gem.c index cc025d8fbe19..72ad7b103448 100644 --- a/drivers/gpu/drm/virtio/virtgpu_gem.c +++ b/drivers/gpu/drm/virtio/virtgpu_gem.c @@ -118,13 +118,6 @@ fail: return ret; } -int virtio_gpu_mode_dumb_destroy(struct drm_file *file_priv, - struct drm_device *dev, - uint32_t handle) -{ - return drm_gem_handle_delete(file_priv, handle); -} - int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, struct drm_device *dev, uint32_t handle, uint64_t *offset_p) diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c index e695d74eaa9f..cd389c5eaef5 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ttm.c +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -192,7 +192,7 @@ static int ttm_bo_man_takedown(struct ttm_mem_type_manager *man) } static void ttm_bo_man_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c b/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c index d2b03d4a3c86..f2f9d88131f2 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c @@ -157,9 +157,9 @@ static int vmw_gmrid_man_takedown(struct ttm_mem_type_manager *man) } static void vmw_gmrid_man_debug(struct ttm_mem_type_manager *man, - const char *prefix) + struct drm_printer *printer) { - pr_info("%s: No debug info available for the GMR id manager\n", prefix); + drm_printf(printer, "No debug info available for the GMR id manager\n"); } const struct ttm_mem_type_manager_func vmw_gmrid_manager_func = { diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c index 7ece0e9058c6..f9cde03030fd 100644 --- a/drivers/gpu/host1x/bus.c +++ b/drivers/gpu/host1x/bus.c @@ -44,9 +44,12 @@ struct host1x_subdev { * @np: device node */ static int host1x_subdev_add(struct host1x_device *device, + struct host1x_driver *driver, struct device_node *np) { struct host1x_subdev *subdev; + struct device_node *child; + int err; subdev = kzalloc(sizeof(*subdev), GFP_KERNEL); if (!subdev) @@ -59,6 +62,19 @@ static int host1x_subdev_add(struct host1x_device *device, list_add_tail(&subdev->list, &device->subdevs); mutex_unlock(&device->subdevs_lock); + /* recursively add children */ + for_each_child_of_node(np, child) { + if (of_match_node(driver->subdevs, child) && + of_device_is_available(child)) { + err = host1x_subdev_add(device, driver, child); + if (err < 0) { + /* XXX cleanup? */ + of_node_put(child); + return err; + } + } + } + return 0; } @@ -87,7 +103,7 @@ static int host1x_device_parse_dt(struct host1x_device *device, for_each_child_of_node(device->dev.parent->of_node, np) { if (of_match_node(driver->subdevs, np) && of_device_is_available(np)) { - err = host1x_subdev_add(device, np); + err = host1x_subdev_add(device, driver, np); if (err < 0) { of_node_put(np); return err; diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index 778272514164..7f22c5c37660 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -134,8 +134,8 @@ static int host1x_probe(struct platform_device *pdev) syncpt_irq = platform_get_irq(pdev, 0); if (syncpt_irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ\n"); - return -ENXIO; + dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); + return syncpt_irq; } host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); diff --git a/drivers/gpu/host1x/hw/intr_hw.c b/drivers/gpu/host1x/hw/intr_hw.c index dacb8009a605..37ebb51703fa 100644 --- a/drivers/gpu/host1x/hw/intr_hw.c +++ b/drivers/gpu/host1x/hw/intr_hw.c @@ -33,10 +33,10 @@ static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt) unsigned int id = syncpt->id; struct host1x *host = syncpt->host; - host1x_sync_writel(host, BIT_MASK(id), - HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id))); - host1x_sync_writel(host, BIT_MASK(id), - HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id))); + host1x_sync_writel(host, BIT(id % 32), + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32)); + host1x_sync_writel(host, BIT(id % 32), + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32)); schedule_work(&syncpt->intr.work); } @@ -50,9 +50,9 @@ static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id) for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) { reg = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); - for_each_set_bit(id, ®, BITS_PER_LONG) { + for_each_set_bit(id, ®, 32) { struct host1x_syncpt *syncpt = - host->syncpt + (i * BITS_PER_LONG + id); + host->syncpt + (i * 32 + id); host1x_intr_syncpt_handle(syncpt); } } @@ -117,17 +117,17 @@ static void _host1x_intr_set_syncpt_threshold(struct host1x *host, static void _host1x_intr_enable_syncpt_intr(struct host1x *host, unsigned int id) { - host1x_sync_writel(host, BIT_MASK(id), - HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(BIT_WORD(id))); + host1x_sync_writel(host, BIT(id % 32), + HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id / 32)); } static void _host1x_intr_disable_syncpt_intr(struct host1x *host, unsigned int id) { - host1x_sync_writel(host, BIT_MASK(id), - HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(BIT_WORD(id))); - host1x_sync_writel(host, BIT_MASK(id), - HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(BIT_WORD(id))); + host1x_sync_writel(host, BIT(id % 32), + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32)); + host1x_sync_writel(host, BIT(id % 32), + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32)); } static int _host1x_free_syncpt_irq(struct host1x *host) diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c index c93f74fcce72..7b0270d60742 100644 --- a/drivers/gpu/host1x/hw/syncpt_hw.c +++ b/drivers/gpu/host1x/hw/syncpt_hw.c @@ -89,7 +89,7 @@ static int syncpt_cpu_incr(struct host1x_syncpt *sp) host1x_syncpt_idle(sp)) return -EINVAL; - host1x_sync_writel(host, BIT_MASK(sp->id), + host1x_sync_writel(host, BIT(sp->id % 32), HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset)); wmb(); diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c index bee504406cfc..db509ab8874e 100644 --- a/drivers/gpu/host1x/job.c +++ b/drivers/gpu/host1x/job.c @@ -197,10 +197,6 @@ static unsigned int pin_job(struct host1x *host, struct host1x_job *job) } phys_addr = host1x_bo_pin(reloc->target.bo, &sgt); - if (!phys_addr) { - err = -EINVAL; - goto unpin; - } job->addr_phys[job->num_unpins] = phys_addr; job->unpins[job->num_unpins].bo = reloc->target.bo; @@ -225,10 +221,6 @@ static unsigned int pin_job(struct host1x *host, struct host1x_job *job) } phys_addr = host1x_bo_pin(g->bo, &sgt); - if (!phys_addr) { - err = -EINVAL; - goto unpin; - } if (!IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL) && host->domain) { for_each_sg(sgt->sgl, sg, sgt->nents, j) |