| Commit message (Collapse) | Author | Age |
|---|
| |
|
|
|
|
|
| |
This adds SPDX GPL-2.0 header to the Trace Hub driver and removes the
GPLv2 boilerplate text.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
| |
|
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Lewisburg PCH.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
| |
|
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Cedar Fork PCH.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
On some devices (TH 2.x devices at the moment), the internal time counter
is initially not synchronized to the global crystal clock, so the time
stamps it produces will not be useful. In this case, the driver needs
to force the time counter resync.
This applies the workaround to relevant devices.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
| |
|
|
|
|
| |
Allow attaching miscellaneous quirk information to devices as drvdata.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
| |
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-LP.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
|
| |
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-H.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
|
| |
|
|
|
|
|
| |
The driver forgets to enable bus mastering for the PCI device.
Fix this.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
| |
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Gemini Lake SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
| |
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Denverton SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
| |
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Kaby Lake PCH-H.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: <stable@vger.kernel.org>
|
| |
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Broxton-M SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Reviewed-by: Laurent Fert <laurent.fert@intel.com>
|
| |
|
|
|
|
|
|
|
|
|
| |
Already during the subdevice initialization time, devices will need
to reference Intel TH controller descriptor structure.
This patch moves setting the drvdata from the pci glue to intel_th
core, before subdevices are populated.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
| |
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Broxton SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
| |
|
|
|
|
|
| |
This adds Intel(R) Trace Hub PCI ID for Apollo Lake SOC.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
|
This patch adds basic support for PCI-based Intel TH devices. It requests
2 bars (configuration registers for the subdevices and STH channel MMIO
region) and calls into Intel TH core code to create the bus with subdevices
etc.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
