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path: root/drivers/pci/dwc
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| * | | PCI: hisi: Remove unused variable driverShawn Lin2017-08-03
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The local "driver" variable was unused and caused a warning, so remove it: drivers/pci/dwc/pcie-hisi.c: In function 'hisi_pcie_probe': drivers/pci/dwc/pcie-hisi.c:271:24: warning: variable 'driver' set but not used [-Wunused-but-set-variable] Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Zhou Wang <wangzhou1@hisilicon.com> Acked-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
* | | Merge branch 'pci/host-exynos' into nextBjorn Helgaas2017-09-07
|\ \ \ | | | | | | | | | | | | | | | | * pci/host-exynos: PCI: exynos: Fix platform_get_irq() error handling
| * | | PCI: exynos: Fix platform_get_irq() error handlingFabio Estevam2017-09-05
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Reported-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
* | | Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas2017-09-07
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-dra7xx: PCI: dra7xx: Fix platform_get_irq() error handling PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe() PCI: dra7xx: Use PCI_NUM_INTX
| * | | PCI: dra7xx: Fix platform_get_irq() error handlingFabio Estevam2017-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | | PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe()Gustavo A. R. Silva2017-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platform_get_irq() returns an error code, but the pci-dra7xx driver ignores it and always returns -EINVAL. This is not correct and prevents -EPROBE_DEFER from being propagated properly. Print and propagate the return value of platform_get_irq() on failure. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | | PCI: dra7xx: Use PCI_NUM_INTXBjorn Helgaas2017-08-16
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Based-on-similar-patches-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Kishon Vijay Abraham I <kishon@ti.com>
* | | Merge branch 'pci/host-designware' into nextBjorn Helgaas2017-09-07
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | * pci/host-designware: PCI: dwc: Clear MSI interrupt status after it is handled, not before PCI: qcom: Allow ->post_init() to fail PCI: qcom: Don't unroll init if ->init() fails PCI: dwc: designware: Handle ->host_init() failures PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static
| * | PCI: dwc: Clear MSI interrupt status after it is handled, not beforeFaiz Abbas2017-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the interrupt status is cleared before it is handled, it is possible that another interrupt will trigger while servicing the previous one. This is causing timeouts in some wireless lan cards which use PCIe. Clear MSI interrupt status after it gets serviced instead of before calling generic_handler. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Joao Pinto <jpinto@synopsys.com>
| * | PCI: qcom: Allow ->post_init() to failBjorn Andersson2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | host_init() should detect and propagate errors from post_init(). In addition, by acknowledging that post_init() can fail we must disable the post_init() resources in a step separate from the deinit, so that we don't try to disable the post_init() resources a second time. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: qcom: Don't unroll init if ->init() failsBjorn Andersson2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | When the init op fails it will restore the state of the resources, so we should not disable them one more time when this happens. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: dwc: designware: Handle ->host_init() failuresBjorn Andersson2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In several dwc-based drivers, ->host_init() can fail, so make sure to propagate and handle this to avoid continuing operation of a driver or hardware in an invalid state. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
| * | PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specificallyJisheng Zhang2017-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ATU CTRL2 register is 32 bits, and bits other than the enable bit may be set. To check whether the ATU is enabled or not, we should test the enable bit specifically. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
| * | PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() staticCarlos Palminha2017-08-02
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Helper functions dw_pcie_prog_*_atu_unroll() don't need to be in global scope, so make them static. Cleans up sparse warnings: - symbol 'dw_pcie_prog_outbound_atu_unroll' was not declared. Should it be static? - symbol 'dw_pcie_prog_inbound_atu_unroll' was not declared. Should it be static? Signed-off-by: Carlos Palminha <palminha@synopsys.com> [bhelgaas: rewrap to fit in 80 columns] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
* | Merge branch 'pci/host-artpec6' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | * pci/host-artpec6: PCI: artpec6: Fix platform_get_irq() error handling
| * | PCI: artpec6: Fix platform_get_irq() error handlingFabio Estevam2017-09-05
| |/ | | | | | | | | | | | | | | | | platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com>
* | PCI: armada8k: Fix platform_get_irq() error handlingFabio Estevam2017-09-05
| | | | | | | | | | | | | | | | | | platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* | PCI: armada8k: Check the return value from clk_prepare_enable()Fabio Estevam2017-08-03
|/ | | | | | | | clk_prepare_enable() may fail, so check its return value and propagate it in the case of error. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Merge branch 'pci/host-qcom' into nextBjorn Helgaas2017-07-04
|\ | | | | | | | | | | | | | | * pci/host-qcom: PCI: qcom: Limit TLP size to 2K to work around hardware issue PCI: qcom: Fix spelling mistake: "asser" -> "assert" PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc PCI: qcom: Add support for IPQ4019 PCIe controller
| * PCI: qcom: Limit TLP size to 2K to work around hardware issueSrinivas Kandagatla2017-07-02
| | | | | | | | | | | | | | | | | | | | | | | | Limit TLP size to 2K to work around a hardware bug in the v0 version of PCIe IP. When using default TLP size of 4K, the internal buffer gets corrupted due to this hardware bug. This bug was originally noticed during ssh session between APQ8064-based board and PC. Network packets got corrupted randomly and terminated the ssh session due to this bug. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: qcom: Fix spelling mistake: "asser" -> "assert"Colin Ian King2017-07-02
| | | | | | | | | | | | Trivial fix to spelling mistake in dev_err message. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: qcom: Reorder to put v0 functions together, v1 functions together, etcBjorn Helgaas2017-07-02
| | | | | | | | | | | | Previously the v0, v1, and v2 functions were not grouped together in a consistent order. Reorder them to make them consistent. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: qcom: Add support for IPQ4019 PCIe controllerJohn Crispin2017-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the IPQ4019 PCIe controller. IPQ4019 supports Gen 1/2, one lane, one PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the same as for the MSM8996, however the clocks and reset lines differ. [bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile issues] Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Rob Herring <robh@kernel.org> # binding
* | Merge branch 'pci/host-kirin' into nextBjorn Helgaas2017-07-04
|\ \ | | | | | | | | | | | | * pci/host-kirin: PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driver
| * | PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driverXiaowei Song2017-07-02
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hisilicon PCIe driver shares the common functions for PCIe dw-host. The poweron functions are developed on hi3660 SoC, while other functions are common for Kirin series SoCs. Low power mode (L1 sub-state and Suspend/Resume), hotplug and MSI feature are not supported currently. Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/20170704021516.96575-1-songxiaowei@hisilicon.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Cc: Guodong Xu <guodong.xu@linaro.org>
* | Merge branch 'pci/host-imx6' into nextBjorn Helgaas2017-07-03
|\ \ | | | | | | | | | | | | * pci/host-imx6: PCI: imx6: Add regulator support
| * | PCI: imx6: Add regulator supportQuentin Schulz2017-07-02
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards might require to control a regulator to power the PCIe port. Add support for an optional regulator defined in Device Tree linked in the PCIe controller under `vpcie-supply`. If present, the regulator will be disabled and then enabled as part of the PCIe host initialization process and will be disabled when shutting down. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> [bhelgaas: use dev_err() instead of pr_err() in imx6_pcie_assert_core_reset()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
* | Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas2017-07-03
|\ \ | | | | | | | | | | | | | | | * pci/host-dra7xx: PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
| * | PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAINArvind Yadav2017-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we tried to clear interrupt requests by clearing bits in the PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN registers. But per the TRM, these fields are RW1C, so we must *set* bits to clear the interrupt bits. Fixes: 47ff3de911a7 ("PCI: dra7xx: Add TI DRA7xx PCIe driver") Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: dwc: dra7xx: Depend on appropriate SoC or compile testPeter Robinson2017-07-02
| |/ | | | | | | | | | | | | | | | | The PCI controller attached to a SoC isn't much use if the core SoC isn't enabled, unless of course it's compile testing, so add appropriate dependency. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
* | Merge branch 'pci/host-designware' into nextBjorn Helgaas2017-07-03
|\ \ | | | | | | | | | | | | | | | * pci/host-designware: PCI: dwc: Constify dw_pcie_host_ops structures PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD
| * | PCI: dwc: Constify dw_pcie_host_ops structuresJisheng Zhang2017-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | The dw_pcie_host_ops structures are never modified. Constify these structures such that these can be write-protected. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREADJisheng Zhang2017-07-02
| |/ | | | | | | | | | | | | | | | | | | Similar as commit 8ff0ef996ca0 ("PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD"), we should mark PCIe/PCI (MSI) IRQ cascade handlers in designware, qcom, and vmd as IRQF_NO_THREAD explicitly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> # vmd Acked-by: Jingoo Han <jingoohan1@gmail.com> # pcie-designware-plat.c
* | Merge branch 'pci/irq-fixups' into nextBjorn Helgaas2017-07-03
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/irq-fixups: arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq() PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions PCI: altera: Drop pci_fixup_irqs() PCI: versatile: Drop pci_fixup_irqs() PCI: generic: Drop pci_fixup_irqs() PCI: faraday: Drop pci_fixup_irqs() PCI: designware: Drop pci_fixup_irqs() PCI: iproc: Drop pci_fixup_irqs() PCI: rcar: Drop pci_fixup_irqs() PCI: xilinx: Drop pci_fixup_irqs() PCI: tegra: Drop pci_fixup_irqs() ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers PCI: Add a call to pci_assign_irq() in pci_device_probe() OF/PCI: Update of_irq_parse_and_map_pci() comment PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it PCI: Add IRQ mapping function pointers to pci_host_bridge struct PCI: Build setup-irq.o on all arches PCI: Remove pci_scan_root_bus_msi() PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge() ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: Make pci_register_host_bridge() PCI core internal PCI: Add pci_scan_root_bus_bridge() interface PCI: tegra: Fix host bridge memory leakage PCI: faraday: Fix host bridge memory leakage PCI: Add devm_pci_alloc_host_bridge() interface PCI: Add pci_free_host_bridge() interface PCI: Initialize bridge release function at bridge allocation PCI: faraday: Convert IRQ masking to raw PCI config accessors PCI: iproc: Convert link check to raw PCI config accessors PCI: xilinx-nwl: Remove nwl_pcie_enable_msi() unused bus parameter
| * PCI: designware: Drop pci_fixup_irqs()Lorenzo Pieralisi2017-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI designware host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
| * PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi2017-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI designware host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
* | PCI: imx6: Fix config read timeout handlingLucas Stach2017-05-22
|/ | | | | | | | | | | | | | | | | | | Commit cc7b0d495589 ("PCI: designware: Update PCI config space remap function") made PCI configuration requests non-posted, which means we now get a synchronous abort when the CFG space read to probe for downstream devices times out. Synchronous aborts need to be handled differently from the async aborts we were getting before, in particular the PC needs to be advanced when resolving the abort. This is mostly a copy of what other PCI drivers do on ARM to handle those aborts. [bhelgaas: changelog, "Fixes"] Fixes: cc7b0d495589 ("PCI: designware: Update PCI config space remap function") Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Peter Senna Tschudin <peter.senna@collabora.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
* Merge tag 'pci-v4.12-changes' of ↵Linus Torvalds2017-05-08
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add framework for supporting PCIe devices in Endpoint mode (Kishon Vijay Abraham I) - use non-postable PCI config space mappings when possible (Lorenzo Pieralisi) - clean up and unify mmap of PCI BARs (David Woodhouse) - export and unify Function Level Reset support (Christoph Hellwig) - avoid FLR for Intel 82579 NICs (Sasha Neftin) - add pci_request_irq() and pci_free_irq() helpers (Christoph Hellwig) - short-circuit config access failures for disconnected devices (Keith Busch) - remove D3 sleep delay when possible (Adrian Hunter) - freeze PME scan before suspending devices (Lukas Wunner) - stop disabling MSI/MSI-X in pci_device_shutdown() (Prarit Bhargava) - disable boot interrupt quirk for ASUS M2N-LR (Stefan Assmann) - add arch-specific alignment control to improve device passthrough by avoiding multiple BARs in a page (Yongji Xie) - add sysfs sriov_drivers_autoprobe to control VF driver binding (Bodong Wang) - allow slots below PCI-to-PCIe "reverse bridges" (Bjorn Helgaas) - fix crashes when unbinding host controllers that don't support removal (Brian Norris) - add driver for MicroSemi Switchtec management interface (Logan Gunthorpe) - add driver for Faraday Technology FTPCI100 host bridge (Linus Walleij) - add i.MX7D support (Andrey Smirnov) - use generic MSI support for Aardvark (Thomas Petazzoni) - make Rockchip driver modular (Brian Norris) - advertise 128-byte Read Completion Boundary support for Rockchip (Shawn Lin) - advertise PCI_EXP_LNKSTA_SLC for Rockchip root port (Shawn Lin) - convert atomic_t to refcount_t in HV driver (Elena Reshetova) - add CPU IRQ affinity in HV driver (K. Y. Srinivasan) - fix PCI bus removal in HV driver (Long Li) - add support for ThunderX2 DMA alias topology (Jayachandran C) - add ThunderX pass2.x 2nd node MCFG quirk (Tomasz Nowicki) - add ITE 8893 bridge DMA alias quirk (Jarod Wilson) - restrict Cavium ACS quirk only to CN81xx/CN83xx/CN88xx devices (Manish Jaggi) * tag 'pci-v4.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (146 commits) PCI: Don't allow unbinding host controllers that aren't prepared ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP MAINTAINERS: Add PCI Endpoint maintainer Documentation: PCI: Add userguide for PCI endpoint test function tools: PCI: Add sample test script to invoke pcitest tools: PCI: Add a userspace tool to test PCI endpoint Documentation: misc-devices: Add Documentation for pci-endpoint-test driver misc: Add host side PCI driver for PCI test function device PCI: Add device IDs for DRA74x and DRA72x dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access PCI: dwc: dra7xx: Workaround for errata id i870 dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode PCI: dwc: dra7xx: Add EP mode support PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently dt-bindings: PCI: Add DT bindings for PCI designware EP mode PCI: dwc: designware: Add EP mode support Documentation: PCI: Add binding documentation for pci-test endpoint function ixgbe: Use pcie_flr() instead of duplicating it IB/hfi1: Use pcie_flr() instead of duplicating it PCI: imx6: Fix spelling mistake: "contol" -> "control" ...
| * PCI: Don't allow unbinding host controllers that aren't preparedBrian Norris2017-04-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many PCI host controller drivers aren't prepared to have their devices unbound from them forcefully (e.g., through /sys/.../<driver>/unbind), as they don't provide any driver .remove callback, where they'd detach the root bus, release resources, etc. Keeping the driver built in (i.e., not a loadable module) is not enough; and providing no .remove callback just means we don't do any teardown. To rule out the possibility of unbinding a device via sysfs, we need to set the ".suppress_bind_attrs" field. I found the suspect drivers via the following search: git grep -l platform_driver $(git grep -L -e '\.remove' -e suppress_bind_attrs drivers/pci/) Then I inspected them to ensure that (a) they set up a PCI bus in their probe() and (b) they don't have a remove() callback for undoing the setup Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * Merge branch 'pci/ioremap' into nextBjorn Helgaas2017-04-28
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/ioremap: PCI: versatile: Update PCI config space remap function PCI: keystone-dw: Update PCI config space remap function PCI: layerscape: Update PCI config space remap function PCI: hisi: Update PCI config space remap function PCI: tegra: Update PCI config space remap function PCI: xgene: Update PCI config space remap function PCI: armada8k: Update PCI config space remap function PCI: designware: Update PCI config space remap function PCI: iproc-platform: Update PCI config space remap function PCI: qcom: Update PCI config space remap function PCI: rockchip: Update PCI config space remap function PCI: spear13xx: Update PCI config space remap function PCI: xilinx-nwl: Update PCI config space remap function PCI: xilinx: Update PCI config space remap function PCI: ECAM: Map config region with pci_remap_cfgspace() PCI: Implement devm_pci_remap_cfgspace() devres: fix devm_ioremap_*() offset parameter kerneldoc description ARM: Implement pci_remap_cfgspace() interface ARM64: Implement pci_remap_cfgspace() interface linux/io.h: Add pci_remap_cfgspace() interface PCI: Remove __weak tag from pci_remap_iospace()
| | * PCI: keystone-dw: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
| | * PCI: layerscape: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Mingkai Hu <mingkai.hu@freescale.com> Cc: Minghuan Lian <minghuan.Lian@freescale.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
| | * PCI: hisi: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Zhou Wang <wangzhou1@hisilicon.com>
| | * PCI: armada8k: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
| | * PCI: designware: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
| | * PCI: qcom: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generates on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
| | * PCI: spear13xx: Update PCI config space remap functionLorenzo Pieralisi2017-04-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI configuration space should be mapped with a memory region type that generate on the CPU host bus non-posted write transations. Update the driver to use the devm_pci_remap_cfg* interface to make sure the correct memory mappings for PCI configuration space are used. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com>
| * | Merge branch 'pci/host-imx6' into nextBjorn Helgaas2017-04-28
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-imx6: PCI: imx6: Fix spelling mistake: "contol" -> "control" PCI: imx6: Do not switch speed if Gen2 is disabled PCI: imx6: Do not wait for speed change on i.MX7 PCI: imx6: Allow probe deferral by reset GPIO PCI: imx6: Add code to support i.MX7D
| | * | PCI: imx6: Fix spelling mistake: "contol" -> "control"Colin Ian King2017-04-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Trivial fix to spelling mistake in dev_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Richard Zhu <hongxing.Zhu@nxp.com>
| | * | PCI: imx6: Do not switch speed if Gen2 is disabledAndrey Smirnov2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Save a bit of time and avoid going through link speed change procedure in configuration where link max speed is limited to Gen1 in DT. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: yurovsky@gmail.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org
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