From 51279ef9f64cf7eb8b3f891a2b60fa1aa4938afc Mon Sep 17 00:00:00 2001 From: Sergej Sawazki Date: Sat, 16 Sep 2017 13:44:41 +0200 Subject: clk: si5351: Add DT property to enable PLL reset Add optional output clock DT property to enable PLL reset when a clock output is enabled. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Russell King Signed-off-by: Sergej Sawazki Signed-off-by: Stephen Boyd --- include/linux/platform_data/si5351.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/platform_data') diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index 818c5c6e203f..c71a2dd66143 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -86,6 +86,7 @@ enum si5351_disable_state { * @multisynth_src: multisynth source clock * @clkout_src: clkout source clock * @pll_master: if true, clkout can also change pll rate + * @pll_reset: if true, clkout can reset its pll * @drive: output drive strength * @rate: initial clkout rate, or default if 0 */ @@ -95,6 +96,7 @@ struct si5351_clkout_config { enum si5351_drive_strength drive; enum si5351_disable_state disable_state; bool pll_master; + bool pll_reset; unsigned long rate; }; -- cgit v1.2.1