diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-09-05 11:45:33 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-09-05 11:45:33 -0700 |
| commit | d16605c9128a498f9b8575b5c43be95c45dbcfab (patch) | |
| tree | 2df1db4222b7e942ca47517fa4f5ab07b9b31b6e | |
| parent | fe9e31383e9a271a9b404488704e00acd1747ee3 (diff) | |
| parent | ac059e2aa01dcbbd7e0b2609abbef5790486fafe (diff) | |
| download | linux-d16605c9128a498f9b8575b5c43be95c45dbcfab.tar.gz linux-d16605c9128a498f9b8575b5c43be95c45dbcfab.tar.xz | |
Merge tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the big bulk of pin control changes for the v4.14 kernel.
There are just a few bigger changes (new drivers mostly) and then a
lot of small patches all over the place.
Core changes:
- Decision to wrap the sleep mode of the Spreadtrum and in the future
others into a specially tagged state. The generic DT bindings and
the new Spreadtrum driver conforms to this. Others should be moved
over if possible.
New drivers:
- Spreadtrum SoCs especially the SC9860 SoC.
- Storlink/Cortina Gemini 3512 and 3516 SoCs.
New subdrivers:
- Intel Denverton subdriver.
- Intel Cannon Lake subdriver.
- Intel Lewisburg subdriver.
- Allwinner sunxi: R40 subdriver for A10.
- Socionext uniphier PXs3 subdriver.
- Rockchip RK3128 subdriver.
- Renesas SH-PFC R8A77995 subdriver.
Miscellaneous:
- Qualcomm APQ8064 can handle general purpose clock muxing.
- Mediatek MT7623 PCIe mux data fixed up.
- Intel GPIO IRQs are disabled during suspend.
- Several fixes and addtions to Renesas r8a7796.
- Qualcomm SPMI GPIO supports dtest route and LV/MV subtype.
- Input schmitt trigger support in Rockchip RV1108.
- Aspeed G4 and G5 USB host/device pin control control added.
- Qualcomm IPQ4019 has matured with a few missing pin groups and
control bits put in place.
- Lots of constification, this is the latest in cocinelle fixes"
* tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (147 commits)
Revert "pinctrl: sunxi: Don't enforce bias disable (for now)"
pinctrl: uniphier: fix members of rmii group for Pro4
pinctrl: Delete an error message
pinctrl: core: Delete an error message
pinctrl: intel: Read back TX buffer state
pinctrl: rockchip: Add rv1108 recalculated iomux support
pinctrl: intel: Decrease indentation in intel_gpio_set()
pinctrl: rza1: Remove suffix from gpiochip label
pinctrl: qcom: spmi-gpio: Correct power_source range check
pinctrl: freescale: make mxs_regs const
pinctrl: aspeed: Rework strap register write logic for the AST2500
pinctrl: rza1: off by one in rza1_parse_gpiochip()
pinctrl: qcom: General Purpose clocks for apq8064
pinctrl: sprd: Add Spreadtrum pin control driver
dt-bindings: pinctrl: Add DT bindings for Spreadtrum SC9860
pinctrl: Add sleep related state to indicate sleep related configs
pinctrl: mediatek: update PCIe mux data for MT7623
pinctrl: intel: Add Intel Lewisburg GPIO support
pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support
pinctrl: aspeed: Fix ast2500 strap register write logic
...
124 files changed, 13259 insertions, 3903 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt new file mode 100644 index 000000000000..61466c58faae --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt @@ -0,0 +1,59 @@ +Cortina Systems Gemini pin controller + +This pin controller is found in the Cortina Systems Gemini SoC family, +see further arm/gemini.txt. It is a purely group-based multiplexing pin +controller. + +The pin controller node must be a subnode of the system controller node. + +Required properties: +- compatible: "cortina,gemini-pinctrl" + +Subnodes of the pin controller contain pin control multiplexing set-up. +Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes. + +Example: + + +syscon { + compatible = "cortina,gemini-syscon"; + ... + pinctrl { + compatible = "cortina,gemini-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, + <&vcontrol_default_pins>; + + dram_default_pins: pinctrl-dram { + mux { + function = "dram"; + groups = "dramgrp"; + }; + }; + rtc_default_pins: pinctrl-rtc { + mux { + function = "rtc"; + groups = "rtcgrp"; + }; + }; + power_default_pins: pinctrl-power { + mux { + function = "power"; + groups = "powergrp"; + }; + }; + system_default_pins: pinctrl-system { + mux { + function = "system"; + groups = "systemgrp"; + }; + }; + (...) + uart_default_pins: pinctrl-uart { + mux { + function = "uart"; + groups = "uartrxtxgrp"; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt new file mode 100644 index 000000000000..44ad670ae11e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt @@ -0,0 +1,61 @@ +* Freescale i.MX7ULP IOMUX Controller + +i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 +ports and IOMUXC DDR for DDR interface. + +Note: +This binding doc is only for the IOMUXC1 support in A7 Domain and it only +supports generic pin config. + +Please also refer pinctrl-bindings.txt in this directory for generic pinctrl +binding. + +=== Pin Controller Node === + +Required properties: +- compatible: "fsl,imx7ulp-iomuxc1" +- reg: Should contain the base physical address and size of the iomuxc + registers. + +=== Pin Configuration Node === +- pinmux: One integers array, represents a group of pins mux setting. + The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on + a specific function. + + NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux + and config register as follows: + <mux_conf_reg input_reg mux_mode input_val> + + Refer to imx7ulp-pinfunc.h in in device tree source folder for all + available imx7ulp PIN_FUNC_ID. + +Optional Properties: +- drive-strength Integer. Controls Drive Strength + 0: Standard + 1: Hi Driver +- drive-push-pull Bool. Enable Pin Push-pull +- drive-open-drain Bool. Enable Pin Open-drian +- slew-rate: Integer. Controls Slew Rate + 0: Standard + 1: Slow +- bias-disable: Bool. Pull disabled +- bias-pull-down: Bool. Pull down on pin +- bias-pull-up: Bool. Pull up on pin + +Examples: +#include "imx7ulp-pinfunc.h" + +/* Pin Controller Node */ +iomuxc1: iomuxc@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + + /* Pin Configuration Node */ + pinctrl_lpuart4: lpuart4grp { + pinmux = < + IMX7ULP_PAD_PTC3__LPUART4_RX + IMX7ULP_PAD_PTC2__LPUART4_TX + >; + bias-pull-up; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt index ca01710ee29a..3b7266c7c438 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4 -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS -VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2 +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1 +USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 +WDTRST2 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: @@ -86,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9 SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0 SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 -TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2 +TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS +VGAVS VPI24 VPO WDTRST1 WDTRST2 Examples ======== diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index 62d0f33fa65e..4483cc31e531 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -268,6 +268,8 @@ output-enable - enable output on a pin without actively driving it (such as enabling an output buffer) output-low - set the pin to output mode with low level output-high - set the pin to output mode with high level +sleep-hardware-state - indicate this is sleep related state which will be programmed + into the registers for the sleep state. slew-rate - set the slew rate For example: diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 17631d0a9af7..37d744750579 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins. Required properties: - compatible: value should be one of the following. "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl. + "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl. "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt index a7bde64798c7..a752a4716486 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt @@ -46,7 +46,8 @@ Valid values for pins are: gpio0-gpio89 Valid values for function are: - cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4, + cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a, + gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt index cfb8500dd56b..93374f478b9e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt @@ -50,7 +50,11 @@ Valid values for qcom,pins are: Supports mux, bias and drive-strength Valid values for qcom,function are: -gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0 +aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0, +blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx, +jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11, +mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1, +smart2, smart3, tm, wifi0, wifi1 Example: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 8d893a874634..5b12c57e7f02 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -16,6 +16,7 @@ PMIC's from Qualcomm. "qcom,pm8941-gpio" "qcom,pm8994-gpio" "qcom,pma8084-gpio" + "qcom,pmi8994-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -85,6 +86,7 @@ to specify in a pin configuration subnode: gpio1-gpio36 for pm8941 gpio1-gpio22 for pm8994 gpio1-gpio22 for pma8084 + gpio1-gpio10 for pmi8994 - function: Usage: required @@ -98,7 +100,10 @@ to specify in a pin configuration subnode: "dtest1", "dtest2", "dtest3", - "dtest4" + "dtest4", + And following values are supported by LV/MV GPIO subtypes: + "func3", + "func4" - bias-disable: Usage: optional @@ -183,6 +188,25 @@ to specify in a pin configuration subnode: Value type: <none> Definition: The specified pins are configured in open-source mode. +- qcom,analog-pass: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in analog-pass-through mode. + +- qcom,atest: + Usage: optional + Value type: <u32> + Definition: Selects ATEST rail to route to GPIO when it's configured + in analog-pass-through mode. + Valid values are 1-4 corresponding to ATEST1 to ATEST4. + +- qcom,dtest-buffer: + Usage: optional + Value type: <u32> + Definition: Selects DTEST rail to route to GPIO when it's configured + as digital input. + Valid values are 1-4 corresponding to DTEST1 to DTEST4. + Example: pm8921_gpio: gpio@150 { diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 645082f03259..f4d127df980d 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -24,6 +24,7 @@ Required Properties: - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. + - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - reg: Base address and length of each memory resource used by the pin diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index ee01ab58224d..58b7921b4fed 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -24,6 +24,7 @@ Required properties for iomux controller: "rockchip,rk2928-pinctrl": for Rockchip RK2928 "rockchip,rk3066a-pinctrl": for Rockchip RK3066a "rockchip,rk3066b-pinctrl": for Rockchip RK3066b + "rockchip,rk3128-pinctrl": for Rockchip RK3128 "rockchip,rk3188-pinctrl": for Rockchip RK3188 "rockchip,rk3228-pinctrl": for Rockchip RK3228 "rockchip,rk3288-pinctrl": for Rockchip RK3288 diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt new file mode 100644 index 000000000000..b1cea7a3a071 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt @@ -0,0 +1,83 @@ +* Spreadtrum Pin Controller + +The Spreadtrum pin controller are organized in 3 blocks (types). + +The first block comprises some global control registers, and each +register contains several bit fields with one bit or several bits +to configure for some global common configuration, such as domain +pad driving level, system control select and so on ("domain pad +driving level": One pin can output 3.0v or 1.8v, depending on the +related domain pad driving selection, if the related domain pad +slect 3.0v, then the pin can output 3.0v. "system control" is used +to choose one function (like: UART0) for which system, since we +have several systems (AP/CP/CM4) on one SoC.). + +There are too much various configuration that we can not list all +of them, so we can not make every Spreadtrum-special configuration +as one generic configuration, and maybe it will add more strange +global configuration in future. Then we add one "sprd,control" to +set these various global control configuration, and we need use +magic number for this property. + +Moreover we recognise every fields comprising one bit or several +bits in one global control register as one pin, thus we should +record every pin's bit offset, bit width and register offset to +configure this field (pin). + +The second block comprises some common registers which have unified +register definition, and each register described one pin is used +to configure the pin sleep mode, function select and sleep related +configuration. + +Now we have 4 systems for sleep mode on SC9860 SoC: AP system, +PUBCP system, TGLDSP system and AGDSP system. And the pin sleep +related configuration are: +- input-enable +- input-disable +- output-high +- output-low +- bias-pull-up +- bias-pull-down + +In some situation we need set the pin sleep mode and pin sleep related +configuration, to set the pin sleep related configuration automatically +by hardware when the system specified by sleep mode goes into deep +sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP +and set the pin sleep related configuration as "input-enable", which +means when PUBCP system goes into deep sleep mode, this pin will be set +input enable automatically. + +Moreover we can not use the "sleep" state, since some systems (like: +PUBCP system) do not run linux kernel OS (only AP system run linux +kernel on SC9860 platform), then we can not select "sleep" state +when the PUBCP system goes into deep sleep mode. Thus we introduce +"sprd,sleep-mode" property to set pin sleep mode. + +The last block comprises some misc registers which also have unified +register definition, and each register described one pin is used to +configure drive strength, pull up/down and so on. Especially for pull +up, we have two kind pull up resistor: 20K and 4.7K. + +Required properties for Spreadtrum pin controller: +- compatible: "sprd,<soc>-pinctrl" + Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs. +- reg: The register address of pin controller device. +- pins : An array of pin names. + +Optional properties: +- function: Specified the function name. +- drive-strength: Drive strength in mA. +- input-schmitt-disable: Enable schmitt-trigger mode. +- input-schmitt-enable: Disable schmitt-trigger mode. +- bias-disable: Disable pin bias. +- bias-pull-down: Pull down on pin. +- bias-pull-up: Pull up on pin. +- input-enable: Enable pin input. +- input-disable: Enable pin output. +- output-high: Set the pin as an output level high. +- output-low: Set the pin as an output level low. +- sleep-hardware-state: Indicate these configs in this state are sleep related. +- sprd,control: Control values referring to databook for global control pins. +- sprd,sleep-mode: Sleep mode selection. + +Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values. diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt new file mode 100644 index 000000000000..5a628333d52f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.txt @@ -0,0 +1,70 @@ +* Spreadtrum SC9860 Pin Controller + +Please refer to sprd,pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: Must be "sprd,sc9860-pinctrl". +- reg: The register address of pin controller device. +- pins : An array of strings, each string containing the name of a pin. + +Optional properties: +- function: A string containing the name of the function, values must be + one of: "func1", "func2", "func3" and "func4". +- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10, + 12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33. +- input-schmitt-disable: Enable schmitt-trigger mode. +- input-schmitt-enable: Disable schmitt-trigger mode. +- bias-disable: Disable pin bias. +- bias-pull-down: Pull down on pin. +- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor + is 20K and 4700 for pull-up resistor is 4.7K. +- input-enable: Enable pin input. +- input-disable: Enable pin output. +- output-high: Set the pin as an output level high. +- output-low: Set the pin as an output level low. +- sleep-hardware-state: Indicate these configs in this state are sleep related. +- sprd,control: Control values referring to databook for global control pins. +- sprd,sleep-mode: Choose the pin sleep mode, and supported values are: + AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP. + +Pin sleep mode definition: +enum pin_sleep_mode { + AP_SLEEP = BIT(0), + PUBCP_SLEEP = BIT(1), + TGLDSP_SLEEP = BIT(2), + AGDSP_SLEEP = BIT(3), +}; + +Example: +pin_controller: pinctrl@402a0000 { + compatible = "sprd,sc9860-pinctrl"; + reg = <0x402a0000 0x10000>; + + grp1: sd0 { + pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; + sprd,control = <0x1>; + }; + + grp2: rfctl_33 { + pins = "SC9860_RFCTL33"; + function = "func2"; + sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>; + grp2_sleep_mode: rfctl_33_sleep { + pins = "SC9860_RFCTL33"; + sleep-hardware-state; + output-low; + } + }; + + grp3: rfctl_misc_20 { + pins = "SC9860_RFCTL20_MISC"; + drive-strength = <10>; + bias-pull-up = <4700>; + grp3_sleep_mode: rfctl_misc_sleep { + pins = "SC9860_RFCTL20_MISC"; + sleep-hardware-state; + bias-pull-up; + } + }; +}; diff --git a/MAINTAINERS b/MAINTAINERS index a90fe134ceb1..c8b2c7e798fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1282,10 +1282,15 @@ S: Maintained ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE M: Hans Ulli Kroll <ulli.kroll@googlemail.com> +M: Linus Walleij <linus.walleij@linaro.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) T: git git://github.com/ulli-kroll/linux.git S: Maintained +F: Documentation/devicetree/bindings/arm/gemini.txt +F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt +F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt F: arch/arm/mach-gemini/ +F: drivers/pinctrl/pinctrl-gemini.c F: drivers/rtc/rtc-ftrtc010.c ARM/CSR SIRFPRIMA2 MACHINE SUPPORT diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h new file mode 100644 index 000000000000..fe511775b518 --- /dev/null +++ b/arch/arm/boot/dts/imx7ulp-pinfunc.h @@ -0,0 +1,468 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX7ULP_PINFUNC_H +#define __DTS_IMX7ULP_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_conf_reg input_reg mux_mode input_val> + */ + +#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 +#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 +#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 +#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 +#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 +#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 +#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 +#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 +#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 +#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 +#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 +#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 +#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 +#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 +#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 +#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 +#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 +#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 +#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 +#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 +#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 +#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 +#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 +#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 +#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 +#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 +#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 +#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 +#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 +#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 +#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 +#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 +#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 +#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 +#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 +#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 +#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 +#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 +#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 +#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 +#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 +#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 +#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 +#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 +#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 +#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 +#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 + +#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index e14b46c7b37f..34ad10873452 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -146,6 +146,13 @@ config PINCTRL_FALCON depends on SOC_FALCON depends on PINCTRL_LANTIQ +config PINCTRL_GEMINI + bool + depends on ARCH_GEMINI + default ARCH_GEMINI + select PINMUX + select MFD_SYSCON + config PINCTRL_MCP23S08 tristate "Microchip MCP23xxx I/O expander" depends on SPI_MASTER || I2C @@ -343,6 +350,7 @@ source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" +source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/stm32/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 2bc641d62400..4c44703ac97f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o +obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MESON) += meson/ @@ -55,6 +56,7 @@ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ +obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ obj-y += ti/ diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index cf3106cec048..05b153034517 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -1006,15 +1006,23 @@ SS_PIN_DECL(H3, GPIOQ5, SDA14); FUNC_GROUP_DECL(I2C14, H4, H3); -#define DASH9028_DESC SIG_DESC_SET(SCU90, 28) +/* + * There are several opportunities to document USB port 4 in the datasheet, but + * it is only mentioned in one location. Particularly, the Multi-function Pins + * Mapping and Control table in the datasheet elides the signal names, + * suggesting that port 4 may not actually be functional. As such we define the + * signal names and control bit, but don't export the capability's function or + * group. + */ +#define USB11H3_DESC SIG_DESC_SET(SCU90, 28) #define H2 134 -SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC); -SS_PIN_DECL(H2, GPIOQ6, DASHH2); +SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC); +SS_PIN_DECL(H2, GPIOQ6, USB11HDP3); #define H1 135 -SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC); -SS_PIN_DECL(H1, GPIOQ7, DASHH1); +SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC); +SS_PIN_DECL(H1, GPIOQ7, USB11HDN3); #define V20 136 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); @@ -1706,10 +1714,42 @@ FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19, FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, L19); +#define USB11H2_DESC SIG_DESC_SET(SCU90, 3) +#define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0) + +#define K4 220 +SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC); +MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1)); + +#define K3 221 +SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC); +MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1)); + +FUNC_GROUP_DECL(USB11H2, K4, K3); +FUNC_GROUP_DECL(USB11D1, K4, K3); + +#define USB2H1_DESC SIG_DESC_SET(SCU90, 29) +#define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0) + +#define AB21 222 +SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC); +MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1)); + +#define AB20 223 +SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC); +MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1)); + +FUNC_GROUP_DECL(USB2H1, AB21, AB20); +FUNC_GROUP_DECL(USB2D1, AB21, AB20); + /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216 - * pins becomes 220. + * pins becomes 220. Four additional non-GPIO-capable pins are present for USB. */ -#define ASPEED_G4_NR_PINS 220 +#define ASPEED_G4_NR_PINS 224 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ @@ -1749,6 +1789,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(AB5), ASPEED_PINCTRL_PIN(AB6), ASPEED_PINCTRL_PIN(AB7), + ASPEED_PINCTRL_PIN(AB20), + ASPEED_PINCTRL_PIN(AB21), ASPEED_PINCTRL_PIN(B1), ASPEED_PINCTRL_PIN(B10), ASPEED_PINCTRL_PIN(B11), @@ -1848,6 +1890,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = { ASPEED_PINCTRL_PIN(J5), ASPEED_PINCTRL_PIN(K18), ASPEED_PINCTRL_PIN(K20), + ASPEED_PINCTRL_PIN(K3), + ASPEED_PINCTRL_PIN(K4), ASPEED_PINCTRL_PIN(K5), ASPEED_PINCTRL_PIN(L1), ASPEED_PINCTRL_PIN(L18), @@ -2070,6 +2114,10 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(TXD3), ASPEED_PINCTRL_GROUP(TXD4), ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USB11D1), + ASPEED_PINCTRL_GROUP(USB11H2), + ASPEED_PINCTRL_GROUP(USB2D1), + ASPEED_PINCTRL_GROUP(USB2H1), ASPEED_PINCTRL_GROUP(USBCKI), ASPEED_PINCTRL_GROUP(VGABIOS_ROM), ASPEED_PINCTRL_GROUP(VGAHS), @@ -2221,6 +2269,10 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(TXD3), ASPEED_PINCTRL_FUNC(TXD4), ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USB11D1), + ASPEED_PINCTRL_FUNC(USB11H2), + ASPEED_PINCTRL_FUNC(USB2D1), + ASPEED_PINCTRL_FUNC(USB2H1), ASPEED_PINCTRL_FUNC(USBCKI), ASPEED_PINCTRL_FUNC(VGABIOS_ROM), ASPEED_PINCTRL_FUNC(VGAHS), @@ -2349,7 +2401,7 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { .nconfigs = ARRAY_SIZE(aspeed_g4_configs), }; -static struct pinmux_ops aspeed_g4_pinmux_ops = { +static const struct pinmux_ops aspeed_g4_pinmux_ops = { .get_functions_count = aspeed_pinmux_get_fn_count, .get_function_name = aspeed_pinmux_get_fn_name, .get_function_groups = aspeed_pinmux_get_fn_groups, @@ -2358,7 +2410,7 @@ static struct pinmux_ops aspeed_g4_pinmux_ops = { .strict = true, }; -static struct pinctrl_ops aspeed_g4_pinctrl_ops = { +static const struct pinctrl_ops aspeed_g4_pinctrl_ops = { .get_groups_count = aspeed_pinctrl_get_groups_count, .get_group_name = aspeed_pinctrl_get_group_name, .get_group_pins = aspeed_pinctrl_get_group_pins, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 68aa04664a62..187abd7693cf 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -25,7 +25,7 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" -#define ASPEED_G5_NR_PINS 232 +#define ASPEED_G5_NR_PINS 236 #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 } #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } @@ -1724,6 +1724,48 @@ FUNC_GROUP_DECL(LPCRST, G22); FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); +#define A7 232 +SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP)); + +#define A8 233 +SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN)); + +FUNC_GROUP_DECL(USB2AH, A7, A8); +FUNC_GROUP_DECL(USB2AD, A7, A8); + +#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 } +#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 } +#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 } +#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 } + +#define B6 234 +SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH), + SIG_EXPR_PTR(USB2BHDP2, USB2BH)); +MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP), + SIG_EXPR_LIST_PTR(USB2BHDP)); + +#define A6 235 +SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH), + SIG_EXPR_PTR(USB2BHDN2, USB2BH)); +MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN), + SIG_EXPR_LIST_PTR(USB2BHDN)); + +FUNC_GROUP_DECL(USB11BHID, B6, A6); +FUNC_GROUP_DECL(USB2BD, B6, A6); +FUNC_GROUP_DECL(USB2BH, B6, A6); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { @@ -1743,6 +1785,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A5), + ASPEED_PINCTRL_PIN(A6), + ASPEED_PINCTRL_PIN(A7), + ASPEED_PINCTRL_PIN(A8), ASPEED_PINCTRL_PIN(A9), ASPEED_PINCTRL_PIN(AA1), ASPEED_PINCTRL_PIN(AA19), @@ -1777,6 +1822,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B4), ASPEED_PINCTRL_PIN(B5), + ASPEED_PINCTRL_PIN(B6), ASPEED_PINCTRL_PIN(B9), ASPEED_PINCTRL_PIN(C1), ASPEED_PINCTRL_PIN(C11), @@ -2111,6 +2157,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ASPEED_PINCTRL_GROUP(TXD3), ASPEED_PINCTRL_GROUP(TXD4), ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(USB11BHID), + ASPEED_PINCTRL_GROUP(USB2AD), + ASPEED_PINCTRL_GROUP(USB2AH), + ASPEED_PINCTRL_GROUP(USB2BD), + ASPEED_PINCTRL_GROUP(USB2BH), ASPEED_PINCTRL_GROUP(USBCKI), ASPEED_PINCTRL_GROUP(VGABIOSROM), ASPEED_PINCTRL_GROUP(VGAHS), @@ -2275,6 +2326,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ASPEED_PINCTRL_FUNC(TXD3), ASPEED_PINCTRL_FUNC(TXD4), ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(USB11BHID), + ASPEED_PINCTRL_FUNC(USB2AD), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2BD), + ASPEED_PINCTRL_FUNC(USB2BH), ASPEED_PINCTRL_FUNC(USBCKI), ASPEED_PINCTRL_FUNC(VGABIOSROM), ASPEED_PINCTRL_FUNC(VGAHS), @@ -2436,7 +2492,7 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { .nconfigs = ARRAY_SIZE(aspeed_g5_configs), }; -static struct pinmux_ops aspeed_g5_pinmux_ops = { +static const struct pinmux_ops aspeed_g5_pinmux_ops = { .get_functions_count = aspeed_pinmux_get_fn_count, .get_function_name = aspeed_pinmux_get_fn_name, .get_function_groups = aspeed_pinmux_get_fn_groups, @@ -2445,7 +2501,7 @@ static struct pinmux_ops aspeed_g5_pinmux_ops = { .strict = true, }; -static struct pinctrl_ops aspeed_g5_pinctrl_ops = { +static const struct pinctrl_ops aspeed_g5_pinctrl_ops = { .get_groups_count = aspeed_pinctrl_get_groups_count, .get_group_name = aspeed_pinctrl_get_group_name, .get_group_pins = aspeed_pinctrl_get_group_pins, @@ -2454,7 +2510,7 @@ static struct pinctrl_ops aspeed_g5_pinctrl_ops = { .dt_free_map = pinctrl_utils_free_map, }; -static struct pinconf_ops aspeed_g5_conf_ops = { +static const struct pinconf_ops aspeed_g5_conf_ops = { .is_generic = true, .pin_config_get = aspeed_pin_config_get, .pin_config_set = aspeed_pin_config_set, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index a86a4d66099c..7f13ce8450a3 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -213,6 +213,27 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr, if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) continue; + /* On AST2500, Set bits in SCU7C are cleared from SCU70 */ + if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) { + unsigned int rev_id; + + ret = regmap_read(maps[ASPEED_IP_SCU], + HW_REVISION_ID, &rev_id); + if (ret < 0) + return ret; + + if (0x04 == (rev_id >> 24)) { + u32 value = ~val & desc->mask; + + if (value) { + ret = regmap_write(maps[desc->ip], + HW_REVISION_ID, value); + if (ret < 0) + return ret; + } + } + } + ret = regmap_update_bits(maps[desc->ip], desc->reg, desc->mask, val); diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index fa125db828f5..d4d7f032c1da 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -251,6 +251,7 @@ #define SCU3C 0x3C /* System Reset Control/Status Register */ #define SCU48 0x48 /* MAC Interface Clock Delay Setting */ #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */ +#define HW_REVISION_ID 0x7C /* Silicon revision ID register */ #define SCU80 0x80 /* Multi-function Pin Control #1 */ #define SCU84 0x84 /* Multi-function Pin Control #2 */ #define SCU88 0x88 /* Multi-function Pin Control #3 */ diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index a7cceffcedfa..bc3b232a727a 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -1384,7 +1384,7 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev, return 0; } -static struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = { +static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = { .pin_config_get = bcm281xx_pinctrl_pin_config_get, .pin_config_set = bcm281xx_pinctrl_pin_config_set, }; diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 230883168e99..0944310225db 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -92,7 +92,6 @@ struct bcm2835_pinctrl { struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; - int irq_group[BCM2835_NUM_IRQS]; spinlock_t irq_lock[BCM2835_NUM_BANKS]; }; @@ -353,7 +352,7 @@ static int bcm2835_gpio_direction_output(struct gpio_chip *chip, return pinctrl_gpio_direction_output(chip->base + offset); } -static struct gpio_chip bcm2835_gpio_chip = { +static const struct gpio_chip bcm2835_gpio_chip = { .label = MODULE_NAME, .owner = THIS_MODULE, .request = gpiochip_generic_request, @@ -400,7 +399,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) for (i = 0; i < ARRAY_SIZE(pc->irq); i++) { if (pc->irq[i] == irq) { - group = pc->irq_group[i]; + group = i; break; } } @@ -692,8 +691,7 @@ static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, struct pinctrl_map *map = *maps; if (fnum >= ARRAY_SIZE(bcm2835_functions)) { - dev_err(pc->dev, "%s: invalid brcm,function %d\n", - of_node_full_name(np), fnum); + dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum); return -EINVAL; } @@ -713,8 +711,7 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, unsigned long *configs; if (pull > 2) { - dev_err(pc->dev, "%s: invalid brcm,pull %d\n", - of_node_full_name(np), pull); + dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull); return -EINVAL; } @@ -745,8 +742,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, pins = of_find_property(np, "brcm,pins", NULL); if (!pins) { - dev_err(pc->dev, "%s: missing brcm,pins property\n", - of_node_full_name(np)); + dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np); return -EINVAL; } @@ -755,8 +751,8 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, if (!funcs && !pulls) { dev_err(pc->dev, - "%s: neither brcm,function nor brcm,pull specified\n", - of_node_full_name(np)); + "%pOF: neither brcm,function nor brcm,pull specified\n", + np); return -EINVAL; } @@ -766,15 +762,15 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, if (num_funcs > 1 && num_funcs != num_pins) { dev_err(pc->dev, - "%s: brcm,function must have 1 or %d entries\n", - of_node_full_name(np), num_pins); + "%pOF: brcm,function must have 1 or %d entries\n", + np, num_pins); return -EINVAL; } if (num_pulls > 1 && num_pulls != num_pins) { dev_err(pc->dev, - "%s: brcm,pull must have 1 or %d entries\n", - of_node_full_name(np), num_pins); + "%pOF: brcm,pull must have 1 or %d entries\n", + np, num_pins); return -EINVAL; } @@ -793,8 +789,8 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, if (err) goto out; if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) { - dev_err(pc->dev, "%s: invalid brcm,pins value %d\n", - of_node_full_name(np), pin); + dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n", + np, pin); err = -EINVAL; goto out; } @@ -1047,7 +1043,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < BCM2835_NUM_IRQS; i++) { pc->irq[i] = irq_of_parse_and_map(np, i); - pc->irq_group[i] = i; if (pc->irq[i] == 0) continue; diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index 8f0dc02f7624..cc3bd2efafe3 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -206,8 +206,8 @@ static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl, static int berlin_pinctrl_build_state(struct platform_device *pdev) { struct berlin_pinctrl *pctrl = platform_get_drvdata(pdev); - struct berlin_desc_group const *desc_group; - struct berlin_desc_function const *desc_function; + const struct berlin_desc_group *desc_group; + const struct berlin_desc_function *desc_function; int i, max_functions = 0; pctrl->nfunctions = 0; diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index c5e2c5705058..56fbe4c3e800 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -264,7 +264,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, } static int pinctrl_register_pins(struct pinctrl_dev *pctldev, - struct pinctrl_pin_desc const *pins, + const struct pinctrl_pin_desc *pins, unsigned num_descs) { unsigned i; @@ -686,7 +686,7 @@ EXPORT_SYMBOL_GPL(pinctrl_generic_remove_group); static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev) { struct radix_tree_iter iter; - void **slot; + void __rcu **slot; radix_tree_for_each_slot(slot, &pctldev->pin_group_tree, &iter, 0) radix_tree_delete(&pctldev->pin_group_tree, iter.index); @@ -907,7 +907,7 @@ static struct pinctrl_state *create_state(struct pinctrl *p, } static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev, - struct pinctrl_map const *map) + const struct pinctrl_map *map) { struct pinctrl_state *state; struct pinctrl_setting *setting; @@ -995,7 +995,7 @@ static struct pinctrl *create_pinctrl(struct device *dev, const char *devname; struct pinctrl_maps *maps_node; int i; - struct pinctrl_map const *map; + const struct pinctrl_map *map; int ret; /* @@ -1321,7 +1321,7 @@ void devm_pinctrl_put(struct pinctrl *p) } EXPORT_SYMBOL_GPL(devm_pinctrl_put); -int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, +int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, bool dup) { int i, ret; @@ -1380,7 +1380,6 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL); if (!maps_node->maps) { - pr_err("failed to duplicate mapping table\n"); kfree(maps_node); return -ENOMEM; } @@ -1402,13 +1401,13 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, * function will perform a shallow copy for the mapping entries. * @num_maps: the number of maps in the mapping table */ -int pinctrl_register_mappings(struct pinctrl_map const *maps, +int pinctrl_register_mappings(const struct pinctrl_map *maps, unsigned num_maps) { return pinctrl_register_map(maps, num_maps, true); } -void pinctrl_unregister_map(struct pinctrl_map const *map) +void pinctrl_unregister_map(const struct pinctrl_map *map) { struct pinctrl_maps *maps_node; @@ -1702,7 +1701,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what) { struct pinctrl_maps *maps_node; int i; - struct pinctrl_map const *map; + const struct pinctrl_map *map; seq_puts(s, "Pinctrl maps:\n"); diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 1c35de59a658..7880c3adc450 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -179,7 +179,7 @@ struct pin_desc { */ struct pinctrl_maps { struct list_head node; - struct pinctrl_map const *maps; + const struct pinctrl_map *maps; unsigned num_maps; }; @@ -243,9 +243,9 @@ extern struct pinctrl_gpio_range * pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev, unsigned int pin); -int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, +int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps, bool dup); -void pinctrl_unregister_map(struct pinctrl_map const *map); +void pinctrl_unregister_map(const struct pinctrl_map *map); extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev); extern int pinctrl_force_default(struct pinctrl_dev *pctldev); diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 0e5c9f14a706..1ff6c3573493 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -83,7 +83,6 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, /* Remember the converted mapping table entries */ dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL); if (!dt_map) { - dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n"); dt_free_map(pctldev, map, num_maps); return -ENOMEM; } @@ -117,8 +116,8 @@ static int dt_to_map_one_config(struct pinctrl *p, for (;;) { np_pctldev = of_get_next_parent(np_pctldev); if (!np_pctldev || of_node_is_root(np_pctldev)) { - dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n", - np_config->full_name); + dev_info(p->dev, "could not find pctldev for node %pOF, deferring probe\n", + np_config); of_node_put(np_pctldev); /* OK let's just assume this will appear later then */ return -EPROBE_DEFER; @@ -158,10 +157,8 @@ static int dt_remember_dummy_state(struct pinctrl *p, const char *statename) struct pinctrl_map *map; map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) { - dev_err(p->dev, "failed to alloc struct pinctrl_map\n"); + if (!map) return -ENOMEM; - } /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ map->type = PIN_MAP_TYPE_DUMMY_STATE; diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 0b266b2aecd4..4dbc576ae27c 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -103,6 +103,13 @@ config PINCTRL_IMX7D help Say Y here to enable the imx7d pinctrl driver +config PINCTRL_IMX7ULP + bool "IMX7ULP pinctrl driver" + depends on SOC_IMX7ULP + select PINCTRL_IMX + help + Say Y here to enable the imx7ulp pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index d44c9e253f21..525a5ff5dcb4 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o +obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 72aca758f4c6..6e472691d8ee 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -35,18 +35,6 @@ #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ #define IMX_PAD_SION 0x40000000 /* set SION */ -/** - * @dev: a pointer back to containing device - * @base: the offset to the controller in virtual memory - */ -struct imx_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - void __iomem *input_sel_base; - struct imx_pinctrl_soc_info *info; -}; - static inline const struct group_desc *imx_pinctrl_find_group_by_name( struct pinctrl_dev *pctldev, const char *name) @@ -255,111 +243,11 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - struct group_desc *grp; - struct imx_pin *imx_pin; - unsigned int pin, group; - u32 reg; - - /* Currently implementation only for shared mux/conf register */ - if (!(info->flags & SHARE_MUX_CONF_REG)) - return 0; - - pin_reg = &info->pin_regs[offset]; - if (pin_reg->mux_reg == -1) - return -EINVAL; - - /* Find the pinctrl config with GPIO mux mode for the requested pin */ - for (group = 0; group < pctldev->num_groups; group++) { - grp = pinctrl_generic_get_group(pctldev, group); - if (!grp) - continue; - for (pin = 0; pin < grp->num_pins; pin++) { - imx_pin = &((struct imx_pin *)(grp->data))[pin]; - if (imx_pin->pin == offset && !imx_pin->mux_mode) - goto mux_pin; - } - } - - return -EINVAL; - -mux_pin: - reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~info->mux_mask; - reg |= imx_pin->config; - writel(reg, ipctl->base + pin_reg->mux_reg); - - return 0; -} - -static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - u32 reg; - - /* - * Only Vybrid has the input/output buffer enable flags (IBE/OBE) - * They are part of the shared mux/conf register. - */ - if (!(info->flags & SHARE_MUX_CONF_REG)) - return; - - pin_reg = &info->pin_regs[offset]; - if (pin_reg->mux_reg == -1) - return; - - /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */ - reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~0x7; - writel(reg, ipctl->base + pin_reg->mux_reg); -} - -static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, unsigned offset, bool input) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - u32 reg; - - /* - * Only Vybrid has the input/output buffer enable flags (IBE/OBE) - * They are part of the shared mux/conf register. - */ - if (!(info->flags & SHARE_MUX_CONF_REG)) - return 0; - - pin_reg = &info->pin_regs[offset]; - if (pin_reg->mux_reg == -1) - return -EINVAL; - - /* IBE always enabled allows us to read the value "on the wire" */ - reg = readl(ipctl->base + pin_reg->mux_reg); - if (input) - reg &= ~0x2; - else - reg |= 0x2; - writel(reg, ipctl->base + pin_reg->mux_reg); - - return 0; -} - -static const struct pinmux_ops imx_pmx_ops = { +struct pinmux_ops imx_pmx_ops = { .get_functions_count = pinmux_generic_get_function_count, .get_function_name = pinmux_generic_get_function_name, .get_function_groups = pinmux_generic_get_function_groups, .set_mux = imx_pmx_set, - .gpio_request_enable = imx_pmx_gpio_request_enable, - .gpio_disable_free = imx_pmx_gpio_disable_free, - .gpio_set_direction = imx_pmx_gpio_set_direction, }; /* decode generic config into raw register values */ @@ -563,26 +451,24 @@ static int imx_pinctrl_parse_groups(struct device_node *np, * do sanity check and calculate pins number * * First try legacy 'fsl,pins' property, then fall back to the - * generic 'pins'. + * generic 'pinmux'. * - * Note: for generic 'pins' case, there's no CONFIG part in + * Note: for generic 'pinmux' case, there's no CONFIG part in * the binding format. */ list = of_get_property(np, "fsl,pins", &size); if (!list) { - list = of_get_property(np, "pins", &size); + list = of_get_property(np, "pinmux", &size); if (!list) { dev_err(info->dev, - "no fsl,pins and pins property in node %s\n", - np->full_name); + "no fsl,pins and pins property in node %pOF\n", np); return -EINVAL; } } /* we do not check return since it's safe node passed down */ if (!size || size % pin_size) { - dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n", - np->full_name); + dev_err(info->dev, "Invalid fsl,pins or pins property in node %pOF\n", np); return -EINVAL; } @@ -666,7 +552,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, func->name = np->name; func->num_group_names = of_get_child_count(np); if (func->num_group_names == 0) { - dev_err(info->dev, "no groups defined in %s\n", np->full_name); + dev_err(info->dev, "no groups defined in %pOF\n", np); return -EINVAL; } func->group_names = devm_kcalloc(info->dev, func->num_group_names, @@ -862,6 +748,9 @@ int imx_pinctrl_probe(struct platform_device *pdev, imx_pinctrl_desc->custom_params = info->custom_params; imx_pinctrl_desc->num_custom_params = info->num_custom_params; + /* platform specific callback */ + imx_pmx_ops.gpio_set_direction = info->gpio_set_direction; + mutex_init(&info->mutex); ipctl->info = info; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 880bba7fd1ab..5aa22b52c1d4 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -16,9 +16,12 @@ #define __DRIVERS_PINCTRL_IMX_H #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> struct platform_device; +extern struct pinmux_ops imx_pmx_ops; + /** * struct imx_pin - describes a single i.MX pin * @pin: the pin_id of this pin @@ -76,6 +79,23 @@ struct imx_pinctrl_soc_info { unsigned int num_decodes; void (*fixup)(unsigned long *configs, unsigned int num_configs, u32 *raw_config); + + int (*gpio_set_direction)(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, + bool input); +}; + +/** + * @dev: a pointer back to containing device + * @base: the offset to the controller in virtual memory + */ +struct imx_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + void __iomem *input_sel_base; + struct imx_pinctrl_soc_info *info; }; #define IMX_CFG_PARAMS_DECODE(p, m, o) \ diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c index 89b4f160138f..c9405685971b 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx23.c +++ b/drivers/pinctrl/freescale/pinctrl-imx23.c @@ -257,7 +257,7 @@ static const struct pinctrl_pin_desc imx23_pins[] = { MXS_PINCTRL_PIN(EMI_CLKN), }; -static struct mxs_regs imx23_regs = { +static const struct mxs_regs imx23_regs = { .muxsel = 0x100, .drive = 0x200, .pull = 0x400, diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c index 295236dfb0bc..87deb9ec938a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx28.c +++ b/drivers/pinctrl/freescale/pinctrl-imx28.c @@ -373,7 +373,7 @@ static const struct pinctrl_pin_desc imx28_pins[] = { MXS_PINCTRL_PIN(EMI_CKE), }; -static struct mxs_regs imx28_regs = { +static const struct mxs_regs imx28_regs = { .muxsel = 0x100, .drive = 0x300, .pull = 0x600, diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c new file mode 100644 index 000000000000..b7bebb292f37 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c @@ -0,0 +1,364 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2017 NXP + * + * Author: Dong Aisheng <aisheng.dong@nxp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx7ulp_pads { + IMX7ULP_PAD_PTC0 = 0, + IMX7ULP_PAD_PTC1, + IMX7ULP_PAD_PTC2, + IMX7ULP_PAD_PTC3, + IMX7ULP_PAD_PTC4, + IMX7ULP_PAD_PTC5, + IMX7ULP_PAD_PTC6, + IMX7ULP_PAD_PTC7, + IMX7ULP_PAD_PTC8, + IMX7ULP_PAD_PTC9, + IMX7ULP_PAD_PTC10, + IMX7ULP_PAD_PTC11, + IMX7ULP_PAD_PTC12, + IMX7ULP_PAD_PTC13, + IMX7ULP_PAD_PTC14, + IMX7ULP_PAD_PTC15, + IMX7ULP_PAD_PTC16, + IMX7ULP_PAD_PTC17, + IMX7ULP_PAD_PTC18, + IMX7ULP_PAD_PTC19, + IMX7ULP_PAD_RESERVE0, + IMX7ULP_PAD_RESERVE1, + IMX7ULP_PAD_RESERVE2, + IMX7ULP_PAD_RESERVE3, + IMX7ULP_PAD_RESERVE4, + IMX7ULP_PAD_RESERVE5, + IMX7ULP_PAD_RESERVE6, + IMX7ULP_PAD_RESERVE7, + IMX7ULP_PAD_RESERVE8, + IMX7ULP_PAD_RESERVE9, + IMX7ULP_PAD_RESERVE10, + IMX7ULP_PAD_RESERVE11, + IMX7ULP_PAD_PTD0, + IMX7ULP_PAD_PTD1, + IMX7ULP_PAD_PTD2, + IMX7ULP_PAD_PTD3, + IMX7ULP_PAD_PTD4, + IMX7ULP_PAD_PTD5, + IMX7ULP_PAD_PTD6, + IMX7ULP_PAD_PTD7, + IMX7ULP_PAD_PTD8, + IMX7ULP_PAD_PTD9, + IMX7ULP_PAD_PTD10, + IMX7ULP_PAD_PTD11, + IMX7ULP_PAD_RESERVE12, + IMX7ULP_PAD_RESERVE13, + IMX7ULP_PAD_RESERVE14, + IMX7ULP_PAD_RESERVE15, + IMX7ULP_PAD_RESERVE16, + IMX7ULP_PAD_RESERVE17, + IMX7ULP_PAD_RESERVE18, + IMX7ULP_PAD_RESERVE19, + IMX7ULP_PAD_RESERVE20, + IMX7ULP_PAD_RESERVE21, + IMX7ULP_PAD_RESERVE22, + IMX7ULP_PAD_RESERVE23, + IMX7ULP_PAD_RESERVE24, + IMX7ULP_PAD_RESERVE25, + IMX7ULP_PAD_RESERVE26, + IMX7ULP_PAD_RESERVE27, + IMX7ULP_PAD_RESERVE28, + IMX7ULP_PAD_RESERVE29, + IMX7ULP_PAD_RESERVE30, + IMX7ULP_PAD_RESERVE31, + IMX7ULP_PAD_PTE0, + IMX7ULP_PAD_PTE1, + IMX7ULP_PAD_PTE2, + IMX7ULP_PAD_PTE3, + IMX7ULP_PAD_PTE4, + IMX7ULP_PAD_PTE5, + IMX7ULP_PAD_PTE6, + IMX7ULP_PAD_PTE7, + IMX7ULP_PAD_PTE8, + IMX7ULP_PAD_PTE9, + IMX7ULP_PAD_PTE10, + IMX7ULP_PAD_PTE11, + IMX7ULP_PAD_PTE12, + IMX7ULP_PAD_PTE13, + IMX7ULP_PAD_PTE14, + IMX7ULP_PAD_PTE15, + IMX7ULP_PAD_RESERVE32, + IMX7ULP_PAD_RESERVE33, + IMX7ULP_PAD_RESERVE34, + IMX7ULP_PAD_RESERVE35, + IMX7ULP_PAD_RESERVE36, + IMX7ULP_PAD_RESERVE37, + IMX7ULP_PAD_RESERVE38, + IMX7ULP_PAD_RESERVE39, + IMX7ULP_PAD_RESERVE40, + IMX7ULP_PAD_RESERVE41, + IMX7ULP_PAD_RESERVE42, + IMX7ULP_PAD_RESERVE43, + IMX7ULP_PAD_RESERVE44, + IMX7ULP_PAD_RESERVE45, + IMX7ULP_PAD_RESERVE46, + IMX7ULP_PAD_RESERVE47, + IMX7ULP_PAD_PTF0, + IMX7ULP_PAD_PTF1, + IMX7ULP_PAD_PTF2, + IMX7ULP_PAD_PTF3, + IMX7ULP_PAD_PTF4, + IMX7ULP_PAD_PTF5, + IMX7ULP_PAD_PTF6, + IMX7ULP_PAD_PTF7, + IMX7ULP_PAD_PTF8, + IMX7ULP_PAD_PTF9, + IMX7ULP_PAD_PTF10, + IMX7ULP_PAD_PTF11, + IMX7ULP_PAD_PTF12, + IMX7ULP_PAD_PTF13, + IMX7ULP_PAD_PTF14, + IMX7ULP_PAD_PTF15, + IMX7ULP_PAD_PTF16, + IMX7ULP_PAD_PTF17, + IMX7ULP_PAD_PTF18, + IMX7ULP_PAD_PTF19, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46), + IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18), + IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19), +}; + +#define BM_OBE_ENABLED BIT(17) +#define BM_IBE_ENABLED BIT(16) +#define BM_LK_ENABLED BIT(15) +#define BM_MUX_MODE 0xf00 +#define BP_MUX_MODE 8 +#define BM_PULL_ENABLED BIT(1) + +struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = { + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0), + + IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5), + IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0), +}; + +static void imx7ulp_cfg_params_fixup(unsigned long *configs, + unsigned int num_configs, + u32 *raw_config) +{ + enum pin_config_param param; + u32 param_val; + int i; + + /* lock field disabled */ + *raw_config &= ~BM_LK_ENABLED; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + + if ((param == PIN_CONFIG_BIAS_PULL_UP) || + (param == PIN_CONFIG_BIAS_PULL_DOWN)) { + /* pull enabled */ + *raw_config |= BM_PULL_ENABLED; + + return; + } + } +} + +static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, bool input) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg; + u32 reg; + + pin_reg = &info->pin_regs[offset]; + if (pin_reg->mux_reg == -1) + return -EINVAL; + + reg = readl(ipctl->base + pin_reg->mux_reg); + if (input) + reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED; + else + reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED; + writel(reg, ipctl->base + pin_reg->mux_reg); + + return 0; +} + +static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = { + .pins = imx7ulp_pinctrl_pads, + .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads), + .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, + .gpio_set_direction = imx7ulp_pmx_gpio_set_direction, + .mux_mask = BM_MUX_MODE, + .mux_shift = BP_MUX_MODE, + .generic_pinconf = true, + .decodes = imx7ulp_cfg_decodes, + .num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes), + .fixup = imx7ulp_cfg_params_fixup, +}; + +static const struct of_device_id imx7ulp_pinctrl_of_match[] = { + { .compatible = "fsl,imx7ulp-iomuxc1", }, + { /* sentinel */ } +}; + +static int imx7ulp_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info); +} + +static struct platform_driver imx7ulp_pinctrl_driver = { + .driver = { + .name = "imx7ulp-pinctrl", + .of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = imx7ulp_pinctrl_probe, +}; + +static int __init imx7ulp_pinctrl_init(void) +{ + return platform_driver_register(&imx7ulp_pinctrl_driver); +} +arch_initcall(imx7ulp_pinctrl_init); diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 3bd85564d1e4..ac18bb6d6d5e 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -295,10 +295,35 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = { IMX_PINCTRL_PIN(VF610_PAD_PTA7), }; +static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset, bool input) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg; + u32 reg; + + pin_reg = &info->pin_regs[offset]; + if (pin_reg->mux_reg == -1) + return -EINVAL; + + /* IBE always enabled allows us to read the value "on the wire" */ + reg = readl(ipctl->base + pin_reg->mux_reg); + if (input) + reg &= ~0x2; + else + reg |= 0x2; + writel(reg, ipctl->base + pin_reg->mux_reg); + + return 0; +} + static struct imx_pinctrl_soc_info vf610_pinctrl_info = { .pins = vf610_pinctrl_pads, .npins = ARRAY_SIZE(vf610_pinctrl_pads), .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, + .gpio_set_direction = vf610_pmx_gpio_set_direction, .mux_mask = 0x700000, .mux_shift = 20, }; diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b82d6ff3116f..f30720a752f3 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -1,6 +1,7 @@ # # Intel pin control drivers # +if (X86 || COMPILE_TEST) config PINCTRL_BAYTRAIL bool "Intel Baytrail GPIO pin control" @@ -64,6 +65,14 @@ config PINCTRL_CANNONLAKE This pinctrl driver provides an interface that allows configuring of Intel Cannon Lake PCH pins and using them as GPIOs. +config PINCTRL_DENVERTON + tristate "Intel Denverton pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Denverton SoC pins and using them as GPIOs. + config PINCTRL_GEMINILAKE tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" depends on ACPI @@ -72,6 +81,14 @@ config PINCTRL_GEMINILAKE This pinctrl driver provides an interface that allows configuring of Intel Gemini Lake SoC pins and using them as GPIOs. +config PINCTRL_LEWISBURG + tristate "Intel Lewisburg pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Lewisburg pins and using them as GPIOs. + config PINCTRL_SUNRISEPOINT tristate "Intel Sunrisepoint pinctrl and GPIO driver" depends on ACPI @@ -80,3 +97,5 @@ config PINCTRL_SUNRISEPOINT Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver provides an interface that allows configuring of PCH pins and using them as GPIOs. + +endif diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 81df3cf408e3..c12874da5992 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -6,5 +6,7 @@ obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o +obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o +obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index fa3c5758ac67..0f3a02495aeb 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -981,12 +981,12 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, */ value = readl(reg) & BYT_PIN_MUX; gpio_mux = byt_get_gpio_mux(vg, offset); - if (WARN_ON(gpio_mux != value)) { + if (gpio_mux != value) { value = readl(reg) & ~BYT_PIN_MUX; value |= gpio_mux; writel(value, reg); - dev_warn(&vg->pdev->dev, + dev_warn(&vg->pdev->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset); } diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 3bc609b67dc2..e130599be571 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -2,7 +2,8 @@ * Intel Cannon Lake PCH pinctrl/GPIO driver * * Copyright (C) 2017, Intel Corporation - * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> + * Mika Westerberg <mika.westerberg@linux.intel.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -42,6 +43,426 @@ .ngpps = ARRAY_SIZE(g), \ } +/* Cannon Lake-H */ +static const struct pinctrl_pin_desc cnlh_pins[] = { + /* GPP_A */ + PINCTRL_PIN(0, "RCINB"), + PINCTRL_PIN(1, "LAD_0"), + PINCTRL_PIN(2, "LAD_1"), + PINCTRL_PIN(3, "LAD_2"), + PINCTRL_PIN(4, "LAD_3"), + PINCTRL_PIN(5, "LFRAMEB"), + PINCTRL_PIN(6, "SERIRQ"), + PINCTRL_PIN(7, "PIRQAB"), + PINCTRL_PIN(8, "CLKRUNB"), + PINCTRL_PIN(9, "CLKOUT_LPC_0"), + PINCTRL_PIN(10, "CLKOUT_LPC_1"), + PINCTRL_PIN(11, "PMEB"), + PINCTRL_PIN(12, "BM_BUSYB"), + PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(14, "SUS_STATB"), + PINCTRL_PIN(15, "SUSACKB"), + PINCTRL_PIN(16, "CLKOUT_48"), + PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"), + PINCTRL_PIN(18, "ISH_GP_0"), + PINCTRL_PIN(19, "ISH_GP_1"), + PINCTRL_PIN(20, "ISH_GP_2"), + PINCTRL_PIN(21, "ISH_GP_3"), + PINCTRL_PIN(22, "ISH_GP_4"), + PINCTRL_PIN(23, "ISH_GP_5"), + PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), + /* GPP_B */ + PINCTRL_PIN(25, "GSPI0_CS1B"), + PINCTRL_PIN(26, "GSPI1_CS1B"), + PINCTRL_PIN(27, "VRALERTB"), + PINCTRL_PIN(28, "CPU_GP_2"), + PINCTRL_PIN(29, "CPU_GP_3"), + PINCTRL_PIN(30, "SRCCLKREQB_0"), + PINCTRL_PIN(31, "SRCCLKREQB_1"), + PINCTRL_PIN(32, "SRCCLKREQB_2"), + PINCTRL_PIN(33, "SRCCLKREQB_3"), + PINCTRL_PIN(34, "SRCCLKREQB_4"), + PINCTRL_PIN(35, "SRCCLKREQB_5"), + PINCTRL_PIN(36, "SSP_MCLK"), + PINCTRL_PIN(37, "SLP_S0B"), + PINCTRL_PIN(38, "PLTRSTB"), + PINCTRL_PIN(39, "SPKR"), + PINCTRL_PIN(40, "GSPI0_CS0B"), + PINCTRL_PIN(41, "GSPI0_CLK"), + PINCTRL_PIN(42, "GSPI0_MISO"), + PINCTRL_PIN(43, "GSPI0_MOSI"), + PINCTRL_PIN(44, "GSPI1_CS0B"), + PINCTRL_PIN(45, "GSPI1_CLK"), + PINCTRL_PIN(46, "GSPI1_MISO"), + PINCTRL_PIN(47, "GSPI1_MOSI"), + PINCTRL_PIN(48, "SML1ALERTB"), + PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"), + /* GPP_C */ + PINCTRL_PIN(51, "SMBCLK"), + PINCTRL_PIN(52, "SMBDATA"), + PINCTRL_PIN(53, "SMBALERTB"), + PINCTRL_PIN(54, "SML0CLK"), + PINCTRL_PIN(55, "SML0DATA"), + PINCTRL_PIN(56, "SML0ALERTB"), + PINCTRL_PIN(57, "SML1CLK"), + PINCTRL_PIN(58, "SML1DATA"), + PINCTRL_PIN(59, "UART0_RXD"), + PINCTRL_PIN(60, "UART0_TXD"), + PINCTRL_PIN(61, "UART0_RTSB"), + PINCTRL_PIN(62, "UART0_CTSB"), + PINCTRL_PIN(63, "UART1_RXD"), + PINCTRL_PIN(64, "UART1_TXD"), + PINCTRL_PIN(65, "UART1_RTSB"), + PINCTRL_PIN(66, "UART1_CTSB"), + PINCTRL_PIN(67, "I2C0_SDA"), + PINCTRL_PIN(68, "I2C0_SCL"), + PINCTRL_PIN(69, "I2C1_SDA"), + PINCTRL_PIN(70, "I2C1_SCL"), + PINCTRL_PIN(71, "UART2_RXD"), + PINCTRL_PIN(72, "UART2_TXD"), + PINCTRL_PIN(73, "UART2_RTSB"), + PINCTRL_PIN(74, "UART2_CTSB"), + /* GPP_D */ + PINCTRL_PIN(75, "SPI1_CSB"), + PINCTRL_PIN(76, "SPI1_CLK"), + PINCTRL_PIN(77, "SPI1_MISO_IO_1"), + PINCTRL_PIN(78, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(79, "ISH_I2C2_SDA"), + PINCTRL_PIN(80, "SSP2_SFRM"), + PINCTRL_PIN(81, "SSP2_TXD"), + PINCTRL_PIN(82, "SSP2_RXD"), + PINCTRL_PIN(83, "SSP2_SCLK"), + PINCTRL_PIN(84, "ISH_SPI_CSB"), + PINCTRL_PIN(85, "ISH_SPI_CLK"), + PINCTRL_PIN(86, "ISH_SPI_MISO"), + PINCTRL_PIN(87, "ISH_SPI_MOSI"), + PINCTRL_PIN(88, "ISH_UART0_RXD"), + PINCTRL_PIN(89, "ISH_UART0_TXD"), + PINCTRL_PIN(90, "ISH_UART0_RTSB"), + PINCTRL_PIN(91, "ISH_UART0_CTSB"), + PINCTRL_PIN(92, "DMIC_CLK_1"), + PINCTRL_PIN(93, "DMIC_DATA_1"), + PINCTRL_PIN(94, "DMIC_CLK_0"), + PINCTRL_PIN(95, "DMIC_DATA_0"), + PINCTRL_PIN(96, "SPI1_IO_2"), + PINCTRL_PIN(97, "SPI1_IO_3"), + PINCTRL_PIN(98, "ISH_I2C2_SCL"), + /* GPP_G */ + PINCTRL_PIN(99, "SD3_CMD"), + PINCTRL_PIN(100, "SD3_D0"), + PINCTRL_PIN(101, "SD3_D1"), + PINCTRL_PIN(102, "SD3_D2"), + PINCTRL_PIN(103, "SD3_D3"), + PINCTRL_PIN(104, "SD3_CDB"), + PINCTRL_PIN(105, "SD3_CLK"), + PINCTRL_PIN(106, "SD3_WP"), + /* AZA */ + PINCTRL_PIN(107, "HDA_BCLK"), + PINCTRL_PIN(108, "HDA_RSTB"), + PINCTRL_PIN(109, "HDA_SYNC"), + PINCTRL_PIN(110, "HDA_SDO"), + PINCTRL_PIN(111, "HDA_SDI_0"), + PINCTRL_PIN(112, "HDA_SDI_1"), + PINCTRL_PIN(113, "SSP1_SFRM"), + PINCTRL_PIN(114, "SSP1_TXD"), + /* vGPIO */ + PINCTRL_PIN(115, "CNV_BTEN"), + PINCTRL_PIN(116, "CNV_GNEN"), + PINCTRL_PIN(117, "CNV_WFEN"), + PINCTRL_PIN(118, "CNV_WCEN"), + PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"), + PINCTRL_PIN(121, "vSD3_CD_B"), + PINCTRL_PIN(122, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(123, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(124, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(127, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(128, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"), + PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"), + PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"), + PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"), + PINCTRL_PIN(135, "vUART0_TXD"), + PINCTRL_PIN(136, "vUART0_RXD"), + PINCTRL_PIN(137, "vUART0_CTS_B"), + PINCTRL_PIN(138, "vUART0_RTSB"), + PINCTRL_PIN(139, "vISH_UART0_TXD"), + PINCTRL_PIN(140, "vISH_UART0_RXD"), + PINCTRL_PIN(141, "vISH_UART0_CTS_B"), + PINCTRL_PIN(142, "vISH_UART0_RTSB"), + PINCTRL_PIN(143, "vISH_UART1_TXD"), + PINCTRL_PIN(144, "vISH_UART1_RXD"), + PINCTRL_PIN(145, "vISH_UART1_CTS_B"), + PINCTRL_PIN(146, "vISH_UART1_RTS_B"), + PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(151, "vSSP2_SCLK"), + PINCTRL_PIN(152, "vSSP2_SFRM"), + PINCTRL_PIN(153, "vSSP2_TXD"), + PINCTRL_PIN(154, "vSSP2_RXD"), + /* GPP_K */ + PINCTRL_PIN(155, "FAN_TACH_0"), + PINCTRL_PIN(156, "FAN_TACH_1"), + PINCTRL_PIN(157, "FAN_TACH_2"), + PINCTRL_PIN(158, "FAN_TACH_3"), + PINCTRL_PIN(159, "FAN_TACH_4"), + PINCTRL_PIN(160, "FAN_TACH_5"), + PINCTRL_PIN(161, "FAN_TACH_6"), + PINCTRL_PIN(162, "FAN_TACH_7"), + PINCTRL_PIN(163, "FAN_PWM_0"), + PINCTRL_PIN(164, "FAN_PWM_1"), + PINCTRL_PIN(165, "FAN_PWM_2"), + PINCTRL_PIN(166, "FAN_PWM_3"), + PINCTRL_PIN(167, "GSXDOUT"), + PINCTRL_PIN(168, "GSXSLOAD"), + PINCTRL_PIN(169, "GSXDIN"), + PINCTRL_PIN(170, "GSXSRESETB"), + PINCTRL_PIN(171, "GSXCLK"), + PINCTRL_PIN(172, "ADR_COMPLETE"), + PINCTRL_PIN(173, "NMIB"), + PINCTRL_PIN(174, "SMIB"), + PINCTRL_PIN(175, "CORE_VID_0"), + PINCTRL_PIN(176, "CORE_VID_1"), + PINCTRL_PIN(177, "IMGCLKOUT_0"), + PINCTRL_PIN(178, "IMGCLKOUT_1"), + /* GPP_H */ + PINCTRL_PIN(179, "SRCCLKREQB_6"), + PINCTRL_PIN(180, "SRCCLKREQB_7"), + PINCTRL_PIN(181, "SRCCLKREQB_8"), + PINCTRL_PIN(182, "SRCCLKREQB_9"), + PINCTRL_PIN(183, "SRCCLKREQB_10"), + PINCTRL_PIN(184, "SRCCLKREQB_11"), + PINCTRL_PIN(185, "SRCCLKREQB_12"), + PINCTRL_PIN(186, "SRCCLKREQB_13"), + PINCTRL_PIN(187, "SRCCLKREQB_14"), + PINCTRL_PIN(188, "SRCCLKREQB_15"), + PINCTRL_PIN(189, "SML2CLK"), + PINCTRL_PIN(190, "SML2DATA"), + PINCTRL_PIN(191, "SML2ALERTB"), + PINCTRL_PIN(192, "SML3CLK"), + PINCTRL_PIN(193, "SML3DATA"), + PINCTRL_PIN(194, "SML3ALERTB"), + PINCTRL_PIN(195, "SML4CLK"), + PINCTRL_PIN(196, "SML4DATA"), + PINCTRL_PIN(197, "SML4ALERTB"), + PINCTRL_PIN(198, "ISH_I2C0_SDA"), + PINCTRL_PIN(199, "ISH_I2C0_SCL"), + PINCTRL_PIN(200, "ISH_I2C1_SDA"), + PINCTRL_PIN(201, "ISH_I2C1_SCL"), + PINCTRL_PIN(202, "TIME_SYNC_0"), + /* GPP_E */ + PINCTRL_PIN(203, "SATAXPCIE_0"), + PINCTRL_PIN(204, "SATAXPCIE_1"), + PINCTRL_PIN(205, "SATAXPCIE_2"), + PINCTRL_PIN(206, "CPU_GP_0"), + PINCTRL_PIN(207, "SATA_DEVSLP_0"), + PINCTRL_PIN(208, "SATA_DEVSLP_1"), + PINCTRL_PIN(209, "SATA_DEVSLP_2"), + PINCTRL_PIN(210, "CPU_GP_1"), + PINCTRL_PIN(211, "SATA_LEDB"), + PINCTRL_PIN(212, "USB2_OCB_0"), + PINCTRL_PIN(213, "USB2_OCB_1"), + PINCTRL_PIN(214, "USB2_OCB_2"), + PINCTRL_PIN(215, "USB2_OCB_3"), + /* GPP_F */ + PINCTRL_PIN(216, "SATAXPCIE_3"), + PINCTRL_PIN(217, "SATAXPCIE_4"), + PINCTRL_PIN(218, "SATAXPCIE_5"), + PINCTRL_PIN(219, "SATAXPCIE_6"), + PINCTRL_PIN(220, "SATAXPCIE_7"), + PINCTRL_PIN(221, "SATA_DEVSLP_3"), + PINCTRL_PIN(222, "SATA_DEVSLP_4"), + PINCTRL_PIN(223, "SATA_DEVSLP_5"), + PINCTRL_PIN(224, "SATA_DEVSLP_6"), + PINCTRL_PIN(225, "SATA_DEVSLP_7"), + PINCTRL_PIN(226, "SATA_SCLOCK"), + PINCTRL_PIN(227, "SATA_SLOAD"), + PINCTRL_PIN(228, "SATA_SDATAOUT1"), + PINCTRL_PIN(229, "SATA_SDATAOUT0"), + PINCTRL_PIN(230, "EXT_PWR_GATEB"), + PINCTRL_PIN(231, "USB2_OCB_4"), + PINCTRL_PIN(232, "USB2_OCB_5"), + PINCTRL_PIN(233, "USB2_OCB_6"), + PINCTRL_PIN(234, "USB2_OCB_7"), + PINCTRL_PIN(235, "L_VDDEN"), + PINCTRL_PIN(236, "L_BKLTEN"), + PINCTRL_PIN(237, "L_BKLTCTL"), + PINCTRL_PIN(238, "DDPF_CTRLCLK"), + PINCTRL_PIN(239, "DDPF_CTRLDATA"), + /* SPI */ + PINCTRL_PIN(240, "SPI0_IO_2"), + PINCTRL_PIN(241, "SPI0_IO_3"), + PINCTRL_PIN(242, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(243, "SPI0_MISO_IO_1"), + PINCTRL_PIN(244, "SPI0_TPM_CSB"), + PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(247, "SPI0_CLK"), + PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"), + /* CPU */ + PINCTRL_PIN(249, "HDACPU_SDI"), + PINCTRL_PIN(250, "HDACPU_SDO"), + PINCTRL_PIN(251, "HDACPU_SCLK"), + PINCTRL_PIN(252, "PM_SYNC"), + PINCTRL_PIN(253, "PECI"), + PINCTRL_PIN(254, "CPUPWRGD"), + PINCTRL_PIN(255, "THRMTRIPB"), + PINCTRL_PIN(256, "PLTRST_CPUB"), + PINCTRL_PIN(257, "PM_DOWN"), + PINCTRL_PIN(258, "TRIGGER_IN"), + PINCTRL_PIN(259, "TRIGGER_OUT"), + /* JTAG */ + PINCTRL_PIN(260, "JTAG_TDO"), + PINCTRL_PIN(261, "JTAGX"), + PINCTRL_PIN(262, "PRDYB"), + PINCTRL_PIN(263, "PREQB"), + PINCTRL_PIN(264, "CPU_TRSTB"), + PINCTRL_PIN(265, "JTAG_TDI"), + PINCTRL_PIN(266, "JTAG_TMS"), + PINCTRL_PIN(267, "JTAG_TCK"), + PINCTRL_PIN(268, "ITP_PMODE"), + /* GPP_I */ + PINCTRL_PIN(269, "DDSP_HPD_0"), + PINCTRL_PIN(270, "DDSP_HPD_1"), + PINCTRL_PIN(271, "DDSP_HPD_2"), + PINCTRL_PIN(272, "DDSP_HPD_3"), + PINCTRL_PIN(273, "EDP_HPD"), + PINCTRL_PIN(274, "DDPB_CTRLCLK"), + PINCTRL_PIN(275, "DDPB_CTRLDATA"), + PINCTRL_PIN(276, "DDPC_CTRLCLK"), + PINCTRL_PIN(277, "DDPC_CTRLDATA"), + PINCTRL_PIN(278, "DDPD_CTRLCLK"), + PINCTRL_PIN(279, "DDPD_CTRLDATA"), + PINCTRL_PIN(280, "M2_SKT2_CFG_0"), + PINCTRL_PIN(281, "M2_SKT2_CFG_1"), + PINCTRL_PIN(282, "M2_SKT2_CFG_2"), + PINCTRL_PIN(283, "M2_SKT2_CFG_3"), + PINCTRL_PIN(284, "SYS_PWROK"), + PINCTRL_PIN(285, "SYS_RESETB"), + PINCTRL_PIN(286, "MLK_RSTB"), + /* GPP_J */ + PINCTRL_PIN(287, "CNV_PA_BLANKING"), + PINCTRL_PIN(288, "CNV_GNSS_FTA"), + PINCTRL_PIN(289, "CNV_GNSS_SYSCK"), + PINCTRL_PIN(290, "CNV_RF_RESET_B"), + PINCTRL_PIN(291, "CNV_BRI_DT"), + PINCTRL_PIN(292, "CNV_BRI_RSP"), + PINCTRL_PIN(293, "CNV_RGI_DT"), + PINCTRL_PIN(294, "CNV_RGI_RSP"), + PINCTRL_PIN(295, "CNV_MFUART2_RXD"), + PINCTRL_PIN(296, "CNV_MFUART2_TXD"), + PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"), + PINCTRL_PIN(298, "A4WP_PRESENT"), +}; + +static const struct intel_padgroup cnlh_community0_gpps[] = { + CNL_GPP(0, 0, 24), /* GPP_A */ + CNL_GPP(1, 25, 50), /* GPP_B */ +}; + +static const struct intel_padgroup cnlh_community1_gpps[] = { + CNL_GPP(0, 51, 74), /* GPP_C */ + CNL_GPP(1, 75, 98), /* GPP_D */ + CNL_GPP(2, 99, 106), /* GPP_G */ + CNL_GPP(3, 107, 114), /* AZA */ + CNL_GPP(4, 115, 146), /* vGPIO_0 */ + CNL_GPP(5, 147, 154), /* vGPIO_1 */ +}; + +static const struct intel_padgroup cnlh_community3_gpps[] = { + CNL_GPP(0, 155, 178), /* GPP_K */ + CNL_GPP(1, 179, 202), /* GPP_H */ + CNL_GPP(2, 203, 215), /* GPP_E */ + CNL_GPP(3, 216, 239), /* GPP_F */ + CNL_GPP(4, 240, 248), /* SPI */ +}; + +static const struct intel_padgroup cnlh_community4_gpps[] = { + CNL_GPP(0, 249, 259), /* CPU */ + CNL_GPP(1, 260, 268), /* JTAG */ + CNL_GPP(2, 269, 286), /* GPP_I */ + CNL_GPP(3, 287, 298), /* GPP_J */ +}; + +static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; +static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 }; +static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 }; + +static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 }; +static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 }; +static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 }; + +static const unsigned int cnlh_i2c0_pins[] = { 67, 68 }; +static const unsigned int cnlh_i2c1_pins[] = { 69, 70 }; +static const unsigned int cnlh_i2c2_pins[] = { 88, 89 }; +static const unsigned int cnlh_i2c3_pins[] = { 79, 98 }; + +static const struct intel_pingroup cnlh_groups[] = { + PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1), + PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1), + PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3), + PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1), + PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1), + PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1), + PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3), + PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2), +}; + +static const char * const cnlh_spi0_groups[] = { "spi0_grp" }; +static const char * const cnlh_spi1_groups[] = { "spi1_grp" }; +static const char * const cnlh_spi2_groups[] = { "spi2_grp" }; +static const char * const cnlh_uart0_groups[] = { "uart0_grp" }; +static const char * const cnlh_uart1_groups[] = { "uart1_grp" }; +static const char * const cnlh_uart2_groups[] = { "uart2_grp" }; +static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" }; +static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" }; +static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" }; +static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" }; + +static const struct intel_function cnlh_functions[] = { + FUNCTION("spi0", cnlh_spi0_groups), + FUNCTION("spi1", cnlh_spi1_groups), + FUNCTION("spi2", cnlh_spi2_groups), + FUNCTION("uart0", cnlh_uart0_groups), + FUNCTION("uart1", cnlh_uart1_groups), + FUNCTION("uart2", cnlh_uart2_groups), + FUNCTION("i2c0", cnlh_i2c0_groups), + FUNCTION("i2c1", cnlh_i2c1_groups), + FUNCTION("i2c2", cnlh_i2c2_groups), + FUNCTION("i2c3", cnlh_i2c3_groups), +}; + +static const struct intel_community cnlh_communities[] = { + CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps), + CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps), + /* + * ACPI MMIO resources are returned in reverse order for + * communities 3 and 4. + */ + CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps), + CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps), +}; + +static const struct intel_pinctrl_soc_data cnlh_soc_data = { + .pins = cnlh_pins, + .npins = ARRAY_SIZE(cnlh_pins), + .groups = cnlh_groups, + .ngroups = ARRAY_SIZE(cnlh_groups), + .functions = cnlh_functions, + .nfunctions = ARRAY_SIZE(cnlh_functions), + .communities = cnlh_communities, + .ncommunities = ARRAY_SIZE(cnlh_communities), +}; + /* Cannon Lake-LP */ static const struct pinctrl_pin_desc cnllp_pins[] = { /* GPP_A */ @@ -403,6 +824,7 @@ static const struct intel_pinctrl_soc_data cnllp_soc_data = { }; static const struct acpi_device_id cnl_pinctrl_acpi_match[] = { + { "INT3450", (kernel_ulong_t)&cnlh_soc_data }, { "INT34BB", (kernel_ulong_t)&cnllp_soc_data }, { }, }; diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c new file mode 100644 index 000000000000..4500880240f2 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -0,0 +1,302 @@ +/* + * Intel Denverton SoC pinctrl/GPIO driver + * + * Copyright (C) 2017, Intel Corporation + * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define DNV_PAD_OWN 0x020 +#define DNV_HOSTSW_OWN 0x0C0 +#define DNV_PADCFGLOCK 0x090 +#define DNV_GPI_IE 0x120 + +#define DNV_GPP(n, s, e) \ + { \ + .reg_num = (n), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + } + +#define DNV_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = DNV_PAD_OWN, \ + .padcfglock_offset = DNV_PADCFGLOCK, \ + .hostown_offset = DNV_HOSTSW_OWN, \ + .ie_offset = DNV_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +static const struct pinctrl_pin_desc dnv_pins[] = { + /* North ALL */ + PINCTRL_PIN(0, "GBE0_SDP0"), + PINCTRL_PIN(1, "GBE1_SDP0"), + PINCTRL_PIN(2, "GBE0_SDP1"), + PINCTRL_PIN(3, "GBE1_SDP1"), + PINCTRL_PIN(4, "GBE0_SDP2"), + PINCTRL_PIN(5, "GBE1_SDP2"), + PINCTRL_PIN(6, "GBE0_SDP3"), + PINCTRL_PIN(7, "GBE1_SDP3"), + PINCTRL_PIN(8, "GBE2_LED0"), + PINCTRL_PIN(9, "GBE2_LED1"), + PINCTRL_PIN(10, "GBE0_I2C_CLK"), + PINCTRL_PIN(11, "GBE0_I2C_DATA"), + PINCTRL_PIN(12, "GBE1_I2C_CLK"), + PINCTRL_PIN(13, "GBE1_I2C_DATA"), + PINCTRL_PIN(14, "NCSI_RXD0"), + PINCTRL_PIN(15, "NCSI_CLK_IN"), + PINCTRL_PIN(16, "NCSI_RXD1"), + PINCTRL_PIN(17, "NCSI_CRS_DV"), + PINCTRL_PIN(18, "NCSI_ARB_IN"), + PINCTRL_PIN(19, "NCSI_TX_EN"), + PINCTRL_PIN(20, "NCSI_TXD0"), + PINCTRL_PIN(21, "NCSI_TXD1"), + PINCTRL_PIN(22, "NCSI_ARB_OUT"), + PINCTRL_PIN(23, "GBE0_LED0"), + PINCTRL_PIN(24, "GBE0_LED1"), + PINCTRL_PIN(25, "GBE1_LED0"), + PINCTRL_PIN(26, "GBE1_LED1"), + PINCTRL_PIN(27, "GPIO_0"), + PINCTRL_PIN(28, "PCIE_CLKREQ0_N"), + PINCTRL_PIN(29, "PCIE_CLKREQ1_N"), + PINCTRL_PIN(30, "PCIE_CLKREQ2_N"), + PINCTRL_PIN(31, "PCIE_CLKREQ3_N"), + PINCTRL_PIN(32, "PCIE_CLKREQ4_N"), + PINCTRL_PIN(33, "GPIO_1"), + PINCTRL_PIN(34, "GPIO_2"), + PINCTRL_PIN(35, "SVID_ALERT_N"), + PINCTRL_PIN(36, "SVID_DATA"), + PINCTRL_PIN(37, "SVID_CLK"), + PINCTRL_PIN(38, "THERMTRIP_N"), + PINCTRL_PIN(39, "PROCHOT_N"), + PINCTRL_PIN(40, "MEMHOT_N"), + /* South DFX */ + PINCTRL_PIN(41, "DFX_PORT_CLK0"), + PINCTRL_PIN(42, "DFX_PORT_CLK1"), + PINCTRL_PIN(43, "DFX_PORT0"), + PINCTRL_PIN(44, "DFX_PORT1"), + PINCTRL_PIN(45, "DFX_PORT2"), + PINCTRL_PIN(46, "DFX_PORT3"), + PINCTRL_PIN(47, "DFX_PORT4"), + PINCTRL_PIN(48, "DFX_PORT5"), + PINCTRL_PIN(49, "DFX_PORT6"), + PINCTRL_PIN(50, "DFX_PORT7"), + PINCTRL_PIN(51, "DFX_PORT8"), + PINCTRL_PIN(52, "DFX_PORT9"), + PINCTRL_PIN(53, "DFX_PORT10"), + PINCTRL_PIN(54, "DFX_PORT11"), + PINCTRL_PIN(55, "DFX_PORT12"), + PINCTRL_PIN(56, "DFX_PORT13"), + PINCTRL_PIN(57, "DFX_PORT14"), + PINCTRL_PIN(58, "DFX_PORT15"), + /* South GPP0 */ + PINCTRL_PIN(59, "GPIO_12"), + PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"), + PINCTRL_PIN(61, "PCIE_CLKREQ5_N"), + PINCTRL_PIN(62, "PCIE_CLKREQ6_N"), + PINCTRL_PIN(63, "PCIE_CLKREQ7_N"), + PINCTRL_PIN(64, "UART0_RXD"), + PINCTRL_PIN(65, "UART0_TXD"), + PINCTRL_PIN(66, "SMB5_GBE_CLK"), + PINCTRL_PIN(67, "SMB5_GBE_DATA"), + PINCTRL_PIN(68, "ERROR2_N"), + PINCTRL_PIN(69, "ERROR1_N"), + PINCTRL_PIN(70, "ERROR0_N"), + PINCTRL_PIN(71, "IERR_N"), + PINCTRL_PIN(72, "MCERR_N"), + PINCTRL_PIN(73, "SMB0_LEG_CLK"), + PINCTRL_PIN(74, "SMB0_LEG_DATA"), + PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"), + PINCTRL_PIN(76, "SMB1_HOST_DATA"), + PINCTRL_PIN(77, "SMB1_HOST_CLK"), + PINCTRL_PIN(78, "SMB2_PECI_DATA"), + PINCTRL_PIN(79, "SMB2_PECI_CLK"), + PINCTRL_PIN(80, "SMB4_CSME0_DATA"), + PINCTRL_PIN(81, "SMB4_CSME0_CLK"), + PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"), + PINCTRL_PIN(83, "USB_OC0_N"), + PINCTRL_PIN(84, "FLEX_CLK_SE0"), + PINCTRL_PIN(85, "FLEX_CLK_SE1"), + PINCTRL_PIN(86, "GPIO_4"), + PINCTRL_PIN(87, "GPIO_5"), + PINCTRL_PIN(88, "GPIO_6"), + PINCTRL_PIN(89, "GPIO_7"), + PINCTRL_PIN(90, "SATA0_LED_N"), + PINCTRL_PIN(91, "SATA1_LED_N"), + PINCTRL_PIN(92, "SATA_PDETECT0"), + PINCTRL_PIN(93, "SATA_PDETECT1"), + PINCTRL_PIN(94, "SATA0_SDOUT"), + PINCTRL_PIN(95, "SATA1_SDOUT"), + PINCTRL_PIN(96, "UART1_RXD"), + PINCTRL_PIN(97, "UART1_TXD"), + PINCTRL_PIN(98, "GPIO_8"), + PINCTRL_PIN(99, "GPIO_9"), + PINCTRL_PIN(100, "TCK"), + PINCTRL_PIN(101, "TRST_N"), + PINCTRL_PIN(102, "TMS"), + PINCTRL_PIN(103, "TDI"), + PINCTRL_PIN(104, "TDO"), + PINCTRL_PIN(105, "CX_PRDY_N"), + PINCTRL_PIN(106, "CX_PREQ_N"), + PINCTRL_PIN(107, "CTBTRIGINOUT"), + PINCTRL_PIN(108, "CTBTRIGOUT"), + PINCTRL_PIN(109, "DFX_SPARE2"), + PINCTRL_PIN(110, "DFX_SPARE3"), + PINCTRL_PIN(111, "DFX_SPARE4"), + /* South GPP1 */ + PINCTRL_PIN(112, "SUSPWRDNACK"), + PINCTRL_PIN(113, "PMU_SUSCLK"), + PINCTRL_PIN(114, "ADR_TRIGGER"), + PINCTRL_PIN(115, "PMU_SLP_S45_N"), + PINCTRL_PIN(116, "PMU_SLP_S3_N"), + PINCTRL_PIN(117, "PMU_WAKE_N"), + PINCTRL_PIN(118, "PMU_PWRBTN_N"), + PINCTRL_PIN(119, "PMU_RESETBUTTON_N"), + PINCTRL_PIN(120, "PMU_PLTRST_N"), + PINCTRL_PIN(121, "SUS_STAT_N"), + PINCTRL_PIN(122, "SLP_S0IX_N"), + PINCTRL_PIN(123, "SPI_CS0_N"), + PINCTRL_PIN(124, "SPI_CS1_N"), + PINCTRL_PIN(125, "SPI_MOSI_IO0"), + PINCTRL_PIN(126, "SPI_MISO_IO1"), + PINCTRL_PIN(127, "SPI_IO2"), + PINCTRL_PIN(128, "SPI_IO3"), + PINCTRL_PIN(129, "SPI_CLK"), + PINCTRL_PIN(130, "SPI_CLK_LOOPBK"), + PINCTRL_PIN(131, "ESPI_IO0"), + PINCTRL_PIN(132, "ESPI_IO1"), + PINCTRL_PIN(133, "ESPI_IO2"), + PINCTRL_PIN(134, "ESPI_IO3"), + PINCTRL_PIN(135, "ESPI_CS0_N"), + PINCTRL_PIN(136, "ESPI_CLK"), + PINCTRL_PIN(137, "ESPI_RST_N"), + PINCTRL_PIN(138, "ESPI_ALRT0_N"), + PINCTRL_PIN(139, "GPIO_10"), + PINCTRL_PIN(140, "GPIO_11"), + PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"), + PINCTRL_PIN(142, "EMMC_CMD"), + PINCTRL_PIN(143, "EMMC_STROBE"), + PINCTRL_PIN(144, "EMMC_CLK"), + PINCTRL_PIN(145, "EMMC_D0"), + PINCTRL_PIN(146, "EMMC_D1"), + PINCTRL_PIN(147, "EMMC_D2"), + PINCTRL_PIN(148, "EMMC_D3"), + PINCTRL_PIN(149, "EMMC_D4"), + PINCTRL_PIN(150, "EMMC_D5"), + PINCTRL_PIN(151, "EMMC_D6"), + PINCTRL_PIN(152, "EMMC_D7"), + PINCTRL_PIN(153, "GPIO_3"), +}; + +static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 }; +static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 }; +static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 }; +static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 }; +static const unsigned int dnv_uart2_modes[] = { 1, 1, 2, 2 }; +static const unsigned int dnv_emmc_pins[] = { + 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, +}; + +static const struct intel_pingroup dnv_groups[] = { + PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes), + PIN_GROUP("uart1_grp", dnv_uart1_pins, 1), + PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes), + PIN_GROUP("emmc_grp", dnv_emmc_pins, 1), +}; + +static const char * const dnv_uart0_groups[] = { "uart0_grp" }; +static const char * const dnv_uart1_groups[] = { "uart1_grp" }; +static const char * const dnv_uart2_groups[] = { "uart2_grp" }; +static const char * const dnv_emmc_groups[] = { "emmc_grp" }; + +static const struct intel_function dnv_functions[] = { + FUNCTION("uart0", dnv_uart0_groups), + FUNCTION("uart1", dnv_uart1_groups), + FUNCTION("uart2", dnv_uart2_groups), + FUNCTION("emmc", dnv_emmc_groups), +}; + +static const struct intel_padgroup dnv_north_gpps[] = { + DNV_GPP(0, 0, 31), /* North ALL_0 */ + DNV_GPP(1, 32, 40), /* North ALL_1 */ +}; + +static const struct intel_padgroup dnv_south_gpps[] = { + DNV_GPP(0, 41, 58), /* South DFX */ + DNV_GPP(1, 59, 90), /* South GPP0_0 */ + DNV_GPP(2, 91, 111), /* South GPP0_1 */ + DNV_GPP(3, 112, 143), /* South GPP1_0 */ + DNV_GPP(4, 144, 153), /* South GPP1_1 */ +}; + +static const struct intel_community dnv_communities[] = { + DNV_COMMUNITY(0, 0, 40, dnv_north_gpps), + DNV_COMMUNITY(1, 41, 153, dnv_south_gpps), +}; + +static const struct intel_pinctrl_soc_data dnv_soc_data = { + .pins = dnv_pins, + .npins = ARRAY_SIZE(dnv_pins), + .groups = dnv_groups, + .ngroups = ARRAY_SIZE(dnv_groups), + .functions = dnv_functions, + .nfunctions = ARRAY_SIZE(dnv_functions), + .communities = dnv_communities, + .ncommunities = ARRAY_SIZE(dnv_communities), +}; + +static int dnv_pinctrl_probe(struct platform_device *pdev) +{ + return intel_pinctrl_probe(pdev, &dnv_soc_data); +} + +static const struct dev_pm_ops dnv_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static const struct acpi_device_id dnv_pinctrl_acpi_match[] = { + { "INTC3000" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match); + +static struct platform_driver dnv_pinctrl_driver = { + .probe = dnv_pinctrl_probe, + .driver = { + .name = "denverton-pinctrl", + .acpi_match_table = dnv_pinctrl_acpi_match, + .pm = &dnv_pinctrl_pm_ops, + }, +}; + +static int __init dnv_pinctrl_init(void) +{ + return platform_driver_register(&dnv_pinctrl_driver); +} +subsys_initcall(dnv_pinctrl_init); + +static void __exit dnv_pinctrl_exit(void) +{ + platform_driver_unregister(&dnv_pinctrl_driver); +} +module_exit(dnv_pinctrl_exit); + +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 6dc1096d3d34..71df0f70b61f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -751,33 +751,38 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); void __iomem *reg; + u32 padcfg0; reg = intel_get_padcfg(pctrl, offset, PADCFG0); if (!reg) return -EINVAL; - return !!(readl(reg) & PADCFG0_GPIORXSTATE); + padcfg0 = readl(reg); + if (!(padcfg0 & PADCFG0_GPIOTXDIS)) + return !!(padcfg0 & PADCFG0_GPIOTXSTATE); + + return !!(padcfg0 & PADCFG0_GPIORXSTATE); } static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); + unsigned long flags; void __iomem *reg; + u32 padcfg0; reg = intel_get_padcfg(pctrl, offset, PADCFG0); - if (reg) { - unsigned long flags; - u32 padcfg0; + if (!reg) + return; - raw_spin_lock_irqsave(&pctrl->lock, flags); - padcfg0 = readl(reg); - if (value) - padcfg0 |= PADCFG0_GPIOTXSTATE; - else - padcfg0 &= ~PADCFG0_GPIOTXSTATE; - writel(padcfg0, reg); - raw_spin_unlock_irqrestore(&pctrl->lock, flags); - } + raw_spin_lock_irqsave(&pctrl->lock, flags); + padcfg0 = readl(reg); + if (value) + padcfg0 |= PADCFG0_GPIOTXSTATE; + else + padcfg0 &= ~PADCFG0_GPIOTXSTATE; + writel(padcfg0, reg); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) @@ -1035,6 +1040,7 @@ static struct irq_chip intel_gpio_irqchip = { .irq_unmask = intel_gpio_irq_unmask, .irq_set_type = intel_gpio_irq_type, .irq_set_wake = intel_gpio_irq_wake, + .flags = IRQCHIP_MASK_ON_SUSPEND, }; static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c new file mode 100644 index 000000000000..14d56ea6cfdc --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c @@ -0,0 +1,343 @@ +/* + * Intel Lewisburg pinctrl/GPIO driver + * + * Copyright (C) 2017, Intel Corporation + * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define LBG_PAD_OWN 0x020 +#define LBG_PADCFGLOCK 0x060 +#define LBG_HOSTSW_OWN 0x080 +#define LBG_GPI_IE 0x110 + +#define LBG_COMMUNITY(b, s, e) \ + { \ + .barno = (b), \ + .padown_offset = LBG_PAD_OWN, \ + .padcfglock_offset = LBG_PADCFGLOCK, \ + .hostown_offset = LBG_HOSTSW_OWN, \ + .ie_offset = LBG_GPI_IE, \ + .gpp_size = 24, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + } + +static const struct pinctrl_pin_desc lbg_pins[] = { + /* GPP_A */ + PINCTRL_PIN(0, "RCINB"), + PINCTRL_PIN(1, "LAD_0"), + PINCTRL_PIN(2, "LAD_1"), + PINCTRL_PIN(3, "LAD_2"), + PINCTRL_PIN(4, "LAD_3"), + PINCTRL_PIN(5, "LFRAMEB"), + PINCTRL_PIN(6, "SERIRQ"), + PINCTRL_PIN(7, "PIRQAB"), + PINCTRL_PIN(8, "CLKRUNB"), + PINCTRL_PIN(9, "CLKOUT_LPC_0"), + PINCTRL_PIN(10, "CLKOUT_LPC_1"), + PINCTRL_PIN(11, "PMEB"), + PINCTRL_PIN(12, "BM_BUSYB"), + PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(14, "ESPI_RESETB"), + PINCTRL_PIN(15, "SUSACKB"), + PINCTRL_PIN(16, "CLKOUT_LPC_2"), + PINCTRL_PIN(17, "GPP_A_17"), + PINCTRL_PIN(18, "GPP_A_18"), + PINCTRL_PIN(19, "GPP_A_19"), + PINCTRL_PIN(20, "GPP_A_20"), + PINCTRL_PIN(21, "GPP_A_21"), + PINCTRL_PIN(22, "GPP_A_22"), + PINCTRL_PIN(23, "GPP_A_23"), + /* GPP_B */ + PINCTRL_PIN(24, "CORE_VID_0"), + PINCTRL_PIN(25, "CORE_VID_1"), + PINCTRL_PIN(26, "VRALERTB"), + PINCTRL_PIN(27, "CPU_GP_2"), + PINCTRL_PIN(28, "CPU_GP_3"), + PINCTRL_PIN(29, "SRCCLKREQB_0"), + PINCTRL_PIN(30, "SRCCLKREQB_1"), + PINCTRL_PIN(31, "SRCCLKREQB_2"), + PINCTRL_PIN(32, "SRCCLKREQB_3"), + PINCTRL_PIN(33, "SRCCLKREQB_4"), + PINCTRL_PIN(34, "SRCCLKREQB_5"), + PINCTRL_PIN(35, "GPP_B_11"), + PINCTRL_PIN(36, "GLB_RST_WARN_N"), + PINCTRL_PIN(37, "PLTRSTB"), + PINCTRL_PIN(38, "SPKR"), + PINCTRL_PIN(39, "GPP_B_15"), + PINCTRL_PIN(40, "GPP_B_16"), + PINCTRL_PIN(41, "GPP_B_17"), + PINCTRL_PIN(42, "GPP_B_18"), + PINCTRL_PIN(43, "GPP_B_19"), + PINCTRL_PIN(44, "GPP_B_20"), + PINCTRL_PIN(45, "GPP_B_21"), + PINCTRL_PIN(46, "GPP_B_22"), + PINCTRL_PIN(47, "SML1ALERTB"), + /* GPP_F */ + PINCTRL_PIN(48, "SATAXPCIE_3"), + PINCTRL_PIN(49, "SATAXPCIE_4"), + PINCTRL_PIN(50, "SATAXPCIE_5"), + PINCTRL_PIN(51, "SATAXPCIE_6"), + PINCTRL_PIN(52, "SATAXPCIE_7"), + PINCTRL_PIN(53, "SATA_DEVSLP_3"), + PINCTRL_PIN(54, "SATA_DEVSLP_4"), + PINCTRL_PIN(55, "SATA_DEVSLP_5"), + PINCTRL_PIN(56, "SATA_DEVSLP_6"), + PINCTRL_PIN(57, "SATA_DEVSLP_7"), + PINCTRL_PIN(58, "SATA_SCLOCK"), + PINCTRL_PIN(59, "SATA_SLOAD"), + PINCTRL_PIN(60, "SATA_SDATAOUT1"), + PINCTRL_PIN(61, "SATA_SDATAOUT0"), + PINCTRL_PIN(62, "SSATA_LEDB"), + PINCTRL_PIN(63, "USB2_OCB_4"), + PINCTRL_PIN(64, "USB2_OCB_5"), + PINCTRL_PIN(65, "USB2_OCB_6"), + PINCTRL_PIN(66, "USB2_OCB_7"), + PINCTRL_PIN(67, "GBE_SMBUS_CLK"), + PINCTRL_PIN(68, "GBE_SMBDATA"), + PINCTRL_PIN(69, "GBE_SMBALRTN"), + PINCTRL_PIN(70, "SSATA_SCLOCK"), + PINCTRL_PIN(71, "SSATA_SLOAD"), + /* GPP_C */ + PINCTRL_PIN(72, "SMBCLK"), + PINCTRL_PIN(73, "SMBDATA"), + PINCTRL_PIN(74, "SMBALERTB"), + PINCTRL_PIN(75, "SML0CLK"), + PINCTRL_PIN(76, "SML0DATA"), + PINCTRL_PIN(77, "SML0ALERTB"), + PINCTRL_PIN(78, "SML1CLK"), + PINCTRL_PIN(79, "SML1DATA"), + PINCTRL_PIN(80, "GPP_C_8"), + PINCTRL_PIN(81, "GPP_C_9"), + PINCTRL_PIN(82, "GPP_C_10"), + PINCTRL_PIN(83, "GPP_C_11"), + PINCTRL_PIN(84, "GPP_C_12"), + PINCTRL_PIN(85, "GPP_C_13"), + PINCTRL_PIN(86, "GPP_C_14"), + PINCTRL_PIN(87, "GPP_C_15"), + PINCTRL_PIN(88, "GPP_C_16"), + PINCTRL_PIN(89, "GPP_C_17"), + PINCTRL_PIN(90, "GPP_C_18"), + PINCTRL_PIN(91, "GPP_C_19"), + PINCTRL_PIN(92, "GPP_C_20"), + PINCTRL_PIN(93, "GPP_C_21"), + PINCTRL_PIN(94, "GPP_C_22"), + PINCTRL_PIN(95, "GPP_C_23"), + /* GPP_D */ + PINCTRL_PIN(96, "GPP_D_0"), + PINCTRL_PIN(97, "GPP_D_1"), + PINCTRL_PIN(98, "GPP_D_2"), + PINCTRL_PIN(99, "GPP_D_3"), + PINCTRL_PIN(100, "GPP_D_4"), + PINCTRL_PIN(101, "SSP0_SFRM"), + PINCTRL_PIN(102, "SSP0_TXD"), + PINCTRL_PIN(103, "SSP0_RXD"), + PINCTRL_PIN(104, "SSP0_SCLK"), + PINCTRL_PIN(105, "SSATA_DEVSLP_3"), + PINCTRL_PIN(106, "SSATA_DEVSLP_4"), + PINCTRL_PIN(107, "SSATA_DEVSLP_5"), + PINCTRL_PIN(108, "SSATA_SDATAOUT1"), + PINCTRL_PIN(109, "SML0BCLK_SML0BCLKIE"), + PINCTRL_PIN(110, "SML0BDATA_SML0BDATAIE"), + PINCTRL_PIN(111, "SSATA_SDATAOUT0"), + PINCTRL_PIN(112, "SML0BALERTB_SML0BALERTBIE"), + PINCTRL_PIN(113, "DMIC_CLK_1"), + PINCTRL_PIN(114, "DMIC_DATA_1"), + PINCTRL_PIN(115, "DMIC_CLK_0"), + PINCTRL_PIN(116, "DMIC_DATA_0"), + PINCTRL_PIN(117, "IE_UART_RXD"), + PINCTRL_PIN(118, "IE_UART_TXD"), + PINCTRL_PIN(119, "GPP_D_23"), + /* GPP_E */ + PINCTRL_PIN(120, "SATAXPCIE_0"), + PINCTRL_PIN(121, "SATAXPCIE_1"), + PINCTRL_PIN(122, "SATAXPCIE_2"), + PINCTRL_PIN(123, "CPU_GP_0"), + PINCTRL_PIN(124, "SATA_DEVSLP_0"), + PINCTRL_PIN(125, "SATA_DEVSLP_1"), + PINCTRL_PIN(126, "SATA_DEVSLP_2"), + PINCTRL_PIN(127, "CPU_GP_1"), + PINCTRL_PIN(128, "SATA_LEDB"), + PINCTRL_PIN(129, "USB2_OCB_0"), + PINCTRL_PIN(130, "USB2_OCB_1"), + PINCTRL_PIN(131, "USB2_OCB_2"), + PINCTRL_PIN(132, "USB2_OCB_3"), + /* GPP_I */ + PINCTRL_PIN(133, "GBE_TDO"), + PINCTRL_PIN(134, "GBE_TCK"), + PINCTRL_PIN(135, "GBE_TMS"), + PINCTRL_PIN(136, "GBE_TDI"), + PINCTRL_PIN(137, "DO_RESET_INB"), + PINCTRL_PIN(138, "DO_RESET_OUTB"), + PINCTRL_PIN(139, "RESET_DONE"), + PINCTRL_PIN(140, "GBE_TRST_N"), + PINCTRL_PIN(141, "GBE_PCI_DIS"), + PINCTRL_PIN(142, "GBE_LAN_DIS"), + PINCTRL_PIN(143, "GPP_I_10"), + PINCTRL_PIN(144, "GPIO_RCOMP_3P3"), + /* GPP_J */ + PINCTRL_PIN(145, "GBE_LED_0_0"), + PINCTRL_PIN(146, "GBE_LED_0_1"), + PINCTRL_PIN(147, "GBE_LED_1_0"), + PINCTRL_PIN(148, "GBE_LED_1_1"), + PINCTRL_PIN(149, "GBE_LED_2_0"), + PINCTRL_PIN(150, "GBE_LED_2_1"), + PINCTRL_PIN(151, "GBE_LED_3_0"), + PINCTRL_PIN(152, "GBE_LED_3_1"), + PINCTRL_PIN(153, "GBE_SCL_0"), + PINCTRL_PIN(154, "GBE_SDA_0"), + PINCTRL_PIN(155, "GBE_SCL_1"), + PINCTRL_PIN(156, "GBE_SDA_1"), + PINCTRL_PIN(157, "GBE_SCL_2"), + PINCTRL_PIN(158, "GBE_SDA_2"), + PINCTRL_PIN(159, "GBE_SCL_3"), + PINCTRL_PIN(160, "GBE_SDA_3"), + PINCTRL_PIN(161, "GBE_SDP_0_0"), + PINCTRL_PIN(162, "GBE_SDP_0_1"), + PINCTRL_PIN(163, "GBE_SDP_1_0"), + PINCTRL_PIN(164, "GBE_SDP_1_1"), + PINCTRL_PIN(165, "GBE_SDP_2_0"), + PINCTRL_PIN(166, "GBE_SDP_2_1"), + PINCTRL_PIN(167, "GBE_SDP_3_0"), + PINCTRL_PIN(168, "GBE_SDP_3_1"), + /* GPP_K */ + PINCTRL_PIN(169, "GBE_RMIICLK"), + PINCTRL_PIN(170, "GBE_RMII_TXD_0"), + PINCTRL_PIN(171, "GBE_RMII_TXD_1"), + PINCTRL_PIN(172, "GBE_RMII_TX_EN"), + PINCTRL_PIN(173, "GBE_RMII_CRS_DV"), + PINCTRL_PIN(174, "GBE_RMII_RXD_0"), + PINCTRL_PIN(175, "GBE_RMII_RXD_1"), + PINCTRL_PIN(176, "GBE_RMII_RX_ER"), + PINCTRL_PIN(177, "GBE_RMII_ARBIN"), + PINCTRL_PIN(178, "GBE_RMII_ARB_OUT"), + PINCTRL_PIN(179, "PE_RST_N"), + PINCTRL_PIN(180, "GPIO_RCOMP_1P8_3P3"), + /* GPP_G */ + PINCTRL_PIN(181, "FAN_TACH_0"), + PINCTRL_PIN(182, "FAN_TACH_1"), + PINCTRL_PIN(183, "FAN_TACH_2"), + PINCTRL_PIN(184, "FAN_TACH_3"), + PINCTRL_PIN(185, "FAN_TACH_4"), + PINCTRL_PIN(186, "FAN_TACH_5"), + PINCTRL_PIN(187, "FAN_TACH_6"), + PINCTRL_PIN(188, "FAN_TACH_7"), + PINCTRL_PIN(189, "FAN_PWM_0"), + PINCTRL_PIN(190, "FAN_PWM_1"), + PINCTRL_PIN(191, "FAN_PWM_2"), + PINCTRL_PIN(192, "FAN_PWM_3"), + PINCTRL_PIN(193, "GSXDOUT"), + PINCTRL_PIN(194, "GSXSLOAD"), + PINCTRL_PIN(195, "GSXDIN"), + PINCTRL_PIN(196, "GSXSRESETB"), + PINCTRL_PIN(197, "GSXCLK"), + PINCTRL_PIN(198, "ADR_COMPLETE"), + PINCTRL_PIN(199, "NMIB"), + PINCTRL_PIN(200, "SMIB"), + PINCTRL_PIN(201, "SSATA_DEVSLP_0"), + PINCTRL_PIN(202, "SSATA_DEVSLP_1"), + PINCTRL_PIN(203, "SSATA_DEVSLP_2"), + PINCTRL_PIN(204, "SSATAXPCIE0_SSATAGP0"), + /* GPP_H */ + PINCTRL_PIN(205, "SRCCLKREQB_6"), + PINCTRL_PIN(206, "SRCCLKREQB_7"), + PINCTRL_PIN(207, "SRCCLKREQB_8"), + PINCTRL_PIN(208, "SRCCLKREQB_9"), + PINCTRL_PIN(209, "SRCCLKREQB_10"), + PINCTRL_PIN(210, "SRCCLKREQB_11"), + PINCTRL_PIN(211, "SRCCLKREQB_12"), + PINCTRL_PIN(212, "SRCCLKREQB_13"), + PINCTRL_PIN(213, "SRCCLKREQB_14"), + PINCTRL_PIN(214, "SRCCLKREQB_15"), + PINCTRL_PIN(215, "SML2CLK"), + PINCTRL_PIN(216, "SML2DATA"), + PINCTRL_PIN(217, "SML2ALERTB"), + PINCTRL_PIN(218, "SML3CLK"), + PINCTRL_PIN(219, "SML3DATA"), + PINCTRL_PIN(220, "SML3ALERTB"), + PINCTRL_PIN(221, "SML4CLK"), + PINCTRL_PIN(222, "SML4DATA"), + PINCTRL_PIN(223, "SML4ALERTB"), + PINCTRL_PIN(224, "SSATAXPCIE1_SSATAGP1"), + PINCTRL_PIN(225, "SSATAXPCIE2_SSATAGP2"), + PINCTRL_PIN(226, "SSATAXPCIE3_SSATAGP3"), + PINCTRL_PIN(227, "SSATAXPCIE4_SSATAGP4"), + PINCTRL_PIN(228, "SSATAXPCIE5_SSATAGP5"), + /* GPP_L */ + PINCTRL_PIN(229, "VISA2CH0_D0"), + PINCTRL_PIN(230, "VISA2CH0_D1"), + PINCTRL_PIN(231, "VISA2CH0_D2"), + PINCTRL_PIN(232, "VISA2CH0_D3"), + PINCTRL_PIN(233, "VISA2CH0_D4"), + PINCTRL_PIN(234, "VISA2CH0_D5"), + PINCTRL_PIN(235, "VISA2CH0_D6"), + PINCTRL_PIN(236, "VISA2CH0_D7"), + PINCTRL_PIN(237, "VISA2CH0_CLK"), + PINCTRL_PIN(238, "VISA2CH1_D0"), + PINCTRL_PIN(239, "VISA2CH1_D1"), + PINCTRL_PIN(240, "VISA2CH1_D2"), + PINCTRL_PIN(241, "VISA2CH1_D3"), + PINCTRL_PIN(242, "VISA2CH1_D4"), + PINCTRL_PIN(243, "VISA2CH1_D5"), + PINCTRL_PIN(244, "VISA2CH1_D6"), + PINCTRL_PIN(245, "VISA2CH1_D7"), + PINCTRL_PIN(246, "VISA2CH1_CLK"), +}; + +static const struct intel_community lbg_communities[] = { + LBG_COMMUNITY(0, 0, 71), + LBG_COMMUNITY(1, 72, 132), + LBG_COMMUNITY(3, 133, 144), + LBG_COMMUNITY(4, 145, 180), + LBG_COMMUNITY(5, 181, 246), +}; + +static const struct intel_pinctrl_soc_data lbg_soc_data = { + .pins = lbg_pins, + .npins = ARRAY_SIZE(lbg_pins), + .communities = lbg_communities, + .ncommunities = ARRAY_SIZE(lbg_communities), +}; + +static int lbg_pinctrl_probe(struct platform_device *pdev) +{ + return intel_pinctrl_probe(pdev, &lbg_soc_data); +} + +static const struct dev_pm_ops lbg_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static const struct acpi_device_id lbg_pinctrl_acpi_match[] = { + { "INT3536" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match); + +static struct platform_driver lbg_pinctrl_driver = { + .probe = lbg_pinctrl_probe, + .driver = { + .name = "lewisburg-pinctrl", + .acpi_match_table = lbg_pinctrl_acpi_match, + .pm = &lbg_pinctrl_pm_ops, + }, +}; + +module_platform_driver(lbg_pinctrl_driver); + +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h index f90642078c31..1035df49301f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h @@ -223,6 +223,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = { MTK_EINT_FUNCTION(0, 0), MTK_FUNCTION(0, "GPIO22"), MTK_FUNCTION(1, "UCTS0"), + /* MT7623 take function 2 as PCIE0_PERST_N */ + MTK_FUNCTION(2, "PCIE0_PERST_N"), MTK_FUNCTION(3, "KCOL3"), MTK_FUNCTION(4, "CONN_DSP_JDO"), MTK_FUNCTION(5, "EXT_FRAME_SYNC"), @@ -235,6 +237,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = { MTK_EINT_FUNCTION(0, 1), MTK_FUNCTION(0, "GPIO23"), MTK_FUNCTION(1, "URTS0"), + /* MT7623 take function 2 as PCIE1_PERST_N */ + MTK_FUNCTION(2, "PCIE1_PERST_N"), MTK_FUNCTION(3, "KCOL2"), MTK_FUNCTION(4, "CONN_MCU_TDO"), MTK_FUNCTION(5, "EXT_FRAME_SYNC"), @@ -247,6 +251,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = { MTK_EINT_FUNCTION(0, 2), MTK_FUNCTION(0, "GPIO24"), MTK_FUNCTION(1, "UCTS1"), + /* MT7623 take function 2 as PCIE2_PERST_N */ + MTK_FUNCTION(2, "PCIE2_PERST_N"), MTK_FUNCTION(3, "KCOL1"), MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"), MTK_FUNCTION(7, "DBG_MON_A[28]"), @@ -308,6 +314,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = { MTK_FUNCTION(3, "KROW0"), MTK_FUNCTION(4, "CONN_MCU_TMS"), MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"), + /* MT7623 take function 6 as PCIE2_PERST_N */ + MTK_FUNCTION(6, "PCIE2_PERST_N"), MTK_FUNCTION(7, "DBG_MON_A[23]"), MTK_FUNCTION(14, "PCIE2_PERST_N") ), @@ -1787,6 +1795,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = { MTK_FUNCTION(0, "GPIO208"), MTK_FUNCTION(1, "AUD_EXT_CK1"), MTK_FUNCTION(2, "PWM0"), + /* MT7623 take function 3 as PCIE0_PERST_N */ + MTK_FUNCTION(3, "PCIE0_PERST_N"), MTK_FUNCTION(4, "ANT_SEL5"), MTK_FUNCTION(5, "DISP_PWM"), MTK_FUNCTION(7, "DBG_MON_A[31]"), @@ -1799,6 +1809,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = { MTK_FUNCTION(0, "GPIO209"), MTK_FUNCTION(1, "AUD_EXT_CK2"), MTK_FUNCTION(2, "MSDC1_WP"), + /* MT7623 take function 3 as PCIE1_PERST_N */ + MTK_FUNCTION(3, "PCIE1_PERST_N"), MTK_FUNCTION(5, "PWM1"), MTK_FUNCTION(7, "DBG_MON_A[32]"), MTK_FUNCTION(11, "PCIE1_PERST_N") diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 0c6d7812d6fd..b8b6ab072cd0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -190,14 +190,14 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { "mii", "mii_err"), }; -const struct armada_37xx_pin_data armada_37xx_pin_nb = { +static const struct armada_37xx_pin_data armada_37xx_pin_nb = { .nr_pins = 36, .name = "GPIO1", .groups = armada_37xx_nb_groups, .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), }; -const struct armada_37xx_pin_data armada_37xx_pin_sb = { +static const struct armada_37xx_pin_data armada_37xx_pin_sb = { .nr_pins = 30, .name = "GPIO2", .groups = armada_37xx_sb_groups, @@ -254,7 +254,7 @@ static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, return -ENOTSUPP; } -static struct pinconf_ops armada_37xx_pinconf_ops = { +static const struct pinconf_ops armada_37xx_pinconf_ops = { .is_generic = true, .pin_config_group_get = armada_37xx_pin_config_group_get, .pin_config_group_set = armada_37xx_pin_config_group_set, diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index f95001bc1d58..b32c0d602024 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -647,7 +647,7 @@ static inline void abx500_gpio_dbg_show_one(struct seq_file *s, #define abx500_gpio_dbg_show NULL #endif -static struct gpio_chip abx500gpio_chip = { +static const struct gpio_chip abx500gpio_chip = { .label = "abx500-gpio", .owner = THIS_MODULE, .request = gpiochip_generic_request, diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index d318ca055489..a53f1a9b1ed2 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1078,7 +1078,7 @@ static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) - return base; + return ERR_CAST(base); nmk_chip->addr = base; clk = clk_get(&gpio_pdev->dev, NULL); diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index fc0c230aa11f..8eaa25c3384f 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -47,6 +47,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false), PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), + PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), }; @@ -178,6 +179,7 @@ static const struct pinconf_generic_params dt_params[] = { { "output-high", PIN_CONFIG_OUTPUT, 1, }, { "output-low", PIN_CONFIG_OUTPUT, 0, }, { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, }; @@ -316,16 +318,15 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev, if (ret < 0) { /* EINVAL=missing, which is fine since it's optional */ if (ret != -EINVAL) - dev_err(dev, "%s: could not parse property function\n", - of_node_full_name(np)); + dev_err(dev, "%pOF: could not parse property function\n", + np); function = NULL; } ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); if (ret < 0) { - dev_err(dev, "%s: could not parse node property\n", - of_node_full_name(np)); + dev_err(dev, "%pOF: could not parse node property\n", np); return ret; } diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index 7fc417e4ae96..d3fe14394b73 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -37,7 +37,7 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev) return 0; } -int pinconf_validate_map(struct pinctrl_map const *map, int i) +int pinconf_validate_map(const struct pinctrl_map *map, int i) { if (!map->data.configs.group_or_pin) { pr_err("failed to register map %s (%d): no group/pin given\n", @@ -106,7 +106,7 @@ unlock: return ret; } -int pinconf_map_to_setting(struct pinctrl_map const *map, +int pinconf_map_to_setting(const struct pinctrl_map *map, struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; @@ -143,11 +143,11 @@ int pinconf_map_to_setting(struct pinctrl_map const *map, return 0; } -void pinconf_free_setting(struct pinctrl_setting const *setting) +void pinconf_free_setting(const struct pinctrl_setting *setting) { } -int pinconf_apply_setting(struct pinctrl_setting const *setting) +int pinconf_apply_setting(const struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinconf_ops *ops = pctldev->desc->confops; @@ -205,7 +205,7 @@ int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, const struct pinconf_ops *ops; ops = pctldev->desc->confops; - if (!ops) + if (!ops || !ops->pin_config_set) return -ENOTSUPP; return ops->pin_config_set(pctldev, pin, configs, nconfigs); @@ -235,7 +235,7 @@ static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, } } -void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) +void pinconf_show_map(struct seq_file *s, const struct pinctrl_map *map) { struct pinctrl_dev *pctldev; @@ -259,7 +259,7 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) } void pinconf_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting) + const struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index bf8aff9abf32..6c722505f893 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -14,11 +14,11 @@ #ifdef CONFIG_PINCONF int pinconf_check_ops(struct pinctrl_dev *pctldev); -int pinconf_validate_map(struct pinctrl_map const *map, int i); -int pinconf_map_to_setting(struct pinctrl_map const *map, +int pinconf_validate_map(const struct pinctrl_map *map, int i); +int pinconf_map_to_setting(const struct pinctrl_map *map, struct pinctrl_setting *setting); -void pinconf_free_setting(struct pinctrl_setting const *setting); -int pinconf_apply_setting(struct pinctrl_setting const *setting); +void pinconf_free_setting(const struct pinctrl_setting *setting); +int pinconf_apply_setting(const struct pinctrl_setting *setting); int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, size_t nconfigs); @@ -39,22 +39,22 @@ static inline int pinconf_check_ops(struct pinctrl_dev *pctldev) return 0; } -static inline int pinconf_validate_map(struct pinctrl_map const *map, int i) +static inline int pinconf_validate_map(const struct pinctrl_map *map, int i) { return 0; } -static inline int pinconf_map_to_setting(struct pinctrl_map const *map, +static inline int pinconf_map_to_setting(const struct pinctrl_map *map, struct pinctrl_setting *setting) { return 0; } -static inline void pinconf_free_setting(struct pinctrl_setting const *setting) +static inline void pinconf_free_setting(const struct pinctrl_setting *setting) { } -static inline int pinconf_apply_setting(struct pinctrl_setting const *setting) +static inline int pinconf_apply_setting(const struct pinctrl_setting *setting) { return 0; } @@ -69,21 +69,21 @@ static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, #if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS) -void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map); +void pinconf_show_map(struct seq_file *s, const struct pinctrl_map *map); void pinconf_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting); + const struct pinctrl_setting *setting); void pinconf_init_device_debugfs(struct dentry *devroot, struct pinctrl_dev *pctldev); #else static inline void pinconf_show_map(struct seq_file *s, - struct pinctrl_map const *map) + const struct pinctrl_map *map) { } static inline void pinconf_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting) + const struct pinctrl_setting *setting) { } diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c index 54569a7eac59..56aa181084ac 100644 --- a/drivers/pinctrl/pinctrl-adi2.c +++ b/drivers/pinctrl/pinctrl-adi2.c @@ -612,7 +612,7 @@ static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static struct pinctrl_ops adi_pctrl_ops = { +static const struct pinctrl_ops adi_pctrl_ops = { .get_groups_count = adi_get_groups_count, .get_group_name = adi_get_group_name, .get_group_pins = adi_get_group_pins, @@ -696,7 +696,7 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops adi_pinmux_ops = { +static const struct pinmux_ops adi_pinmux_ops = { .set_mux = adi_pinmux_set, .get_functions_count = adi_pinmux_get_funcs_count, .get_function_name = adi_pinmux_get_func_name, diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index e6779d4352a2..38af1ec2df0c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -760,8 +760,8 @@ static int amd_gpio_probe(struct platform_device *pdev) irq_base = platform_get_irq(pdev, 0); if (irq_base < 0) { - dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); - return -EINVAL; + dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base); + return irq_base; } gpio_dev->pdev = pdev; diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c index 357516d524bd..e33781cd0a05 100644 --- a/drivers/pinctrl/pinctrl-artpec6.c +++ b/drivers/pinctrl/pinctrl-artpec6.c @@ -445,7 +445,7 @@ static unsigned int artpec6_pconf_drive_field_to_mA(int field) } } -static struct pinctrl_ops artpec6_pctrl_ops = { +static const struct pinctrl_ops artpec6_pctrl_ops = { .get_group_pins = artpec6_get_group_pins, .get_groups_count = artpec6_get_groups_count, .get_group_name = artpec6_get_group_name, diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index dc8591543dee..b1ca838dd80a 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -494,8 +494,8 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); if (ret < 0) { - dev_err(pctldev->dev, "%s: could not parse node property\n", - of_node_full_name(np)); + dev_err(pctldev->dev, "%pOF: could not parse node property\n", + np); return ret; } @@ -504,8 +504,7 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, num_pins = pins->length / sizeof(u32); if (!num_pins) { - dev_err(pctldev->dev, "no pins found in node %s\n", - of_node_full_name(np)); + dev_err(pctldev->dev, "no pins found in node %pOF\n", np); ret = -EINVAL; goto exit; } @@ -584,8 +583,8 @@ static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, if (ret < 0) { pinctrl_utils_free_map(pctldev, *map, *num_maps); - dev_err(pctldev->dev, "can't create maps for node %s\n", - np_config->full_name); + dev_err(pctldev->dev, "can't create maps for node %pOF\n", + np_config); } return ret; diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index 741b39eaeb8b..ac155e7d3412 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -387,7 +387,7 @@ int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, return 0; } -static struct gpio_chip u300_gpio_chip = { +static const struct gpio_chip u300_gpio_chip = { .label = "u300-gpio-chip", .owner = THIS_MODULE, .request = gpiochip_generic_request, diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c index 639a57ecc7c2..ce269ced4d49 100644 --- a/drivers/pinctrl/pinctrl-digicolor.c +++ b/drivers/pinctrl/pinctrl-digicolor.c @@ -79,7 +79,7 @@ static int dc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, return 0; } -static struct pinctrl_ops dc_pinctrl_ops = { +static const struct pinctrl_ops dc_pinctrl_ops = { .get_groups_count = dc_get_groups_count, .get_group_name = dc_get_group_name, .get_group_pins = dc_get_group_pins, @@ -161,7 +161,7 @@ static int dc_pmx_request_gpio(struct pinctrl_dev *pcdev, return 0; } -static struct pinmux_ops dc_pmxops = { +static const struct pinmux_ops dc_pmxops = { .get_functions_count = dc_get_functions_count, .get_function_name = dc_get_fname, .get_function_groups = dc_get_groups, diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c new file mode 100644 index 000000000000..39e6221e7100 --- /dev/null +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -0,0 +1,2359 @@ +/* + * Driver for the Gemini pin controller + * + * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> + * + * This is a group-only pin controller. + */ +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/regmap.h> + +#include "pinctrl-utils.h" + +#define DRIVER_NAME "pinctrl-gemini" + +/** + * @dev: a pointer back to containing device + * @virtbase: the offset to the controller in virtual memory + * @map: regmap to access registers + * @is_3512: whether the SoC/package is the 3512 variant + * @is_3516: whether the SoC/package is the 3516 variant + * @flash_pin: whether the flash pin (extended pins for parallel + * flash) is set + */ +struct gemini_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct regmap *map; + bool is_3512; + bool is_3516; + bool flash_pin; +}; + +/** + * struct gemini_pin_group - describes a Gemini pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @mask: bits to clear to enable this when doing pin muxing + * @value: bits to set to enable this when doing pin muxing + */ +struct gemini_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + u32 mask; + u32 value; +}; + +/* + * Global Miscellaneous Control Register + * This register controls all Gemini pad/pin multiplexing + * + * It is a tricky register though: + * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot + * be brought back online, so it means permanent disablement of the + * corresponding pads. + * - For the bits named *_DISABLE, once you enable something, it cannot be + * DISABLED again. So you select a flash configuration once, and then + * you are stuck with it. + */ +#define GLOBAL_WORD_ID 0x00 +#define GLOBAL_STATUS 0x04 +#define GLOBAL_STATUS_FLPIN BIT(20) +#define GLOBAL_MISC_CTRL 0x30 +#define TVC_CLK_PAD_ENABLE BIT(20) +#define PCI_CLK_PAD_ENABLE BIT(17) +#define LPC_CLK_PAD_ENABLE BIT(16) +#define TVC_PADS_ENABLE BIT(9) +#define SSP_PADS_ENABLE BIT(8) +#define LCD_PADS_ENABLE BIT(7) +#define LPC_PADS_ENABLE BIT(6) +#define PCI_PADS_ENABLE BIT(5) +#define IDE_PADS_ENABLE BIT(4) +#define DRAM_PADS_POWERDOWN BIT(3) +#define NAND_PADS_DISABLE BIT(2) +#define PFLASH_PADS_DISABLE BIT(1) +#define SFLASH_PADS_DISABLE BIT(0) +#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) +#define PADS_MAXBIT 20 + +/* Ordered by bit index */ +static const char * const gemini_padgroups[] = { + "serial flash", + "parallel flash", + "NAND flash", + "DRAM", + "IDE", + "PCI", + "LPC", + "LCD", + "SSP", + "TVC", + NULL, NULL, NULL, NULL, NULL, NULL, + "LPC CLK", + "PCI CLK", + NULL, NULL, + "TVC CLK", +}; + +static const struct pinctrl_pin_desc gemini_3512_pins[] = { + /* Row A */ + PINCTRL_PIN(0, "A1 VREF CTRL"), + PINCTRL_PIN(1, "A2 VCC2IO CTRL"), + PINCTRL_PIN(2, "A3 DRAM CK"), + PINCTRL_PIN(3, "A4 DRAM CK N"), + PINCTRL_PIN(4, "A5 DRAM A5"), + PINCTRL_PIN(5, "A6 DRAM CKE"), + PINCTRL_PIN(6, "A7 DRAM DQ11"), + PINCTRL_PIN(7, "A8 DRAM DQ0"), + PINCTRL_PIN(8, "A9 DRAM DQ5"), + PINCTRL_PIN(9, "A10 DRAM DQ6"), + PINCTRL_PIN(10, "A11 DRAM DRAM VREF"), + PINCTRL_PIN(11, "A12 DRAM BA1"), + PINCTRL_PIN(12, "A13 DRAM A2"), + PINCTRL_PIN(13, "A14 PCI GNT1 N"), + PINCTRL_PIN(14, "A15 PCI REQ9 N"), + PINCTRL_PIN(15, "A16 PCI REQ2 N"), + PINCTRL_PIN(16, "A17 PCI REQ3 N"), + PINCTRL_PIN(17, "A18 PCI AD31"), + /* Row B */ + PINCTRL_PIN(18, "B1 VCCK CTRL"), + PINCTRL_PIN(19, "B2 PWR EN"), + PINCTRL_PIN(20, "B3 RTC CLKI"), + PINCTRL_PIN(21, "B4 DRAM A4"), + PINCTRL_PIN(22, "B5 DRAM A6"), + PINCTRL_PIN(23, "B6 DRAM A12"), + PINCTRL_PIN(24, "B7 DRAM DQS1"), + PINCTRL_PIN(25, "B8 DRAM DQ15"), + PINCTRL_PIN(26, "B9 DRAM DQ4"), + PINCTRL_PIN(27, "B10 DRAM DQS0"), + PINCTRL_PIN(28, "B11 DRAM WE N"), + PINCTRL_PIN(29, "B12 DRAM A10"), + PINCTRL_PIN(30, "B13 DRAM A3"), + PINCTRL_PIN(31, "B14 PCI GNT0 N"), + PINCTRL_PIN(32, "B15 PCI GNT3 N"), + PINCTRL_PIN(33, "B16 PCI REQ1 N"), + PINCTRL_PIN(34, "B17 PCI AD30"), + PINCTRL_PIN(35, "B18 PCI AD29"), + /* Row C */ + PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */ + PINCTRL_PIN(37, "C2 XTALI"), + PINCTRL_PIN(38, "C3 PWR BTN"), + PINCTRL_PIN(39, "C4 RTC CLKO"), + PINCTRL_PIN(40, "C5 DRAM A7"), + PINCTRL_PIN(41, "C6 DRAM A11"), + PINCTRL_PIN(42, "C7 DRAM DQ10"), + PINCTRL_PIN(43, "C8 DRAM DQ14"), + PINCTRL_PIN(44, "C9 DRAM DQ3"), + PINCTRL_PIN(45, "C10 DRAM DQ7"), + PINCTRL_PIN(46, "C11 DRAM CAS N"), + PINCTRL_PIN(47, "C12 DRAM A0"), + PINCTRL_PIN(48, "C13 PCI INT0 N"), + PINCTRL_PIN(49, "C14 EXT RESET N"), + PINCTRL_PIN(50, "C15 PCI GNT2 N"), + PINCTRL_PIN(51, "C16 PCI AD28"), + PINCTRL_PIN(52, "C17 PCI AD27"), + PINCTRL_PIN(53, "C18 PCI AD26"), + /* Row D */ + PINCTRL_PIN(54, "D1 AVCCKHA"), + PINCTRL_PIN(55, "D2 AGNDIOHA"), + PINCTRL_PIN(56, "D3 XTALO"), + PINCTRL_PIN(57, "D4 AVCC3IOHA"), + PINCTRL_PIN(58, "D5 DRAM A8"), + PINCTRL_PIN(59, "D6 DRAM A9"), + PINCTRL_PIN(60, "D7 DRAM DQ9"), + PINCTRL_PIN(61, "D8 DRAM DQ13"), + PINCTRL_PIN(62, "D9 DRAM DQ2"), + PINCTRL_PIN(63, "D10 DRAM A13"), + PINCTRL_PIN(64, "D11 DRAM RAS N"), + PINCTRL_PIN(65, "D12 DRAM A1"), + PINCTRL_PIN(66, "D13 PCI INTC N"), + PINCTRL_PIN(67, "D14 PCI CLK"), + PINCTRL_PIN(68, "D15 PCI AD25"), + PINCTRL_PIN(69, "D16 PCI AD24"), + PINCTRL_PIN(70, "D17 PCI CBE3 N"), + PINCTRL_PIN(71, "D18 PCI AD23"), + /* Row E */ + PINCTRL_PIN(72, "E1 AVCC3IOHA"), + PINCTRL_PIN(73, "E2 EBG"), + PINCTRL_PIN(74, "E3 AVCC3IOHB"), + PINCTRL_PIN(75, "E4 REXT"), + PINCTRL_PIN(76, "E5 GND"), + PINCTRL_PIN(77, "E6 DRAM DQM1"), + PINCTRL_PIN(78, "E7 DRAM DQ8"), + PINCTRL_PIN(79, "E8 DRAM DQ12"), + PINCTRL_PIN(80, "E9 DRAM DQ1"), + PINCTRL_PIN(81, "E10 DRAM DQM0"), + PINCTRL_PIN(82, "E11 DRAM BA0"), + PINCTRL_PIN(83, "E12 PCI INTA N"), + PINCTRL_PIN(84, "E13 PCI INTB N"), + PINCTRL_PIN(85, "E14 GND"), + PINCTRL_PIN(86, "E15 PCI AD22"), + PINCTRL_PIN(87, "E16 PCI AD21"), + PINCTRL_PIN(88, "E17 PCI AD20"), + PINCTRL_PIN(89, "E18 PCI AD19"), + /* Row F */ + PINCTRL_PIN(90, "F1 SATA0 RXDP"), + PINCTRL_PIN(91, "F2 SATA0 RXDN"), + PINCTRL_PIN(92, "F3 AGNDK 0"), + PINCTRL_PIN(93, "F4 AVCC3 S"), + PINCTRL_PIN(94, "F5 AVCCK P"), + PINCTRL_PIN(95, "F6 GND"), + PINCTRL_PIN(96, "F7 VCC2IOHA 2"), + PINCTRL_PIN(97, "F8 VCC2IOHA 2"), + PINCTRL_PIN(98, "F9 V1"), + PINCTRL_PIN(99, "F10 V1"), + PINCTRL_PIN(100, "F11 VCC2IOHA 2"), + PINCTRL_PIN(101, "F12 VCC2IOHA 2"), + PINCTRL_PIN(102, "F13 GND"), + PINCTRL_PIN(103, "F14 PCI AD18"), + PINCTRL_PIN(104, "F15 PCI AD17"), + PINCTRL_PIN(105, "F16 PCI AD16"), + PINCTRL_PIN(106, "F17 PCI CBE2 N"), + PINCTRL_PIN(107, "F18 PCI FRAME N"), + /* Row G */ + PINCTRL_PIN(108, "G1 SATA0 TXDP"), + PINCTRL_PIN(109, "G2 SATA0 TXDN"), + PINCTRL_PIN(110, "G3 AGNDK 1"), + PINCTRL_PIN(111, "G4 AVCCK 0"), + PINCTRL_PIN(112, "G5 TEST CLKOUT"), + PINCTRL_PIN(113, "G6 AGND"), + PINCTRL_PIN(114, "G7 GND"), + PINCTRL_PIN(115, "G8 VCC2IOHA 2"), + PINCTRL_PIN(116, "G9 V1"), + PINCTRL_PIN(117, "G10 V1"), + PINCTRL_PIN(118, "G11 VCC2IOHA 2"), + PINCTRL_PIN(119, "G12 GND"), + PINCTRL_PIN(120, "G13 VCC3IOHA"), + PINCTRL_PIN(121, "G14 PCI IRDY N"), + PINCTRL_PIN(122, "G15 PCI TRDY N"), + PINCTRL_PIN(123, "G16 PCI DEVSEL N"), + PINCTRL_PIN(124, "G17 PCI STOP N"), + PINCTRL_PIN(125, "G18 PCI PAR"), + /* Row H */ + PINCTRL_PIN(126, "H1 SATA1 TXDP"), + PINCTRL_PIN(127, "H2 SATA1 TXDN"), + PINCTRL_PIN(128, "H3 AGNDK 2"), + PINCTRL_PIN(129, "H4 AVCCK 1"), + PINCTRL_PIN(130, "H5 AVCCK S"), + PINCTRL_PIN(131, "H6 AVCCKHB"), + PINCTRL_PIN(132, "H7 AGND"), + PINCTRL_PIN(133, "H8 GND"), + PINCTRL_PIN(134, "H9 GND"), + PINCTRL_PIN(135, "H10 GND"), + PINCTRL_PIN(136, "H11 GND"), + PINCTRL_PIN(137, "H12 VCC3IOHA"), + PINCTRL_PIN(138, "H13 VCC3IOHA"), + PINCTRL_PIN(139, "H14 PCI CBE1 N"), + PINCTRL_PIN(140, "H15 PCI AD15"), + PINCTRL_PIN(141, "H16 PCI AD14"), + PINCTRL_PIN(142, "H17 PCI AD13"), + PINCTRL_PIN(143, "H18 PCI AD12"), + /* Row J (for some reason I is skipped) */ + PINCTRL_PIN(144, "J1 SATA1 RXDP"), + PINCTRL_PIN(145, "J2 SATA1 RXDN"), + PINCTRL_PIN(146, "J3 AGNDK 3"), + PINCTRL_PIN(147, "J4 AVCCK 2"), + PINCTRL_PIN(148, "J5 IDE DA1"), + PINCTRL_PIN(149, "J6 V1"), + PINCTRL_PIN(150, "J7 V1"), + PINCTRL_PIN(151, "J8 GND"), + PINCTRL_PIN(152, "J9 GND"), + PINCTRL_PIN(153, "J10 GND"), + PINCTRL_PIN(154, "J11 GND"), + PINCTRL_PIN(155, "J12 V1"), + PINCTRL_PIN(156, "J13 V1"), + PINCTRL_PIN(157, "J14 PCI AD11"), + PINCTRL_PIN(158, "J15 PCI AD10"), + PINCTRL_PIN(159, "J16 PCI AD9"), + PINCTRL_PIN(160, "J17 PCI AD8"), + PINCTRL_PIN(161, "J18 PCI CBE0 N"), + /* Row K */ + PINCTRL_PIN(162, "K1 IDE CS1 N"), + PINCTRL_PIN(163, "K2 IDE CS0 N"), + PINCTRL_PIN(164, "K3 AVCCK 3"), + PINCTRL_PIN(165, "K4 IDE DA2"), + PINCTRL_PIN(166, "K5 IDE DA0"), + PINCTRL_PIN(167, "K6 V1"), + PINCTRL_PIN(168, "K7 V1"), + PINCTRL_PIN(169, "K8 GND"), + PINCTRL_PIN(170, "K9 GND"), + PINCTRL_PIN(171, "K10 GND"), + PINCTRL_PIN(172, "K11 GND"), + PINCTRL_PIN(173, "K12 V1"), + PINCTRL_PIN(174, "K13 V1"), + PINCTRL_PIN(175, "K14 PCI AD3"), + PINCTRL_PIN(176, "K15 PCI AD4"), + PINCTRL_PIN(177, "K16 PCI AD5"), + PINCTRL_PIN(178, "K17 PCI AD6"), + PINCTRL_PIN(179, "K18 PCI AD7"), + /* Row L */ + PINCTRL_PIN(180, "L1 IDE INTRQ"), + PINCTRL_PIN(181, "L2 IDE DMACK N"), + PINCTRL_PIN(182, "L3 IDE IORDY"), + PINCTRL_PIN(183, "L4 IDE DIOR N"), + PINCTRL_PIN(184, "L5 IDE DIOW N"), + PINCTRL_PIN(185, "L6 VCC3IOHA"), + PINCTRL_PIN(186, "L7 VCC3IOHA"), + PINCTRL_PIN(187, "L8 GND"), + PINCTRL_PIN(188, "L9 GND"), + PINCTRL_PIN(189, "L10 GND"), + PINCTRL_PIN(190, "L11 GND"), + PINCTRL_PIN(191, "L12 VCC3IOHA"), + PINCTRL_PIN(192, "L13 VCC3IOHA"), + PINCTRL_PIN(193, "L14 GPIO0 30"), + PINCTRL_PIN(194, "L15 GPIO0 31"), + PINCTRL_PIN(195, "L16 PCI AD0"), + PINCTRL_PIN(196, "L17 PCI AD1"), + PINCTRL_PIN(197, "L18 PCI AD2"), + /* Row M */ + PINCTRL_PIN(198, "M1 IDE DMARQ"), + PINCTRL_PIN(199, "M2 IDE DD15"), + PINCTRL_PIN(200, "M3 IDE DD0"), + PINCTRL_PIN(201, "M4 IDE DD14"), + PINCTRL_PIN(202, "M5 IDE DD1"), + PINCTRL_PIN(203, "M6 VCC3IOHA"), + PINCTRL_PIN(204, "M7 GND"), + PINCTRL_PIN(205, "M8 VCC2IOHA 1"), + PINCTRL_PIN(206, "M9 V1"), + PINCTRL_PIN(207, "M10 V1"), + PINCTRL_PIN(208, "M11 VCC3IOHA"), + PINCTRL_PIN(209, "M12 GND"), + PINCTRL_PIN(210, "M13 VCC3IOHA"), + PINCTRL_PIN(211, "M14 GPIO0 25"), + PINCTRL_PIN(212, "M15 GPIO0 26"), + PINCTRL_PIN(213, "M16 GPIO0 27"), + PINCTRL_PIN(214, "M17 GPIO0 28"), + PINCTRL_PIN(215, "M18 GPIO0 29"), + /* Row N */ + PINCTRL_PIN(216, "N1 IDE DD13"), + PINCTRL_PIN(217, "N2 IDE DD2"), + PINCTRL_PIN(218, "N3 IDE DD12"), + PINCTRL_PIN(219, "N4 IDE DD3"), + PINCTRL_PIN(220, "N5 IDE DD11"), + PINCTRL_PIN(221, "N6 GND"), + PINCTRL_PIN(222, "N7 VCC2IOHA 1"), + PINCTRL_PIN(223, "N8 VCC2IOHA 1"), + PINCTRL_PIN(224, "N9 V1"), + PINCTRL_PIN(225, "N10 V1"), + PINCTRL_PIN(226, "N11 VCC3IOHA"), + PINCTRL_PIN(227, "N12 VCC3IOHA"), + PINCTRL_PIN(228, "N13 GND"), + PINCTRL_PIN(229, "N14 GPIO0 20"), + PINCTRL_PIN(230, "N15 GPIO0 21"), + PINCTRL_PIN(231, "N16 GPIO0 22"), + PINCTRL_PIN(232, "N17 GPIO0 23"), + PINCTRL_PIN(233, "N18 GPIO0 24"), + /* Row P (for some reason O is skipped) */ + PINCTRL_PIN(234, "P1 IDE DD4"), + PINCTRL_PIN(235, "P2 IDE DD10"), + PINCTRL_PIN(236, "P3 IDE DD5"), + PINCTRL_PIN(237, "P4 IDE DD9"), + PINCTRL_PIN(238, "P5 GND"), + PINCTRL_PIN(239, "P6 USB XSCO"), + PINCTRL_PIN(240, "P7 GMAC0 TXD3"), + PINCTRL_PIN(241, "P8 GMAC0 TXEN"), + PINCTRL_PIN(242, "P9 GMAC0 RXD2"), + PINCTRL_PIN(243, "P10 GMAC1 TXC"), + PINCTRL_PIN(244, "P11 GMAC1 RXD1"), + PINCTRL_PIN(245, "P12 MODE SEL 1"), + PINCTRL_PIN(246, "P13 GPIO1 28"), + PINCTRL_PIN(247, "P14 GND"), + PINCTRL_PIN(248, "P15 GPIO0 5"), + PINCTRL_PIN(249, "P16 GPIO0 17"), + PINCTRL_PIN(250, "P17 GPIO0 18"), + PINCTRL_PIN(251, "P18 GPIO0 19"), + /* Row R (for some reason Q us skipped) */ + PINCTRL_PIN(252, "R1 IDE DD6"), + PINCTRL_PIN(253, "R2 IDE DD8"), + PINCTRL_PIN(254, "R3 IDE DD7"), + PINCTRL_PIN(255, "R4 IDE RESET N"), + PINCTRL_PIN(256, "R5 ICE0 DBGACK"), + PINCTRL_PIN(257, "R6 USB XSCI"), + PINCTRL_PIN(258, "R7 GMAC0 TXD2"), + PINCTRL_PIN(259, "R8 GMAC0 RXDV"), + PINCTRL_PIN(260, "R9 GMAC0 RXD3"), + PINCTRL_PIN(261, "R10 GMAC1 TXD0"), + PINCTRL_PIN(262, "R11 GMAC1 RXD0"), + PINCTRL_PIN(263, "R12 MODE SEL 0"), + PINCTRL_PIN(264, "R13 MODE SEL 3"), + PINCTRL_PIN(265, "R14 GPIO0 0"), + PINCTRL_PIN(266, "R15 GPIO0 4"), + PINCTRL_PIN(267, "R16 GPIO0 9"), + PINCTRL_PIN(268, "R17 GPIO0 15"), + PINCTRL_PIN(269, "R18 GPIO0 16"), + /* Row T (for some reason S is skipped) */ + PINCTRL_PIN(270, "T1 ICE0 DBGRQ"), + PINCTRL_PIN(271, "T2 ICE0 IDO"), + PINCTRL_PIN(272, "T3 ICE0 ICK"), + PINCTRL_PIN(273, "T4 ICE0 IMS"), + PINCTRL_PIN(274, "T5 ICE0 IDI"), + PINCTRL_PIN(275, "T6 USB RREF"), + PINCTRL_PIN(276, "T7 GMAC0 TXD1"), + PINCTRL_PIN(277, "T8 GMAC0 RXC"), + PINCTRL_PIN(278, "T9 GMAC0 CRS"), + PINCTRL_PIN(279, "T10 GMAC1 TXD1"), + PINCTRL_PIN(280, "T11 GMAC1 RXC"), + PINCTRL_PIN(281, "T12 GMAC1 CRS"), + PINCTRL_PIN(282, "T13 EXT CLK"), + PINCTRL_PIN(283, "T14 GPIO1 31"), + PINCTRL_PIN(284, "T15 GPIO0 3"), + PINCTRL_PIN(285, "T16 GPIO0 8"), + PINCTRL_PIN(286, "T17 GPIO0 12"), + PINCTRL_PIN(287, "T18 GPIO0 14"), + /* Row U */ + PINCTRL_PIN(288, "U1 ICE0 IRST N"), + PINCTRL_PIN(289, "U2 USB0 VCCHSRT"), + PINCTRL_PIN(290, "U3 USB0 DP"), + PINCTRL_PIN(291, "U4 USB VCCA U20"), + PINCTRL_PIN(292, "U5 USB1 DP"), + PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"), + PINCTRL_PIN(294, "U7 GMAC0 TXD0"), + PINCTRL_PIN(295, "U8 GMAC0 RXD0"), + PINCTRL_PIN(296, "U9 GMAC1 COL"), + PINCTRL_PIN(297, "U10 GMAC1 TXD2"), + PINCTRL_PIN(298, "U11 GMAC1 RXDV"), + PINCTRL_PIN(299, "U12 GMAC1 RXD3"), + PINCTRL_PIN(300, "U13 MODE SEL 2"), + PINCTRL_PIN(301, "U14 GPIO1 30"), + PINCTRL_PIN(302, "U15 GPIO0 2"), + PINCTRL_PIN(303, "U16 GPIO0 7"), + PINCTRL_PIN(304, "U17 GPIO0 11"), + PINCTRL_PIN(305, "U18 GPIO0 13"), + /* Row V */ + PINCTRL_PIN(306, "V1 USB0 GNDHSRT"), + PINCTRL_PIN(307, "V2 USB0 DM"), + PINCTRL_PIN(308, "V3 USB GNDA U20"), + PINCTRL_PIN(309, "V4 USB1 DM"), + PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"), + PINCTRL_PIN(311, "V6 GMAC0 COL"), + PINCTRL_PIN(312, "V7 GMAC0 TXC"), + PINCTRL_PIN(313, "V8 GMAC0 RXD1"), + PINCTRL_PIN(314, "V9 REF CLK"), + PINCTRL_PIN(315, "V10 GMAC1 TXD3"), + PINCTRL_PIN(316, "V11 GMAC1 TXEN"), + PINCTRL_PIN(317, "V12 GMAC1 RXD2"), + PINCTRL_PIN(318, "V13 M30 CLK"), + PINCTRL_PIN(319, "V14 GPIO1 29"), + PINCTRL_PIN(320, "V15 GPIO0 1"), + PINCTRL_PIN(321, "V16 GPIO0 6"), + PINCTRL_PIN(322, "V17 GPIO0 10"), + PINCTRL_PIN(323, "V18 SYS RESET N"), +}; + + +/* Digital ground */ +static const unsigned int gnd_3512_pins[] = { + 76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169, + 170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247 +}; + +static const unsigned int dram_3512_pins[] = { + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29, + 30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77, + 78, 79, 80, 81, 82 +}; + +static const unsigned int rtc_3512_pins[] = { 57, 20, 39 }; + +static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 }; + +static const unsigned int system_3512_pins[] = { + 318, 264, 300, 245, 263, 282, 314, 323, 49, +}; + +static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 }; + +static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 }; + +static const unsigned int ide_3512_pins[] = { + 162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202, + 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255 +}; + +static const unsigned int sata_3512_pins[] = { + 75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129, + 128, 127, 126, 147, 146, 145, 144, 164 +}; + +static const unsigned int usb_3512_pins[] = { + 306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293 +}; + +/* GMII, ethernet pins */ +static const unsigned int gmii_3512_pins[] = { + 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, + 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 +}; + +static const unsigned int pci_3512_pins[] = { + 13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69, + 70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123, + 124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177, + 178, 179, 195, 196, 197 +}; + +/* + * Apparently the LPC interface is using the PCICLK for the clocking so + * PCI needs to be active at the same time. + */ +static const unsigned int lpc_3512_pins[] = { + 285, /* LPC_LAD[0] */ + 304, /* LPC_SERIRQ */ + 286, /* LPC_LAD[2] */ + 305, /* LPC_LFRAME# */ + 287, /* LPC_LAD[3] */ + 268, /* LPC_LAD[1] */ +}; + +/* Character LCD */ +static const unsigned int lcd_3512_pins[] = { + 262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211 +}; + +static const unsigned int ssp_3512_pins[] = { + 285, /* SSP_97RST# SSP AC97 Reset, active low */ + 304, /* SSP_FSC */ + 286, /* SSP_ECLK */ + 305, /* SSP_TXD */ + 287, /* SSP_RXD */ + 268, /* SSP_SCLK */ +}; + +static const unsigned int uart_rxtx_3512_pins[] = { + 267, /* UART_SIN serial input, RX */ + 322, /* UART_SOUT serial output, TX */ +}; + +static const unsigned int uart_modem_3512_pins[] = { + 285, /* UART_NDCD DCD carrier detect */ + 304, /* UART_NDTR DTR data terminal ready */ + 286, /* UART_NDSR DSR data set ready */ + 305, /* UART_NRTS RTS request to send */ + 287, /* UART_NCTS CTS clear to send */ + 268, /* UART_NRI RI ring indicator */ +}; + +static const unsigned int tvc_3512_pins[] = { + 246, /* TVC_DATA[0] */ + 319, /* TVC_DATA[1] */ + 301, /* TVC_DATA[2] */ + 283, /* TVC_DATA[3] */ + 265, /* TVC_CLK */ + 320, /* TVC_DATA[4] */ + 302, /* TVC_DATA[5] */ + 284, /* TVC_DATA[6] */ + 266, /* TVC_DATA[7] */ +}; + +/* NAND flash pins */ +static const unsigned int nflash_3512_pins[] = { + 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, + 253, 254, 249, 250, 232, 233, 211, 193, 194 +}; + +/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ +static const unsigned int pflash_3512_pins[] = { + 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, + 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, + 214, 215, 193, 194 +}; + +/* + * The parallel flash can be set up in a 26-bit address bus mode exposing + * A[0-15] (A[15] takes the place of ALE), but it has the + * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be + * used at the same time. + */ +static const unsigned int pflash_3512_pins_extended[] = { + 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, + 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, + 214, 215, 193, 194, + /* The extra pins */ + 296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281, + 265, +}; + +/* Serial flash pins CE0, CE1, DI, DO, CK */ +static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 }; + +/* The GPIO0A (0) pin overlap with TVC and extended parallel flash */ +static const unsigned int gpio0a_3512_pins[] = { 265 }; + +/* The GPIO0B (1-4) pins overlap with TVC and ICE */ +static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 }; + +/* The GPIO0C (5-7) pins overlap with ICE */ +static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 }; + +/* The GPIO0D (9,10) pins overlap with UART RX/TX */ +static const unsigned int gpio0d_3512_pins[] = { 267, 322 }; + +/* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */ +static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 }; + +/* The GPIO0F (16) pins overlap with LCD */ +static const unsigned int gpio0f_3512_pins[] = { 269 }; + +/* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */ +static const unsigned int gpio0g_3512_pins[] = { 249, 250 }; + +/* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */ +static const unsigned int gpio0h_3512_pins[] = { 251, 229 }; + +/* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */ +static const unsigned int gpio0i_3512_pins[] = { 230, 231 }; + +/* The GPIO0J (23) pins overlap with all flash */ +static const unsigned int gpio0j_3512_pins[] = { 232 }; + +/* The GPIO0K (24,25) pins overlap with all flash and LCD */ +static const unsigned int gpio0k_3512_pins[] = { 233, 211 }; + +/* The GPIO0L (26-29) pins overlap with parallel flash */ +static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 }; + +/* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */ +static const unsigned int gpio0m_3512_pins[] = { 193, 194 }; + +/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ +static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 }; + +/* The GPIO1B (5-10, 27) pins overlap with just IDE */ +static const unsigned int gpio1b_3512_pins[] = { + 180, 181, 182, 183, 184, 198, 255 +}; + +/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ +static const unsigned int gpio1c_3512_pins[] = { + 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, + 252, 253, 254 +}; + +/* The GPIO1D (28-31) pins overlap with LCD and TVC */ +static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; + +/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ +static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; + +/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ +static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; + +/* The GPIO2C (8-31) pins overlap with PCI */ +static const unsigned int gpio2c_3512_pins[] = { + 17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105, + 140, 141, 142, 143, 157, 158, 159, 160 +}; + +/* Groups for the 3512 SoC/package */ +static const struct gemini_pin_group gemini_3512_pin_groups[] = { + { + .name = "gndgrp", + .pins = gnd_3512_pins, + .num_pins = ARRAY_SIZE(gnd_3512_pins), + }, + { + .name = "dramgrp", + .pins = dram_3512_pins, + .num_pins = ARRAY_SIZE(dram_3512_pins), + .mask = DRAM_PADS_POWERDOWN, + }, + { + .name = "rtcgrp", + .pins = rtc_3512_pins, + .num_pins = ARRAY_SIZE(rtc_3512_pins), + }, + { + .name = "powergrp", + .pins = power_3512_pins, + .num_pins = ARRAY_SIZE(power_3512_pins), + }, + { + .name = "systemgrp", + .pins = system_3512_pins, + .num_pins = ARRAY_SIZE(system_3512_pins), + }, + { + .name = "vcontrolgrp", + .pins = vcontrol_3512_pins, + .num_pins = ARRAY_SIZE(vcontrol_3512_pins), + }, + { + .name = "icegrp", + .pins = ice_3512_pins, + .num_pins = ARRAY_SIZE(ice_3512_pins), + /* Conflict with some GPIO groups */ + }, + { + .name = "idegrp", + .pins = ide_3512_pins, + .num_pins = ARRAY_SIZE(ide_3512_pins), + /* Conflict with all flash usage */ + .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | + PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, + }, + { + .name = "satagrp", + .pins = sata_3512_pins, + .num_pins = ARRAY_SIZE(sata_3512_pins), + }, + { + .name = "usbgrp", + .pins = usb_3512_pins, + .num_pins = ARRAY_SIZE(usb_3512_pins), + }, + { + .name = "gmiigrp", + .pins = gmii_3512_pins, + .num_pins = ARRAY_SIZE(gmii_3512_pins), + }, + { + .name = "pcigrp", + .pins = pci_3512_pins, + .num_pins = ARRAY_SIZE(pci_3512_pins), + /* Conflict only with GPIO2 */ + .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, + }, + { + .name = "lpcgrp", + .pins = lpc_3512_pins, + .num_pins = ARRAY_SIZE(lpc_3512_pins), + /* Conflict with SSP and UART modem pins */ + .mask = SSP_PADS_ENABLE, + .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, + }, + { + .name = "lcdgrp", + .pins = lcd_3512_pins, + .num_pins = ARRAY_SIZE(lcd_3512_pins), + /* Conflict with TVC and ICE */ + .mask = TVC_PADS_ENABLE, + .value = LCD_PADS_ENABLE, + }, + { + .name = "sspgrp", + .pins = ssp_3512_pins, + .num_pins = ARRAY_SIZE(ssp_3512_pins), + /* Conflict with LPC and UART modem pins */ + .mask = LPC_PADS_ENABLE, + .value = SSP_PADS_ENABLE, + }, + { + .name = "uartrxtxgrp", + .pins = uart_rxtx_3512_pins, + .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins), + /* No conflicts except GPIO */ + }, + { + .name = "uartmodemgrp", + .pins = uart_modem_3512_pins, + .num_pins = ARRAY_SIZE(uart_modem_3512_pins), + /* + * Conflict with LPC and SSP, + * so when those are both disabled, modem UART can thrive. + */ + .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, + }, + { + .name = "tvcgrp", + .pins = tvc_3512_pins, + .num_pins = ARRAY_SIZE(tvc_3512_pins), + /* Conflict with character LCD and ICE */ + .mask = LCD_PADS_ENABLE, + .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, + }, + /* + * The construction is done such that it is possible to use a serial + * flash together with a NAND or parallel (NOR) flash, but it is not + * possible to use NAND and parallel flash together. To use serial + * flash with one of the two others, the muxbits need to be flipped + * around before any access. + */ + { + .name = "nflashgrp", + .pins = nflash_3512_pins, + .num_pins = ARRAY_SIZE(nflash_3512_pins), + /* Conflict with IDE, parallel and serial flash */ + .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, + .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, + }, + { + .name = "pflashgrp", + .pins = pflash_3512_pins, + .num_pins = ARRAY_SIZE(pflash_3512_pins), + /* Conflict with IDE, NAND and serial flash */ + .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, + .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, + }, + { + .name = "sflashgrp", + .pins = sflash_3512_pins, + .num_pins = ARRAY_SIZE(sflash_3512_pins), + /* Conflict with IDE, NAND and parallel flash */ + .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, + .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, + }, + { + .name = "gpio0agrp", + .pins = gpio0a_3512_pins, + .num_pins = ARRAY_SIZE(gpio0a_3512_pins), + /* Conflict with TVC */ + .mask = TVC_PADS_ENABLE, + }, + { + .name = "gpio0bgrp", + .pins = gpio0b_3512_pins, + .num_pins = ARRAY_SIZE(gpio0b_3512_pins), + /* Conflict with TVC and ICE */ + .mask = TVC_PADS_ENABLE, + }, + { + .name = "gpio0cgrp", + .pins = gpio0c_3512_pins, + .num_pins = ARRAY_SIZE(gpio0c_3512_pins), + /* Conflict with ICE */ + }, + { + .name = "gpio0dgrp", + .pins = gpio0d_3512_pins, + .num_pins = ARRAY_SIZE(gpio0d_3512_pins), + /* Conflict with UART RX/TX */ + }, + { + .name = "gpio0egrp", + .pins = gpio0e_3512_pins, + .num_pins = ARRAY_SIZE(gpio0e_3512_pins), + /* Conflict with LPC, UART modem pins, SSP */ + .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, + }, + { + .name = "gpio0fgrp", + .pins = gpio0f_3512_pins, + .num_pins = ARRAY_SIZE(gpio0f_3512_pins), + /* Conflict with LCD */ + .mask = LCD_PADS_ENABLE, + }, + { + .name = "gpio0ggrp", + .pins = gpio0g_3512_pins, + .num_pins = ARRAY_SIZE(gpio0g_3512_pins), + /* Conflict with NAND flash */ + .value = NAND_PADS_DISABLE, + }, + { + .name = "gpio0hgrp", + .pins = gpio0h_3512_pins, + .num_pins = ARRAY_SIZE(gpio0h_3512_pins), + /* Conflict with parallel flash */ + .value = PFLASH_PADS_DISABLE, + }, + { + .name = "gpio0igrp", + .pins = gpio0i_3512_pins, + .num_pins = ARRAY_SIZE(gpio0i_3512_pins), + /* Conflict with serial flash */ + .value = SFLASH_PADS_DISABLE, + }, + { + .name = "gpio0jgrp", + .pins = gpio0j_3512_pins, + .num_pins = ARRAY_SIZE(gpio0j_3512_pins), + /* Conflict with all flash */ + .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | + SFLASH_PADS_DISABLE, + }, + { + .name = "gpio0kgrp", + .pins = gpio0k_3512_pins, + .num_pins = ARRAY_SIZE(gpio0k_3512_pins), + /* Conflict with all flash and LCD */ + .mask = LCD_PADS_ENABLE, + .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | + SFLASH_PADS_DISABLE, + }, + { + .name = "gpio0lgrp", + .pins = gpio0l_3512_pins, + .num_pins = ARRAY_SIZE(gpio0l_3512_pins), + /* Conflict with parallel flash */ + .value = PFLASH_PADS_DISABLE, + }, + { + .name = "gpio0mgrp", + .pins = gpio0m_3512_pins, + .num_pins = ARRAY_SIZE(gpio0m_3512_pins), + /* Conflict with parallel and NAND flash */ + .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, + }, + { + .name = "gpio1agrp", + .pins = gpio1a_3512_pins, + .num_pins = ARRAY_SIZE(gpio1a_3512_pins), + /* Conflict with IDE and parallel flash */ + .mask = IDE_PADS_ENABLE, + .value = PFLASH_PADS_DISABLE, + }, + { + .name = "gpio1bgrp", + .pins = gpio1b_3512_pins, + .num_pins = ARRAY_SIZE(gpio1b_3512_pins), + /* Conflict with IDE only */ + .mask = IDE_PADS_ENABLE, + }, + { + .name = "gpio1cgrp", + .pins = gpio1c_3512_pins, + .num_pins = ARRAY_SIZE(gpio1c_3512_pins), + /* Conflict with IDE, parallel and NAND flash */ + .mask = IDE_PADS_ENABLE, + .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, + }, + { + .name = "gpio1dgrp", + .pins = gpio1d_3512_pins, + .num_pins = ARRAY_SIZE(gpio1d_3512_pins), + /* Conflict with LCD and TVC */ + .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE, + }, + { + .name = "gpio2agrp", + .pins = gpio2a_3512_pins, + .num_pins = ARRAY_SIZE(gpio2a_3512_pins), + /* Conflict with GMII and extended parallel flash */ + }, + { + .name = "gpio2bgrp", + .pins = gpio2b_3512_pins, + .num_pins = ARRAY_SIZE(gpio2b_3512_pins), + /* Conflict with GMII, extended parallel flash and LCD */ + .mask = LCD_PADS_ENABLE, + }, + { + .name = "gpio2cgrp", + .pins = gpio2c_3512_pins, + .num_pins = ARRAY_SIZE(gpio2c_3512_pins), + /* Conflict with PCI */ + .mask = PCI_PADS_ENABLE, + }, +}; + +/* Pin names for the pinmux subsystem, 3516 variant */ +static const struct pinctrl_pin_desc gemini_3516_pins[] = { + /* Row A */ + PINCTRL_PIN(0, "A1 AVCC3IOHA"), + PINCTRL_PIN(1, "A2 DRAM CK N"), + PINCTRL_PIN(2, "A3 DRAM CK"), + PINCTRL_PIN(3, "A4 DRAM DQM1"), + PINCTRL_PIN(4, "A5 DRAM DQ9"), + PINCTRL_PIN(5, "A6 DRAM DQ13"), + PINCTRL_PIN(6, "A7 DRAM DQ1"), + PINCTRL_PIN(7, "A8 DRAM DQ2"), + PINCTRL_PIN(8, "A9 DRAM DQ4"), + PINCTRL_PIN(9, "A10 DRAM VREF"), + PINCTRL_PIN(10, "A11 DRAM DQ24"), + PINCTRL_PIN(11, "A12 DRAM DQ28"), + PINCTRL_PIN(12, "A13 DRAM DQ30"), + PINCTRL_PIN(13, "A14 DRAM DQ18"), + PINCTRL_PIN(14, "A15 DRAM DQ21"), + PINCTRL_PIN(15, "A16 DRAM CAS_N"), + PINCTRL_PIN(16, "A17 DRAM BA1"), + PINCTRL_PIN(17, "A18 PCI INTA N"), + PINCTRL_PIN(18, "A19 PCI INTB N"), + PINCTRL_PIN(19, "A20 PCI INTC N"), + /* Row B */ + PINCTRL_PIN(20, "B1 PWR EN"), + PINCTRL_PIN(21, "B2 GND"), + PINCTRL_PIN(22, "B3 RTC CLKO"), + PINCTRL_PIN(23, "B4 DRAM A5"), + PINCTRL_PIN(24, "B5 DRAM A6"), + PINCTRL_PIN(25, "B6 DRAM DQS1"), + PINCTRL_PIN(26, "B7 DRAM DQ11"), + PINCTRL_PIN(27, "B8 DRAM DQ0"), + PINCTRL_PIN(28, "B9 DRAM DQS0"), + PINCTRL_PIN(29, "B10 DRAM DQ7"), + PINCTRL_PIN(30, "B11 DRAM DQS3"), + PINCTRL_PIN(31, "B12 DRAM DQ27"), + PINCTRL_PIN(32, "B13 DRAM DQ31"), + PINCTRL_PIN(33, "B14 DRAM DQ20"), + PINCTRL_PIN(34, "B15 DRAM DQS2"), + PINCTRL_PIN(35, "B16 DRAM WE N"), + PINCTRL_PIN(36, "B17 DRAM A10"), + PINCTRL_PIN(37, "B18 DRAM A2"), + PINCTRL_PIN(38, "B19 GND"), + PINCTRL_PIN(39, "B20 PCI GNT0 N"), + /* Row C */ + PINCTRL_PIN(40, "C1 AGNDIOHA"), + PINCTRL_PIN(41, "C2 XTALI"), + PINCTRL_PIN(42, "C3 GND"), + PINCTRL_PIN(43, "C4 RTC CLKI"), + PINCTRL_PIN(44, "C5 DRAM A12"), + PINCTRL_PIN(45, "C6 DRAM A11"), + PINCTRL_PIN(46, "C7 DRAM DQ8"), + PINCTRL_PIN(47, "C8 DRAM DQ10"), + PINCTRL_PIN(48, "C9 DRAM DQ3"), + PINCTRL_PIN(49, "C10 DRAM DQ6"), + PINCTRL_PIN(50, "C11 DRAM DQM0"), + PINCTRL_PIN(51, "C12 DRAM DQ26"), + PINCTRL_PIN(52, "C13 DRAM DQ16"), + PINCTRL_PIN(53, "C14 DRAM DQ22"), + PINCTRL_PIN(54, "C15 DRAM DQM2"), + PINCTRL_PIN(55, "C16 DRAM BA0"), + PINCTRL_PIN(56, "C17 DRAM A3"), + PINCTRL_PIN(57, "C18 GND"), + PINCTRL_PIN(58, "C19 PCI GNT1 N"), + PINCTRL_PIN(59, "C20 PCI REQ2 N"), + /* Row D */ + PINCTRL_PIN(60, "D1 AVCC3IOAHA"), + PINCTRL_PIN(61, "D2 AVCCKHA"), + PINCTRL_PIN(62, "D3 XTALO"), + PINCTRL_PIN(63, "D4 GND"), + PINCTRL_PIN(64, "D5 CIR RXD"), + PINCTRL_PIN(65, "D6 DRAM A7"), + PINCTRL_PIN(66, "D7 DRAM A4"), + PINCTRL_PIN(67, "D8 DRAM A8"), + PINCTRL_PIN(68, "D9 DRAM CKE"), + PINCTRL_PIN(69, "D10 DRAM DQ14"), + PINCTRL_PIN(70, "D11 DRAM DQ5"), + PINCTRL_PIN(71, "D12 DRAM DQ25"), + PINCTRL_PIN(72, "D13 DRAM DQ17"), + PINCTRL_PIN(73, "D14 DRAM DQ23"), + PINCTRL_PIN(74, "D15 DRAM RAS N"), + PINCTRL_PIN(75, "D16 DRAM A1"), + PINCTRL_PIN(76, "D17 GND"), + PINCTRL_PIN(77, "D18 EXT RESET N"), + PINCTRL_PIN(78, "D19 PCI REQ1 N"), + PINCTRL_PIN(79, "D20 PCI REQ3 N"), + /* Row E */ + PINCTRL_PIN(80, "E1 VCC2IO CTRL"), + PINCTRL_PIN(81, "E2 VREF CTRL"), + PINCTRL_PIN(82, "E3 CIR RST N"), + PINCTRL_PIN(83, "E4 PWR BTN"), + PINCTRL_PIN(84, "E5 GND"), + PINCTRL_PIN(85, "E6 CIR TXD"), + PINCTRL_PIN(86, "E7 VCCK CTRL"), + PINCTRL_PIN(87, "E8 DRAM A9"), + PINCTRL_PIN(88, "E9 DRAM DQ12"), + PINCTRL_PIN(89, "E10 DRAM DQ15"), + PINCTRL_PIN(90, "E11 DRAM DQM3"), + PINCTRL_PIN(91, "E12 DRAM DQ29"), + PINCTRL_PIN(92, "E13 DRAM DQ19"), + PINCTRL_PIN(93, "E14 DRAM A13"), + PINCTRL_PIN(94, "E15 DRAM A0"), + PINCTRL_PIN(95, "E16 GND"), + PINCTRL_PIN(96, "E17 PCI INTD N"), + PINCTRL_PIN(97, "E18 PCI GNT3 N"), + PINCTRL_PIN(98, "E19 PCI AD29"), + PINCTRL_PIN(99, "E20 PCI AD28"), + /* Row F */ + PINCTRL_PIN(100, "F1 AVCCKHB"), + PINCTRL_PIN(101, "F2 AVCCK P"), + PINCTRL_PIN(102, "F3 EBG"), + PINCTRL_PIN(103, "F4 REXT"), + PINCTRL_PIN(104, "F5 AVCC3IOHB"), + PINCTRL_PIN(105, "F6 GND"), + PINCTRL_PIN(106, "F7 VCC2IOHA 2"), + PINCTRL_PIN(107, "F8 VCC2IOHA 2"), + PINCTRL_PIN(108, "F9 VCC2IOHA 2"), + PINCTRL_PIN(109, "F10 V1"), + PINCTRL_PIN(110, "F11 V1"), + PINCTRL_PIN(111, "F12 VCC2IOHA 2"), + PINCTRL_PIN(112, "F13 VCC2IOHA 2"), + PINCTRL_PIN(113, "F14 VCC2IOHA 2"), + PINCTRL_PIN(114, "F15 GND"), + PINCTRL_PIN(115, "F16 PCI CLK"), + PINCTRL_PIN(116, "F17 PCI GNT2 N"), + PINCTRL_PIN(117, "F18 PCI AD31"), + PINCTRL_PIN(118, "F19 PCI AD26"), + PINCTRL_PIN(119, "F20 PCI CBE3 N"), + /* Row G */ + PINCTRL_PIN(120, "G1 SATA0 RXDP"), + PINCTRL_PIN(121, "G2 SATA0 RXDN"), + PINCTRL_PIN(122, "G3 AGNDK 0"), + PINCTRL_PIN(123, "G4 AVCCK S"), + PINCTRL_PIN(124, "G5 AVCC3 S"), + PINCTRL_PIN(125, "G6 VCC2IOHA 2"), + PINCTRL_PIN(126, "G7 GND"), + PINCTRL_PIN(127, "G8 VCC2IOHA 2"), + PINCTRL_PIN(128, "G9 V1"), + PINCTRL_PIN(129, "G10 V1"), + PINCTRL_PIN(130, "G11 V1"), + PINCTRL_PIN(131, "G12 V1"), + PINCTRL_PIN(132, "G13 VCC2IOHA 2"), + PINCTRL_PIN(133, "G14 GND"), + PINCTRL_PIN(134, "G15 VCC3IOHA"), + PINCTRL_PIN(135, "G16 PCI REQ0 N"), + PINCTRL_PIN(136, "G17 PCI AD30"), + PINCTRL_PIN(137, "G18 PCI AD24"), + PINCTRL_PIN(138, "G19 PCI AD23"), + PINCTRL_PIN(139, "G20 PCI AD21"), + /* Row H */ + PINCTRL_PIN(140, "H1 SATA0 TXDP"), + PINCTRL_PIN(141, "H2 SATA0 TXDN"), + PINCTRL_PIN(142, "H3 AGNDK 1"), + PINCTRL_PIN(143, "H4 AVCCK 0"), + PINCTRL_PIN(144, "H5 TEST CLKOUT"), + PINCTRL_PIN(145, "H6 AGND"), + PINCTRL_PIN(146, "H7 VCC2IOHA 2"), + PINCTRL_PIN(147, "H8 GND"), + PINCTRL_PIN(148, "H9 GND"), + PINCTRL_PIN(149, "H10 GDN"), + PINCTRL_PIN(150, "H11 GND"), + PINCTRL_PIN(151, "H12 GND"), + PINCTRL_PIN(152, "H13 GND"), + PINCTRL_PIN(153, "H14 VCC3IOHA"), + PINCTRL_PIN(154, "H15 VCC3IOHA"), + PINCTRL_PIN(155, "H16 PCI AD27"), + PINCTRL_PIN(156, "H17 PCI AD25"), + PINCTRL_PIN(157, "H18 PCI AD22"), + PINCTRL_PIN(158, "H19 PCI AD18"), + PINCTRL_PIN(159, "H20 PCI AD17"), + /* Row J (for some reason I is skipped) */ + PINCTRL_PIN(160, "J1 SATA1 TXDP"), + PINCTRL_PIN(161, "J2 SATA1 TXDN"), + PINCTRL_PIN(162, "J3 AGNDK 2"), + PINCTRL_PIN(163, "J4 AVCCK 1"), + PINCTRL_PIN(164, "J5 AGND"), + PINCTRL_PIN(165, "J6 AGND"), + PINCTRL_PIN(166, "J7 V1"), + PINCTRL_PIN(167, "J8 GND"), + PINCTRL_PIN(168, "J9 GND"), + PINCTRL_PIN(169, "J10 GND"), + PINCTRL_PIN(170, "J11 GND"), + PINCTRL_PIN(171, "J12 GND"), + PINCTRL_PIN(172, "J13 GND"), + PINCTRL_PIN(173, "J14 V1"), + PINCTRL_PIN(174, "J15 VCC3IOHA"), + PINCTRL_PIN(175, "J16 PCI AD19"), + PINCTRL_PIN(176, "J17 PCI AD20"), + PINCTRL_PIN(177, "J18 PCI AD16"), + PINCTRL_PIN(178, "J19 PCI CBE2 N"), + PINCTRL_PIN(179, "J20 PCI FRAME N"), + /* Row K */ + PINCTRL_PIN(180, "K1 SATA1 RXDP"), + PINCTRL_PIN(181, "K2 SATA1 RXDN"), + PINCTRL_PIN(182, "K3 AGNDK 3"), + PINCTRL_PIN(183, "K4 AVCCK 2"), + PINCTRL_PIN(184, "K5 AGND"), + PINCTRL_PIN(185, "K6 V1"), + PINCTRL_PIN(186, "K7 V1"), + PINCTRL_PIN(187, "K8 GND"), + PINCTRL_PIN(188, "K9 GND"), + PINCTRL_PIN(189, "K10 GND"), + PINCTRL_PIN(190, "K11 GND"), + PINCTRL_PIN(191, "K12 GND"), + PINCTRL_PIN(192, "K13 GND"), + PINCTRL_PIN(193, "K14 V1"), + PINCTRL_PIN(194, "K15 V1"), + PINCTRL_PIN(195, "K16 PCI TRDY N"), + PINCTRL_PIN(196, "K17 PCI IRDY N"), + PINCTRL_PIN(197, "K18 PCI DEVSEL N"), + PINCTRL_PIN(198, "K19 PCI STOP N"), + PINCTRL_PIN(199, "K20 PCI PAR"), + /* Row L */ + PINCTRL_PIN(200, "L1 IDE CS0 N"), + PINCTRL_PIN(201, "L2 IDE DA0"), + PINCTRL_PIN(202, "L3 AVCCK 3"), + PINCTRL_PIN(203, "L4 AGND"), + PINCTRL_PIN(204, "L5 IDE DIOR N"), + PINCTRL_PIN(205, "L6 V1"), + PINCTRL_PIN(206, "L7 V1"), + PINCTRL_PIN(207, "L8 GND"), + PINCTRL_PIN(208, "L9 GND"), + PINCTRL_PIN(209, "L10 GND"), + PINCTRL_PIN(210, "L11 GND"), + PINCTRL_PIN(211, "L12 GND"), + PINCTRL_PIN(212, "L13 GND"), + PINCTRL_PIN(213, "L14 V1"), + PINCTRL_PIN(214, "L15 V1"), + PINCTRL_PIN(215, "L16 PCI AD12"), + PINCTRL_PIN(216, "L17 PCI AD13"), + PINCTRL_PIN(217, "L18 PCI AD14"), + PINCTRL_PIN(218, "L19 PCI AD15"), + PINCTRL_PIN(219, "L20 PCI CBE1 N"), + /* Row M */ + PINCTRL_PIN(220, "M1 IDE DA1"), + PINCTRL_PIN(221, "M2 IDE CS1 N"), + PINCTRL_PIN(222, "M3 IDE DA2"), + PINCTRL_PIN(223, "M4 IDE DMACK N"), + PINCTRL_PIN(224, "M5 IDE DD1"), + PINCTRL_PIN(225, "M6 VCC3IOHA"), + PINCTRL_PIN(226, "M7 V1"), + PINCTRL_PIN(227, "M8 GND"), + PINCTRL_PIN(228, "M9 GND"), + PINCTRL_PIN(229, "M10 GND"), + PINCTRL_PIN(230, "M11 GND"), + PINCTRL_PIN(231, "M12 GND"), + PINCTRL_PIN(232, "M13 GND"), + PINCTRL_PIN(233, "M14 V1"), + PINCTRL_PIN(234, "M15 VCC3IOHA"), + PINCTRL_PIN(235, "M16 PCI AD7"), + PINCTRL_PIN(236, "M17 PCI AD6"), + PINCTRL_PIN(237, "M18 PCI AD9"), + PINCTRL_PIN(238, "M19 PCI AD10"), + PINCTRL_PIN(239, "M20 PCI AD11"), + /* Row N */ + PINCTRL_PIN(240, "N1 IDE IORDY"), + PINCTRL_PIN(241, "N2 IDE INTRQ"), + PINCTRL_PIN(242, "N3 IDE DIOW N"), + PINCTRL_PIN(243, "N4 IDE DD15"), + PINCTRL_PIN(244, "N5 IDE DMARQ"), + PINCTRL_PIN(245, "N6 VCC3IOHA"), + PINCTRL_PIN(246, "N7 VCC3IOHA"), + PINCTRL_PIN(247, "N8 GND"), + PINCTRL_PIN(248, "N9 GND"), + PINCTRL_PIN(249, "N10 GND"), + PINCTRL_PIN(250, "N11 GND"), + PINCTRL_PIN(251, "N12 GND"), + PINCTRL_PIN(252, "N13 GND"), + PINCTRL_PIN(253, "N14 VCC3IOHA"), + PINCTRL_PIN(254, "N15 VCC3IOHA"), + PINCTRL_PIN(255, "N16 PCI CLKRUN N"), + PINCTRL_PIN(256, "N17 PCI AD0"), + PINCTRL_PIN(257, "N18 PCI AD4"), + PINCTRL_PIN(258, "N19 PCI CBE0 N"), + PINCTRL_PIN(259, "N20 PCI AD8"), + /* Row P (for some reason O is skipped) */ + PINCTRL_PIN(260, "P1 IDE DD0"), + PINCTRL_PIN(261, "P2 IDE DD14"), + PINCTRL_PIN(262, "P3 IDE DD2"), + PINCTRL_PIN(263, "P4 IDE DD4"), + PINCTRL_PIN(264, "P5 IDE DD3"), + PINCTRL_PIN(265, "P6 VCC3IOHA"), + PINCTRL_PIN(266, "P7 GND"), + PINCTRL_PIN(267, "P8 VCC2IOHA 1"), + PINCTRL_PIN(268, "P9 V1"), + PINCTRL_PIN(269, "P10 V1"), + PINCTRL_PIN(270, "P11 V1"), + PINCTRL_PIN(271, "P12 V1"), + PINCTRL_PIN(272, "P13 VCC3IOHA"), + PINCTRL_PIN(273, "P14 GND"), + PINCTRL_PIN(274, "P15 VCC3IOHA"), + PINCTRL_PIN(275, "P16 GPIO0 30"), + PINCTRL_PIN(276, "P17 GPIO0 28"), + PINCTRL_PIN(277, "P18 PCI AD1"), + PINCTRL_PIN(278, "P19 PCI AD3"), + PINCTRL_PIN(279, "P20 PCI AD5"), + /* Row R (for some reason Q us skipped) */ + PINCTRL_PIN(280, "R1 IDE DD13"), + PINCTRL_PIN(281, "R2 IDE DD12"), + PINCTRL_PIN(282, "R3 IDE DD10"), + PINCTRL_PIN(283, "R4 IDE DD6"), + PINCTRL_PIN(284, "R5 ICE0 IDI"), + PINCTRL_PIN(285, "R6 GND"), + PINCTRL_PIN(286, "R7 VCC2IOHA 1"), + PINCTRL_PIN(287, "R8 VCC2IOHA 1"), + PINCTRL_PIN(288, "R9 VCC2IOHA 1"), + PINCTRL_PIN(289, "R10 V1"), + PINCTRL_PIN(290, "R11 V1"), + PINCTRL_PIN(291, "R12 VCC3IOHA"), + PINCTRL_PIN(292, "R13 VCC3IOHA"), + PINCTRL_PIN(293, "R14 VCC3IOHA"), + PINCTRL_PIN(294, "R15 GND"), + PINCTRL_PIN(295, "R16 GPIO0 23"), + PINCTRL_PIN(296, "R17 GPIO0 21"), + PINCTRL_PIN(297, "R18 GPIO0 26"), + PINCTRL_PIN(298, "R19 GPIO0 31"), + PINCTRL_PIN(299, "R20 PCI AD2"), + /* Row T (for some reason S is skipped) */ + PINCTRL_PIN(300, "T1 IDE DD11"), + PINCTRL_PIN(301, "T2 IDE DD5"), + PINCTRL_PIN(302, "T3 IDE DD8"), + PINCTRL_PIN(303, "T4 ICE0 IDO"), + PINCTRL_PIN(304, "T5 GND"), + PINCTRL_PIN(305, "T6 USB GNDA U20"), + PINCTRL_PIN(306, "T7 GMAC0 TXD0"), + PINCTRL_PIN(307, "T8 GMAC0 TXEN"), + PINCTRL_PIN(308, "T9 GMAC1 TXD3"), + PINCTRL_PIN(309, "T10 GMAC1 RXDV"), + PINCTRL_PIN(310, "T11 GMAC1 RXD2"), + PINCTRL_PIN(311, "T12 GPIO1 29"), + PINCTRL_PIN(312, "T13 GPIO0 3"), + PINCTRL_PIN(313, "T14 GPIO0 9"), + PINCTRL_PIN(314, "T15 GPIO0 16"), + PINCTRL_PIN(315, "T16 GND"), + PINCTRL_PIN(316, "T17 GPIO0 14"), + PINCTRL_PIN(317, "T18 GPIO0 19"), + PINCTRL_PIN(318, "T19 GPIO0 27"), + PINCTRL_PIN(319, "T20 GPIO0 29"), + /* Row U */ + PINCTRL_PIN(320, "U1 IDE DD9"), + PINCTRL_PIN(321, "U2 IDE DD7"), + PINCTRL_PIN(322, "U3 ICE0 ICK"), + PINCTRL_PIN(323, "U4 GND"), + PINCTRL_PIN(324, "U5 USB XSCO"), + PINCTRL_PIN(325, "U6 GMAC0 TXD1"), + PINCTRL_PIN(326, "U7 GMAC0 TXD3"), + PINCTRL_PIN(327, "U8 GMAC0 TXC"), + PINCTRL_PIN(328, "U9 GMAC0 RXD3"), + PINCTRL_PIN(329, "U10 GMAC1 TXD0"), + PINCTRL_PIN(330, "U11 GMAC1 CRS"), + PINCTRL_PIN(331, "U12 EXT CLK"), + PINCTRL_PIN(332, "U13 DEV DEF"), + PINCTRL_PIN(333, "U14 GPIO0 0"), + PINCTRL_PIN(334, "U15 GPIO0 4"), + PINCTRL_PIN(335, "U16 GPIO0 10"), + PINCTRL_PIN(336, "U17 GND"), + PINCTRL_PIN(337, "U18 GPIO0 17"), + PINCTRL_PIN(338, "U19 GPIO0 22"), + PINCTRL_PIN(339, "U20 GPIO0 25"), + /* Row V */ + PINCTRL_PIN(340, "V1 ICE0 DBGACK"), + PINCTRL_PIN(341, "V2 ICE0 DBGRQ"), + PINCTRL_PIN(342, "V3 GND"), + PINCTRL_PIN(343, "V4 ICE0 IRST N"), + PINCTRL_PIN(344, "V5 USB XSCI"), + PINCTRL_PIN(345, "V6 GMAC0 COL"), + PINCTRL_PIN(346, "V7 GMAC0 TXD2"), + PINCTRL_PIN(347, "V8 GMAC0 RXDV"), + PINCTRL_PIN(348, "V9 GMAC0 RXD1"), + PINCTRL_PIN(349, "V10 GMAC1 COL"), + PINCTRL_PIN(350, "V11 GMAC1 TXC"), + PINCTRL_PIN(351, "V12 GMAC1 RXD1"), + PINCTRL_PIN(352, "V13 MODE SEL1"), + PINCTRL_PIN(353, "V14 GPIO1 28"), + PINCTRL_PIN(354, "V15 GPIO0 1"), + PINCTRL_PIN(355, "V16 GPIO0 8"), + PINCTRL_PIN(356, "V17 GPIO0 11"), + PINCTRL_PIN(357, "V18 GND"), + PINCTRL_PIN(358, "V19 GPIO0 18"), + PINCTRL_PIN(359, "V20 GPIO0 24"), + /* Row W */ + PINCTRL_PIN(360, "W1 IDE RESET N"), + PINCTRL_PIN(361, "W2 GND"), + PINCTRL_PIN(362, "W3 USB0 VCCHSRT"), + PINCTRL_PIN(363, "W4 USB0 DP"), + PINCTRL_PIN(364, "W5 USB VCCA U20"), + PINCTRL_PIN(365, "W6 USB1 DP"), + PINCTRL_PIN(366, "W7 USB1 GNDHSRT"), + PINCTRL_PIN(367, "W8 GMAC0 RXD0"), + PINCTRL_PIN(368, "W9 GMAC0 CRS"), + PINCTRL_PIN(369, "W10 GMAC1 TXD2"), + PINCTRL_PIN(370, "W11 GMAC1 TXEN"), + PINCTRL_PIN(371, "W12 GMAC1 RXD3"), + PINCTRL_PIN(372, "W13 MODE SEL0"), + PINCTRL_PIN(373, "W14 MODE SEL3"), + PINCTRL_PIN(374, "W15 GPIO1 31"), + PINCTRL_PIN(375, "W16 GPIO0 5"), + PINCTRL_PIN(376, "W17 GPIO0 7"), + PINCTRL_PIN(377, "W18 GPIO0 12"), + PINCTRL_PIN(378, "W19 GND"), + PINCTRL_PIN(379, "W20 GPIO0 20"), + /* Row Y */ + PINCTRL_PIN(380, "Y1 ICE0 IMS"), + PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"), + PINCTRL_PIN(382, "Y3 USB0 DM"), + PINCTRL_PIN(383, "Y4 USB RREF"), + PINCTRL_PIN(384, "Y5 USB1 DM"), + PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"), + PINCTRL_PIN(386, "Y7 GMAC0 RXC"), + PINCTRL_PIN(387, "Y8 GMAC0 RXD2"), + PINCTRL_PIN(388, "Y9 REF CLK"), + PINCTRL_PIN(389, "Y10 GMAC1 TXD1"), + PINCTRL_PIN(390, "Y11 GMAC1 RXC"), + PINCTRL_PIN(391, "Y12 GMAC1 RXD0"), + PINCTRL_PIN(392, "Y13 M30 CLK"), + PINCTRL_PIN(393, "Y14 MODE SEL2"), + PINCTRL_PIN(394, "Y15 GPIO1 30"), + PINCTRL_PIN(395, "Y16 GPIO0 2"), + PINCTRL_PIN(396, "Y17 GPIO0 6"), + PINCTRL_PIN(397, "Y18 SYS RESET N"), + PINCTRL_PIN(398, "Y19 GPIO0 13"), + PINCTRL_PIN(399, "Y20 GPIO0 15"), +}; + +/* Digital ground */ +static const unsigned int gnd_3516_pins[] = { + 21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150, + 151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192, + 207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248, + 249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357, + 361, 378 +}; + +static const unsigned int dram_3516_pins[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26, + 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, + 87, 88, 89, 90, 91, 92, 93, 94 +}; + +static const unsigned int rtc_3516_pins[] = { 0, 43, 22 }; + +static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 }; + +static const unsigned int cir_3516_pins[] = { 85, 64, 82 }; + +static const unsigned int system_3516_pins[] = { + 332, 392, 372, 373, 393, 352, 331, 388, 397, 77 +}; + +static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 }; + +static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 }; + +static const unsigned int ide_3516_pins[] = { + 200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260, + 261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360 +}; + +static const unsigned int sata_3516_pins[] = { + 100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143, + 144, 160, 161, 162, 163, 180, 181, 182, 183, 202 +}; + +static const unsigned int usb_3516_pins[] = { + 305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385 +}; + +/* GMII, ethernet pins */ +static const unsigned int gmii_3516_pins[] = { + 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, + 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 +}; + +static const unsigned int pci_3516_pins[] = { + 17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118, + 119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177, + 178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236, + 237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299 +}; + +/* + * Apparently the LPC interface is using the PCICLK for the clocking so + * PCI needs to be active at the same time. + */ +static const unsigned int lpc_3516_pins[] = { + 355, /* LPC_LAD[0] */ + 356, /* LPC_SERIRQ */ + 377, /* LPC_LAD[2] */ + 398, /* LPC_LFRAME# */ + 316, /* LPC_LAD[3] */ + 399, /* LPC_LAD[1] */ +}; + +/* Character LCD */ +static const unsigned int lcd_3516_pins[] = { + 391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339 +}; + +static const unsigned int ssp_3516_pins[] = { + 355, /* SSP_97RST# SSP AC97 Reset, active low */ + 356, /* SSP_FSC */ + 377, /* SSP_ECLK */ + 398, /* SSP_TXD */ + 316, /* SSP_RXD */ + 399, /* SSP_SCLK */ +}; + +static const unsigned int uart_rxtx_3516_pins[] = { + 313, /* UART_SIN serial input, RX */ + 335, /* UART_SOUT serial output, TX */ +}; + +static const unsigned int uart_modem_3516_pins[] = { + 355, /* UART_NDCD DCD carrier detect */ + 356, /* UART_NDTR DTR data terminal ready */ + 377, /* UART_NDSR DSR data set ready */ + 398, /* UART_NRTS RTS request to send */ + 316, /* UART_NCTS CTS clear to send */ + 399, /* UART_NRI RI ring indicator */ +}; + +static const unsigned int tvc_3516_pins[] = { + 353, /* TVC_DATA[0] */ + 311, /* TVC_DATA[1] */ + 394, /* TVC_DATA[2] */ + 374, /* TVC_DATA[3] */ + 333, /* TVC_CLK */ + 354, /* TVC_DATA[4] */ + 395, /* TVC_DATA[5] */ + 312, /* TVC_DATA[6] */ + 334, /* TVC_DATA[7] */ +}; + +/* NAND flash pins */ +static const unsigned int nflash_3516_pins[] = { + 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, + 302, 321, 337, 358, 295, 359, 339, 275, 298 +}; + +/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ +static const unsigned int pflash_3516_pins[] = { + 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, + 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, + 276, 319, 275, 298 +}; + +/* + * The parallel flash can be set up in a 26-bit address bus mode exposing + * A[0-15] (A[15] takes the place of ALE), but it has the + * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be + * used at the same time. + */ +static const unsigned int pflash_3516_pins_extended[] = { + 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, + 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, + 276, 319, 275, 298, + /* The extra pins */ + 349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330, + 333 +}; + +/* Serial flash pins CE0, CE1, DI, DO, CK */ +static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 }; + +/* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ +static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 }; + +/* The GPIO0B (5-7) pins overlap with ICE */ +static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 }; + +/* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */ +static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 }; + +/* The GPIO0D (9,10) pins overlap with UART RX/TX */ +static const unsigned int gpio0d_3516_pins[] = { 313, 335 }; + +/* The GPIO0E (16) pins overlap with LCD */ +static const unsigned int gpio0e_3516_pins[] = { 314 }; + +/* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */ +static const unsigned int gpio0f_3516_pins[] = { 337, 358 }; + +/* The GPIO0G (19,20,26-29) pins overlap with parallel flash */ +static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 }; + +/* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */ +static const unsigned int gpio0h_3516_pins[] = { 296, 338 }; + +/* The GPIO0I (23) pins overlap with all flash */ +static const unsigned int gpio0i_3516_pins[] = { 295 }; + +/* The GPIO0J (24,25) pins overlap with all flash and LCD */ +static const unsigned int gpio0j_3516_pins[] = { 359, 339 }; + +/* The GPIO0K (30,31) pins overlap with NAND flash */ +static const unsigned int gpio0k_3516_pins[] = { 275, 298 }; + +/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ +static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 }; + +/* The GPIO1B (5-10,27) pins overlap with just IDE */ +static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 }; + +/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ +static const unsigned int gpio1c_3516_pins[] = { + 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, + 302, 321 +}; + +/* The GPIO1D (28-31) pins overlap with TVC */ +static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; + +/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ +static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; + +/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ +static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; + +/* The GPIO2C (8-31) pins overlap with PCI */ +static const unsigned int gpio2c_3516_pins[] = { + 259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139, + 157, 138, 137, 156, 118, 155, 99, 98, 136, 117 +}; + +/* Groups for the 3516 SoC/package */ +static const struct gemini_pin_group gemini_3516_pin_groups[] = { + { + .name = "gndgrp", + .pins = gnd_3516_pins, + .num_pins = ARRAY_SIZE(gnd_3516_pins), + }, + { + .name = "dramgrp", + .pins = dram_3516_pins, + .num_pins = ARRAY_SIZE(dram_3516_pins), + .mask = DRAM_PADS_POWERDOWN, + }, + { + .name = "rtcgrp", + .pins = rtc_3516_pins, + .num_pins = ARRAY_SIZE(rtc_3516_pins), + }, + { + .name = "powergrp", + .pins = power_3516_pins, + .num_pins = ARRAY_SIZE(power_3516_pins), + }, + { + .name = "cirgrp", + .pins = cir_3516_pins, + .num_pins = ARRAY_SIZE(cir_3516_pins), + }, + { + .name = "systemgrp", + .pins = system_3516_pins, + .num_pins = ARRAY_SIZE(system_3516_pins), + }, + { + .name = "vcontrolgrp", + .pins = vcontrol_3516_pins, + .num_pins = ARRAY_SIZE(vcontrol_3516_pins), + }, + { + .name = "icegrp", + .pins = ice_3516_pins, + .num_pins = ARRAY_SIZE(ice_3516_pins), + /* Conflict with some GPIO groups */ + }, + { + .name = "idegrp", + .pins = ide_3516_pins, + .num_pins = ARRAY_SIZE(ide_3516_pins), + /* Conflict with all flash usage */ + .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | + PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, + }, + { + .name = "satagrp", + .pins = sata_3516_pins, + .num_pins = ARRAY_SIZE(sata_3516_pins), + }, + { + .name = "usbgrp", + .pins = usb_3516_pins, + .num_pins = ARRAY_SIZE(usb_3516_pins), + }, + { + .name = "gmiigrp", + .pins = gmii_3516_pins, + .num_pins = ARRAY_SIZE(gmii_3516_pins), + }, + { + .name = "pcigrp", + .pins = pci_3516_pins, + .num_pins = ARRAY_SIZE(pci_3516_pins), + /* Conflict only with GPIO2 */ + .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, + }, + { + .name = "lpcgrp", + .pins = lpc_3516_pins, + .num_pins = ARRAY_SIZE(lpc_3516_pins), + /* Conflict with SSP */ + .mask = SSP_PADS_ENABLE, + .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, + }, + { + .name = "lcdgrp", + .pins = lcd_3516_pins, + .num_pins = ARRAY_SIZE(lcd_3516_pins), + .mask = TVC_PADS_ENABLE, + .value = LCD_PADS_ENABLE, + }, + { + .name = "sspgrp", + .pins = ssp_3516_pins, + .num_pins = ARRAY_SIZE(ssp_3516_pins), + /* Conflict with LPC */ + .mask = LPC_PADS_ENABLE, + .value = SSP_PADS_ENABLE, + }, + { + .name = "uartrxtxgrp", + .pins = uart_rxtx_3516_pins, + .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins), + /* No conflicts except GPIO */ + }, + { + .name = "uartmodemgrp", + .pins = uart_modem_3516_pins, + .num_pins = ARRAY_SIZE(uart_modem_3516_pins), + /* + * Conflict with LPC and SSP, + * so when those are both disabled, modem UART can thrive. + */ + .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, + }, + { + .name = "tvcgrp", + .pins = tvc_3516_pins, + .num_pins = ARRAY_SIZE(tvc_3516_pins), + /* Conflict with character LCD */ + .mask = LCD_PADS_ENABLE, + .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, + }, + /* + * The construction is done such that it is possible to use a serial + * flash together with a NAND or parallel (NOR) flash, but it is not + * possible to use NAND and parallel flash together. To use serial + * flash with one of the two others, the muxbits need to be flipped + * around before any access. + */ + { + .name = "nflashgrp", + .pins = nflash_3516_pins, + .num_pins = ARRAY_SIZE(nflash_3516_pins), + /* Conflict with IDE, parallel and serial flash */ + .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, + .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, + }, + { + .name = "pflashgrp", + .pins = pflash_3516_pins, + .num_pins = ARRAY_SIZE(pflash_3516_pins), + /* Conflict with IDE, NAND and serial flash */ + .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, + .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, + }, + { + .name = "sflashgrp", + .pins = sflash_3516_pins, + .num_pins = ARRAY_SIZE(sflash_3516_pins), + /* Conflict with IDE, NAND and parallel flash */ + .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, + .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, + }, + { + .name = "gpio0agrp", + .pins = gpio0a_3516_pins, + .num_pins = ARRAY_SIZE(gpio0a_3516_pins), + /* Conflict with TVC and ICE */ + .mask = TVC_PADS_ENABLE, + }, + { + .name = "gpio0bgrp", + .pins = gpio0b_3516_pins, + .num_pins = ARRAY_SIZE(gpio0b_3516_pins), + /* Conflict with ICE */ + }, + { + .name = "gpio0cgrp", + .pins = gpio0c_3516_pins, + .num_pins = ARRAY_SIZE(gpio0c_3516_pins), + /* Conflict with LPC, UART and SSP */ + .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, + }, + { + .name = "gpio0dgrp", + .pins = gpio0d_3516_pins, + .num_pins = ARRAY_SIZE(gpio0d_3516_pins), + /* Conflict with UART */ + }, + { + .name = "gpio0egrp", + .pins = gpio0e_3516_pins, + .num_pins = ARRAY_SIZE(gpio0e_3516_pins), + /* Conflict with LCD */ + .mask = LCD_PADS_ENABLE, + }, + { + .name = "gpio0fgrp", + .pins = gpio0f_3516_pins, + .num_pins = ARRAY_SIZE(gpio0f_3516_pins), + /* Conflict with NAND flash */ + .value = NAND_PADS_DISABLE, + }, + { + .name = "gpio0ggrp", + .pins = gpio0g_3516_pins, + .num_pins = ARRAY_SIZE(gpio0g_3516_pins), + /* Conflict with parallel flash */ + .value = PFLASH_PADS_DISABLE, + }, + { + .name = "gpio0hgrp", + .pins = gpio0h_3516_pins, + .num_pins = ARRAY_SIZE(gpio0h_3516_pins), + /* Conflict with serial flash */ + .value = SFLASH_PADS_DISABLE, + }, + { + .name = "gpio0igrp", + .pins = gpio0i_3516_pins, + .num_pins = ARRAY_SIZE(gpio0i_3516_pins), + /* Conflict with all flash */ + .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | + SFLASH_PADS_DISABLE, + }, + { + .name = "gpio0jgrp", + .pins = gpio0j_3516_pins, + .num_pins = ARRAY_SIZE(gpio0j_3516_pins), + /* Conflict with all flash and LCD */ + .mask = LCD_PADS_ENABLE, + .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | + SFLASH_PADS_DISABLE, + }, + { + .name = "gpio0kgrp", + .pins = gpio0k_3516_pins, + .num_pins = ARRAY_SIZE(gpio0k_3516_pins), + /* Conflict with parallel and NAND flash */ + .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, + }, + { + .name = "gpio1agrp", + .pins = gpio1a_3516_pins, + .num_pins = ARRAY_SIZE(gpio1a_3516_pins), + /* Conflict with IDE and parallel flash */ + .mask = IDE_PADS_ENABLE, + .value = PFLASH_PADS_DISABLE, + }, + { + .name = "gpio1bgrp", + .pins = gpio1b_3516_pins, + .num_pins = ARRAY_SIZE(gpio1b_3516_pins), + /* Conflict with IDE only */ + .mask = IDE_PADS_ENABLE, + }, + { + .name = "gpio1cgrp", + .pins = gpio1c_3516_pins, + .num_pins = ARRAY_SIZE(gpio1c_3516_pins), + /* Conflict with IDE, parallel and NAND flash */ + .mask = IDE_PADS_ENABLE, + .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, + }, + { + .name = "gpio1dgrp", + .pins = gpio1d_3516_pins, + .num_pins = ARRAY_SIZE(gpio1d_3516_pins), + /* Conflict with TVC */ + .mask = TVC_PADS_ENABLE, + }, + { + .name = "gpio2agrp", + .pins = gpio2a_3516_pins, + .num_pins = ARRAY_SIZE(gpio2a_3516_pins), + /* Conflict with GMII and extended parallel flash */ + }, + { + .name = "gpio2bgrp", + .pins = gpio2b_3516_pins, + .num_pins = ARRAY_SIZE(gpio2b_3516_pins), + /* Conflict with GMII, extended parallel flash and LCD */ + .mask = LCD_PADS_ENABLE, + }, + { + .name = "gpio2cgrp", + .pins = gpio2c_3516_pins, + .num_pins = ARRAY_SIZE(gpio2c_3516_pins), + /* Conflict with PCI */ + .mask = PCI_PADS_ENABLE, + }, +}; + +static int gemini_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + if (pmx->is_3512) + return ARRAY_SIZE(gemini_3512_pin_groups); + if (pmx->is_3516) + return ARRAY_SIZE(gemini_3516_pin_groups); + return 0; +} + +static const char *gemini_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + if (pmx->is_3512) + return gemini_3512_pin_groups[selector].name; + if (pmx->is_3516) + return gemini_3516_pin_groups[selector].name; + return NULL; +} + +static int gemini_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + + /* The special case with the 3516 flash pin */ + if (pmx->flash_pin && + pmx->is_3512 && + !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) { + *pins = pflash_3512_pins_extended; + *num_pins = ARRAY_SIZE(pflash_3512_pins_extended); + return 0; + } + if (pmx->flash_pin && + pmx->is_3516 && + !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) { + *pins = pflash_3516_pins_extended; + *num_pins = ARRAY_SIZE(pflash_3516_pins_extended); + return 0; + } + if (pmx->is_3512) { + *pins = gemini_3512_pin_groups[selector].pins; + *num_pins = gemini_3512_pin_groups[selector].num_pins; + } + if (pmx->is_3516) { + *pins = gemini_3516_pin_groups[selector].pins; + *num_pins = gemini_3516_pin_groups[selector].num_pins; + } + return 0; +} + +static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *reserved_maps, + unsigned int *num_maps) +{ + int ret; + const char *function = NULL; + const char *group; + struct property *prop; + + ret = of_property_read_string(np, "function", &function); + if (ret < 0) + return ret; + + ret = of_property_count_strings(np, "groups"); + if (ret < 0) + return ret; + + ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, + num_maps, ret); + if (ret < 0) + return ret; + + of_property_for_each_string(np, "groups", prop, group) { + ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, + num_maps, group, function); + if (ret < 0) + return ret; + pr_debug("ADDED FUNCTION %s <-> GROUP %s\n", + function, group); + } + + return 0; +} + +static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + unsigned int reserved_maps = 0; + struct device_node *np; + int ret; + + *map = NULL; + *num_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +}; + +static const struct pinctrl_ops gemini_pctrl_ops = { + .get_groups_count = gemini_get_groups_count, + .get_group_name = gemini_get_group_name, + .get_group_pins = gemini_get_group_pins, + .pin_dbg_show = gemini_pin_dbg_show, + .dt_node_to_map = gemini_pinctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +/** + * struct gemini_pmx_func - describes Gemini pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + */ +struct gemini_pmx_func { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const dramgrps[] = { "dramgrp" }; +static const char * const rtcgrps[] = { "rtcgrp" }; +static const char * const powergrps[] = { "powergrp" }; +static const char * const cirgrps[] = { "cirgrp" }; +static const char * const systemgrps[] = { "systemgrp" }; +static const char * const vcontrolgrps[] = { "vcontrolgrp" }; +static const char * const icegrps[] = { "icegrp" }; +static const char * const idegrps[] = { "idegrp" }; +static const char * const satagrps[] = { "satagrp" }; +static const char * const usbgrps[] = { "usbgrp" }; +static const char * const gmiigrps[] = { "gmiigrp" }; +static const char * const pcigrps[] = { "pcigrp" }; +static const char * const lpcgrps[] = { "lpcgrp" }; +static const char * const lcdgrps[] = { "lcdgrp" }; +static const char * const sspgrps[] = { "sspgrp" }; +static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" }; +static const char * const tvcgrps[] = { "tvcgrp" }; +static const char * const nflashgrps[] = { "nflashgrp" }; +static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" }; +static const char * const sflashgrps[] = { "sflashgrp" }; +static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", + "gpio0dgrp", "gpio0egrp", "gpio0fgrp", + "gpio0ggrp", "gpio0hgrp", "gpio0igrp", + "gpio0jgrp", "gpio0kgrp" }; +static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", + "gpio1dgrp" }; +static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; + +static const struct gemini_pmx_func gemini_pmx_functions[] = { + { + .name = "dram", + .groups = dramgrps, + .num_groups = ARRAY_SIZE(idegrps), + }, + { + .name = "rtc", + .groups = rtcgrps, + .num_groups = ARRAY_SIZE(rtcgrps), + }, + { + .name = "power", + .groups = powergrps, + .num_groups = ARRAY_SIZE(powergrps), + }, + { + /* This function is strictly unavailable on 3512 */ + .name = "cir", + .groups = cirgrps, + .num_groups = ARRAY_SIZE(cirgrps), + }, + { + .name = "system", + .groups = systemgrps, + .num_groups = ARRAY_SIZE(systemgrps), + }, + { + .name = "vcontrol", + .groups = vcontrolgrps, + .num_groups = ARRAY_SIZE(vcontrolgrps), + }, + { + .name = "ice", + .groups = icegrps, + .num_groups = ARRAY_SIZE(icegrps), + }, + { + .name = "ide", + .groups = idegrps, + .num_groups = ARRAY_SIZE(idegrps), + }, + { + .name = "sata", + .groups = satagrps, + .num_groups = ARRAY_SIZE(satagrps), + }, + { + .name = "pci", + .groups = pcigrps, + .num_groups = ARRAY_SIZE(pcigrps), + }, + { + .name = "lpc", + .groups = lpcgrps, + .num_groups = ARRAY_SIZE(lpcgrps), + }, + { + .name = "lcd", + .groups = lcdgrps, + .num_groups = ARRAY_SIZE(lcdgrps), + }, + { + .name = "ssp", + .groups = sspgrps, + .num_groups = ARRAY_SIZE(sspgrps), + }, + { + .name = "uart", + .groups = uartgrps, + .num_groups = ARRAY_SIZE(uartgrps), + }, + { + .name = "tvc", + .groups = tvcgrps, + .num_groups = ARRAY_SIZE(tvcgrps), + }, + { + .name = "nflash", + .groups = nflashgrps, + .num_groups = ARRAY_SIZE(nflashgrps), + }, + { + .name = "pflash", + .groups = pflashgrps, + .num_groups = ARRAY_SIZE(pflashgrps), + }, + { + .name = "sflash", + .groups = sflashgrps, + .num_groups = ARRAY_SIZE(sflashgrps), + }, + { + .name = "gpio0", + .groups = gpio0grps, + .num_groups = ARRAY_SIZE(gpio0grps), + }, + { + .name = "gpio1", + .groups = gpio1grps, + .num_groups = ARRAY_SIZE(gpio1grps), + }, + { + .name = "gpio2", + .groups = gpio2grps, + .num_groups = ARRAY_SIZE(gpio2grps), + }, +}; + + +static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct gemini_pmx *pmx; + const struct gemini_pmx_func *func; + const struct gemini_pin_group *grp; + u32 before, after, expected; + unsigned long tmp; + int i; + + pmx = pinctrl_dev_get_drvdata(pctldev); + + func = &gemini_pmx_functions[selector]; + if (pmx->is_3512) + grp = &gemini_3512_pin_groups[group]; + else if (pmx->is_3516) + grp = &gemini_3516_pin_groups[group]; + else { + dev_err(pmx->dev, "invalid SoC type\n"); + return -ENODEV; + } + + dev_info(pmx->dev, + "ACTIVATE function \"%s\" with group \"%s\"\n", + func->name, grp->name); + + regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); + regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, grp->mask, + grp->value); + regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); + + /* Which bits changed */ + before &= PADS_MASK; + after &= PADS_MASK; + expected = before &= ~grp->mask; + expected |= grp->value; + expected &= PADS_MASK; + + /* Print changed states */ + tmp = grp->mask; + for_each_set_bit(i, &tmp, PADS_MAXBIT) { + bool enabled = !(i > 3); + + /* Did not go low though it should */ + if (after & BIT(i)) { + dev_err(pmx->dev, + "pin group %s could not be %s: " + "probably a hardware limitation\n", + gemini_padgroups[i], + enabled ? "enabled" : "disabled"); + dev_err(pmx->dev, + "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", + before, after, expected); + } else { + dev_info(pmx->dev, + "padgroup %s %s\n", + gemini_padgroups[i], + enabled ? "enabled" : "disabled"); + } + } + + tmp = grp->value; + for_each_set_bit(i, &tmp, PADS_MAXBIT) { + bool enabled = (i > 3); + + /* Did not go high though it should */ + if (!(after & BIT(i))) { + dev_err(pmx->dev, + "pin group %s could not be %s: " + "probably a hardware limitation\n", + gemini_padgroups[i], + enabled ? "enabled" : "disabled"); + dev_err(pmx->dev, + "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", + before, after, expected); + } else { + dev_info(pmx->dev, + "padgroup %s %s\n", + gemini_padgroups[i], + enabled ? "enabled" : "disabled"); + } + } + + return 0; +} + +static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(gemini_pmx_functions); +} + +static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return gemini_pmx_functions[selector].name; +} + +static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = gemini_pmx_functions[selector].groups; + *num_groups = gemini_pmx_functions[selector].num_groups; + return 0; +} + +static const struct pinmux_ops gemini_pmx_ops = { + .get_functions_count = gemini_pmx_get_funcs_count, + .get_function_name = gemini_pmx_get_func_name, + .get_function_groups = gemini_pmx_get_groups, + .set_mux = gemini_pmx_set_mux, +}; + +static struct pinctrl_desc gemini_pmx_desc = { + .name = DRIVER_NAME, + .pctlops = &gemini_pctrl_ops, + .pmxops = &gemini_pmx_ops, + .owner = THIS_MODULE, +}; + +static int gemini_pmx_probe(struct platform_device *pdev) +{ + struct gemini_pmx *pmx; + struct regmap *map; + struct device *dev = &pdev->dev; + struct device *parent; + unsigned long tmp; + u32 val; + int ret; + int i; + + /* Create state holders etc for this driver */ + pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->dev = &pdev->dev; + parent = dev->parent; + if (!parent) { + dev_err(dev, "no parent to pin controller\n"); + return -ENODEV; + } + map = syscon_node_to_regmap(parent->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + pmx->map = map; + + /* Check that regmap works at first call, then no more */ + ret = regmap_read(map, GLOBAL_WORD_ID, &val); + if (ret) { + dev_err(dev, "cannot access regmap\n"); + return ret; + } + val >>= 8; + val &= 0xffff; + if (val == 0x3512) { + pmx->is_3512 = true; + gemini_pmx_desc.pins = gemini_3512_pins; + gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); + dev_info(dev, "detected 3512 chip variant\n"); + } else if (val == 0x3516) { + pmx->is_3516 = true; + gemini_pmx_desc.pins = gemini_3516_pins; + gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); + dev_info(dev, "detected 3516 chip variant\n"); + } else { + dev_err(dev, "unknown chip ID: %04x\n", val); + return -ENODEV; + } + + ret = regmap_read(map, GLOBAL_MISC_CTRL, &val); + dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val); + /* Mask off relevant pads */ + val &= PADS_MASK; + /* Invert the meaning of the DRAM+flash pads */ + val ^= 0x0f; + /* Print initial state */ + tmp = val; + for_each_set_bit(i, &tmp, PADS_MAXBIT) { + dev_info(dev, "pad group %s %s\n", gemini_padgroups[i], + (val & BIT(i)) ? "enabled" : "disabled"); + } + + /* Check if flash pin is set */ + regmap_read(map, GLOBAL_STATUS, &val); + pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); + dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); + + pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); + if (IS_ERR(pmx->pctl)) { + dev_err(dev, "could not register pinmux driver\n"); + return PTR_ERR(pmx->pctl); + } + + dev_info(dev, "initialized Gemini pin control driver\n"); + + return 0; +} + +static const struct of_device_id gemini_pinctrl_match[] = { + { .compatible = "cortina,gemini-pinctrl" }, + {}, +}; + +static struct platform_driver gemini_pmx_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = gemini_pinctrl_match, + }, + .probe = gemini_pmx_probe, +}; + +static int __init gemini_pmx_init(void) +{ + return platform_driver_register(&gemini_pmx_driver); +} +arch_initcall(gemini_pmx_init); diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index d8e8842967d6..d84761822243 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -460,7 +460,7 @@ static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, return val & BIT(idx); } -static struct pinctrl_ops ingenic_pctlops = { +static const struct pinctrl_ops ingenic_pctlops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, @@ -543,7 +543,7 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops ingenic_pmxops = { +static const struct pinmux_ops ingenic_pmxops = { .get_functions_count = pinmux_generic_get_function_count, .get_function_name = pinmux_generic_get_function_name, .get_function_groups = pinmux_generic_get_function_groups, @@ -696,7 +696,7 @@ static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, return 0; } -static struct pinconf_ops ingenic_confops = { +static const struct pinconf_ops ingenic_confops = { .is_generic = true, .pin_config_get = ingenic_pinconf_get, .pin_config_set = ingenic_pinconf_set, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index e831647c56a6..b5cb7858ffdc 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -62,6 +62,7 @@ enum rockchip_pinctrl_type { RV1108, RK2928, RK3066B, + RK3128, RK3188, RK3288, RK3368, @@ -76,7 +77,6 @@ enum rockchip_pinctrl_type { #define IOMUX_SOURCE_PMU BIT(2) #define IOMUX_UNROUTED BIT(3) #define IOMUX_WIDTH_3BIT BIT(4) -#define IOMUX_RECALCED BIT(5) /** * @type: iomux variant using IOMUX_* constants @@ -166,6 +166,7 @@ struct rockchip_pin_bank { struct pinctrl_gpio_range grange; raw_spinlock_t slock; u32 toggle_edge_mode; + u32 recalced_mask; u32 route_mask; }; @@ -291,6 +292,22 @@ struct rockchip_pin_bank { /** * struct rockchip_mux_recalced_data: represent a pin iomux data. + * @num: bank number. + * @pin: pin number. + * @bit: index at register. + * @reg: register offset. + * @mask: mask bit + */ +struct rockchip_mux_recalced_data { + u8 num; + u8 pin; + u32 reg; + u8 bit; + u8 mask; +}; + +/** + * struct rockchip_mux_recalced_data: represent a pin iomux data. * @bank_num: bank number. * @pin: index at register or used to calc index. * @func: the min pin. @@ -317,6 +334,8 @@ struct rockchip_pin_ctrl { int pmu_mux_offset; int grf_drv_offset; int pmu_drv_offset; + struct rockchip_mux_recalced_data *iomux_recalced; + u32 niomux_recalced; struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; @@ -326,8 +345,6 @@ struct rockchip_pin_ctrl { void (*drv_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); - void (*iomux_recalc)(u8 bank_num, int pin, int *reg, - u8 *bit, int *mask); int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -382,22 +399,6 @@ struct rockchip_pinctrl { unsigned int nfunctions; }; -/** - * struct rockchip_mux_recalced_data: represent a pin iomux data. - * @num: bank number. - * @pin: pin number. - * @bit: index at register. - * @reg: register offset. - * @mask: mask bit - */ -struct rockchip_mux_recalced_data { - u8 num; - u8 pin; - u8 reg; - u8 bit; - u8 mask; -}; - static struct regmap_config rockchip_regmap_config = { .reg_bits = 32, .val_bits = 32, @@ -557,7 +558,105 @@ static const struct pinctrl_ops rockchip_pctrl_ops = { * Hardware access */ -static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { +static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { + { + .num = 1, + .pin = 0, + .reg = 0x418, + .bit = 0, + .mask = 0x3 + }, { + .num = 1, + .pin = 1, + .reg = 0x418, + .bit = 2, + .mask = 0x3 + }, { + .num = 1, + .pin = 2, + .reg = 0x418, + .bit = 4, + .mask = 0x3 + }, { + .num = 1, + .pin = 3, + .reg = 0x418, + .bit = 6, + .mask = 0x3 + }, { + .num = 1, + .pin = 4, + .reg = 0x418, + .bit = 8, + .mask = 0x3 + }, { + .num = 1, + .pin = 5, + .reg = 0x418, + .bit = 10, + .mask = 0x3 + }, { + .num = 1, + .pin = 6, + .reg = 0x418, + .bit = 12, + .mask = 0x3 + }, { + .num = 1, + .pin = 7, + .reg = 0x418, + .bit = 14, + .mask = 0x3 + }, { + .num = 1, + .pin = 8, + .reg = 0x41c, + .bit = 0, + .mask = 0x3 + }, { + .num = 1, + .pin = 9, + .reg = 0x41c, + .bit = 2, + .mask = 0x3 + }, +}; + +static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { + { + .num = 2, + .pin = 20, + .reg = 0xe8, + .bit = 0, + .mask = 0x7 + }, { + .num = 2, + .pin = 21, + .reg = 0xe8, + .bit = 4, + .mask = 0x7 + }, { + .num = 2, + .pin = 22, + .reg = 0xe8, + .bit = 8, + .mask = 0x7 + }, { + .num = 2, + .pin = 23, + .reg = 0xe8, + .bit = 12, + .mask = 0x7 + }, { + .num = 2, + .pin = 24, + .reg = 0xd4, + .bit = 12, + .mask = 0x7 + }, +}; + +static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { .num = 2, .pin = 12, @@ -579,20 +678,22 @@ static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { }, }; -static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg, - u8 *bit, int *mask) +static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + int *reg, u8 *bit, int *mask) { - const struct rockchip_mux_recalced_data *data = NULL; + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_mux_recalced_data *data; int i; - for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++) - if (rk3328_mux_recalced_data[i].num == bank_num && - rk3328_mux_recalced_data[i].pin == pin) { - data = &rk3328_mux_recalced_data[i]; + for (i = 0; i < ctrl->niomux_recalced; i++) { + data = &ctrl->iomux_recalced[i]; + if (data->num == bank->bank_num && + data->pin == pin) break; - } + } - if (!data) + if (i >= ctrl->niomux_recalced) return; *reg = data->reg; @@ -600,6 +701,59 @@ static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg, *bit = data->bit; } +static struct rockchip_mux_route_data rk3128_mux_route_data[] = { + { + /* spi-0 */ + .bank_num = 1, + .pin = 10, + .func = 1, + .route_offset = 0x144, + .route_val = BIT(16 + 3) | BIT(16 + 4), + }, { + /* spi-1 */ + .bank_num = 1, + .pin = 27, + .func = 3, + .route_offset = 0x144, + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), + }, { + /* spi-2 */ + .bank_num = 0, + .pin = 13, + .func = 2, + .route_offset = 0x144, + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), + }, { + /* i2s-0 */ + .bank_num = 1, + .pin = 5, + .func = 1, + .route_offset = 0x144, + .route_val = BIT(16 + 5), + }, { + /* i2s-1 */ + .bank_num = 0, + .pin = 14, + .func = 1, + .route_offset = 0x144, + .route_val = BIT(16 + 5) | BIT(5), + }, { + /* emmc-0 */ + .bank_num = 1, + .pin = 22, + .func = 2, + .route_offset = 0x144, + .route_val = BIT(16 + 6), + }, { + /* emmc-1 */ + .bank_num = 2, + .pin = 4, + .func = 2, + .route_offset = 0x144, + .route_val = BIT(16 + 6) | BIT(6), + }, +}; + static struct rockchip_mux_route_data rk3228_mux_route_data[] = { { /* pwm0-0 */ @@ -877,7 +1031,6 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; int iomux_num = (pin / 8); struct regmap *regmap; unsigned int val; @@ -916,8 +1069,8 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) mask = 0x3; } - if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) - ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); ret = regmap_read(regmap, reg, &val); if (ret) @@ -967,7 +1120,6 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; int iomux_num = (pin / 8); struct regmap *regmap; int reg, ret, mask, mux_type; @@ -1005,8 +1157,8 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) mask = 0x3; } - if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) - ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); if (bank->route_mask & BIT(pin)) { if (rockchip_get_mux_route(bank, pin, mux, &route_reg, @@ -1084,6 +1236,36 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= RV1108_DRV_BITS_PER_PIN; } +#define RV1108_SCHMITT_PMU_OFFSET 0x30 +#define RV1108_SCHMITT_GRF_OFFSET 0x388 +#define RV1108_SCHMITT_BANK_STRIDE 8 +#define RV1108_SCHMITT_PINS_PER_GRF_REG 16 +#define RV1108_SCHMITT_PINS_PER_PMU_REG 8 + +static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int pins_per_reg; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RV1108_SCHMITT_PMU_OFFSET; + pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; + } else { + *regmap = info->regmap_base; + *reg = RV1108_SCHMITT_GRF_OFFSET; + pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; + *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; + } + *reg += ((pin_num / pins_per_reg) * 4); + *bit = pin_num % pins_per_reg; + + return 0; +} + #define RK2928_PULL_OFFSET 0x118 #define RK2928_PULL_PINS_PER_REG 16 #define RK2928_PULL_BANK_STRIDE 8 @@ -1102,6 +1284,22 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit = pin_num % RK2928_PULL_PINS_PER_REG; }; +#define RK3128_PULL_OFFSET 0x118 + +static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3128_PULL_OFFSET; + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; + *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); + + *bit = pin_num % RK2928_PULL_PINS_PER_REG; +} + #define RK3188_PULL_OFFSET 0x164 #define RK3188_PULL_BITS_PER_PIN 2 #define RK3188_PULL_PINS_PER_REG 8 @@ -1571,6 +1769,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) switch (ctrl->type) { case RK2928: + case RK3128: return !(data & BIT(bit)) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE; @@ -1611,6 +1810,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, switch (ctrl->type) { case RK2928: + case RK3128: data = BIT(bit + 16); if (pull == PIN_CONFIG_BIAS_DISABLE) data |= BIT(bit); @@ -1865,6 +2065,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, { switch (ctrl->type) { case RK2928: + case RK3128: return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || pull == PIN_CONFIG_BIAS_DISABLE); case RK3066B: @@ -2853,6 +3054,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } + /* calculate the per-bank recalced_mask */ + for (j = 0; j < ctrl->niomux_recalced; j++) { + int pin = 0; + + if (ctrl->iomux_recalced[j].num == bank->bank_num) { + pin = ctrl->iomux_recalced[j].pin; + bank->recalced_mask |= BIT(pin); + } + } + /* calculate the per-bank route_mask */ for (j = 0; j < ctrl->niomux_routes; j++) { int pin = 0; @@ -3015,8 +3226,11 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .type = RV1108, .grf_mux_offset = 0x10, .pmu_mux_offset = 0x0, + .iomux_recalced = rv1108_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), .pull_calc_reg = rv1108_calc_pull_reg_and_bit, .drv_calc_reg = rv1108_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, }; static struct rockchip_pin_bank rk2928_pin_banks[] = { @@ -3083,6 +3297,26 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { .grf_mux_offset = 0x60, }; +static struct rockchip_pin_bank rk3128_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3128_pin_ctrl = { + .pin_banks = rk3128_pin_banks, + .nr_banks = ARRAY_SIZE(rk3128_pin_banks), + .label = "RK3128-GPIO", + .type = RK3128, + .grf_mux_offset = 0xa8, + .iomux_recalced = rk3128_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), + .iomux_routes = rk3128_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), + .pull_calc_reg = rk3128_calc_pull_reg_and_bit, +}; + static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), PIN_BANK(1, 32, "gpio1"), @@ -3165,12 +3399,12 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT | IOMUX_RECALCED, - IOMUX_WIDTH_3BIT | IOMUX_RECALCED, + IOMUX_WIDTH_3BIT, + IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_3BIT, - IOMUX_WIDTH_3BIT | IOMUX_RECALCED, + IOMUX_WIDTH_3BIT, 0, 0), }; @@ -3181,11 +3415,12 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .label = "RK3328-GPIO", .type = RK3288, .grf_mux_offset = 0x0, + .iomux_recalced = rk3328_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), .iomux_routes = rk3328_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), .pull_calc_reg = rk3228_calc_pull_reg_and_bit, .drv_calc_reg = rk3228_calc_drv_reg_and_bit, - .iomux_recalc = rk3328_recalc_mux, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; @@ -3290,6 +3525,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = &rk3066a_pin_ctrl }, { .compatible = "rockchip,rk3066b-pinctrl", .data = &rk3066b_pin_ctrl }, + { .compatible = "rockchip,rk3128-pinctrl", + .data = (void *)&rk3128_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = &rk3188_pin_ctrl }, { .compatible = "rockchip,rk3228-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index dc164da10446..04d058706b80 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -723,7 +723,7 @@ static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, rza1_pin_set(port, gpio, value); } -static struct gpio_chip rza1_gpiochip_template = { +static const struct gpio_chip rza1_gpiochip_template = { .request = rza1_gpio_request, .free = rza1_gpio_free, .get_direction = rza1_gpio_get_direction, @@ -1026,7 +1026,7 @@ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, return 0; } -static struct pinmux_ops rza1_pinmux_ops = { +static const struct pinmux_ops rza1_pinmux_ops = { .get_functions_count = pinmux_generic_get_function_count, .get_function_name = pinmux_generic_get_function_name, .get_function_groups = pinmux_generic_get_function_groups, @@ -1088,7 +1088,7 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, */ pinctrl_base = of_args.args[1]; gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base); - if (gpioport > RZA1_NPORTS) { + if (gpioport >= RZA1_NPORTS) { dev_err(rza1_pctl->dev, "Invalid values in property %s\n", list_name); return -EINVAL; @@ -1096,8 +1096,8 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, *chip = rza1_gpiochip_template; chip->base = -1; - chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s-%u", - np->name, gpioport); + chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s", + np->name); chip->ngpio = of_args.args[2]; chip->of_node = np; chip->parent = rza1_pctl->dev; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 3ae8066bc127..a5205b94b2e6 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -861,7 +861,7 @@ static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, { } -static struct pinctrl_ops st_pctlops = { +static const struct pinctrl_ops st_pctlops = { .get_groups_count = st_pctl_get_groups_count, .get_group_pins = st_pctl_get_group_pins, .get_group_name = st_pctl_get_group_name, @@ -928,7 +928,7 @@ static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops st_pmxops = { +static const struct pinmux_ops st_pmxops = { .get_functions_count = st_pmx_get_funcs_count, .get_function_name = st_pmx_get_fname, .get_function_groups = st_pmx_get_groups, @@ -1025,7 +1025,7 @@ static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, ST_PINCONF_UNPACK_RT_DELAY(config)); } -static struct pinconf_ops st_confops = { +static const struct pinconf_ops st_confops = { .pin_config_get = st_pinconf_get, .pin_config_set = st_pinconf_set, .pin_config_dbg_show = st_pinconf_dbg_show, @@ -1442,7 +1442,7 @@ static void st_gpio_irqmux_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static struct gpio_chip st_gpio_template = { +static const struct gpio_chip st_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .get = st_gpio_get, @@ -1521,7 +1521,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, * [irqN]----> [gpio-bank (n)] */ - if (of_irq_to_resource(np, 0, &irq_res)) { + if (of_irq_to_resource(np, 0, &irq_res) > 0) { gpio_irq = irq_res.start; gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip, gpio_irq, st_gpio_irq_handler); @@ -1537,7 +1537,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, return err; } } else { - dev_info(dev, "No IRQ support for %s bank\n", np->full_name); + dev_info(dev, "No IRQ support for %pOF bank\n", np); } return 0; diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c index edfba506e958..2e90a6d8fb3b 100644 --- a/drivers/pinctrl/pinctrl-tb10x.c +++ b/drivers/pinctrl/pinctrl-tb10x.c @@ -557,8 +557,8 @@ static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl, int ret = 0; if (of_property_read_string(np_config, "abilis,function", &string)) { - pr_err("%s: No abilis,function property in device tree.\n", - np_config->full_name); + pr_err("%pOF: No abilis,function property in device tree.\n", + np_config); return -EINVAL; } @@ -577,7 +577,7 @@ out: return ret; } -static struct pinctrl_ops tb10x_pinctrl_ops = { +static const struct pinctrl_ops tb10x_pinctrl_ops = { .get_groups_count = tb10x_get_groups_count, .get_group_name = tb10x_get_group_name, .get_group_pins = tb10x_get_group_pins, @@ -738,7 +738,7 @@ static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl, return 0; } -static struct pinmux_ops tb10x_pinmux_ops = { +static const struct pinmux_ops tb10x_pinmux_ops = { .get_functions_count = tb10x_get_functions_count, .get_function_name = tb10x_get_function_name, .get_function_groups = tb10x_get_function_groups, diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c index e70e36283b3b..5cfa93cecf73 100644 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c @@ -486,7 +486,7 @@ static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops tz1090_pdc_pinctrl_ops = { +static const struct pinctrl_ops tz1090_pdc_pinctrl_ops = { .get_groups_count = tz1090_pdc_pinctrl_get_groups_count, .get_group_name = tz1090_pdc_pinctrl_get_group_name, .get_group_pins = tz1090_pdc_pinctrl_get_group_pins, @@ -631,7 +631,7 @@ static void tz1090_pdc_pinctrl_gpio_disable_free( } } -static struct pinmux_ops tz1090_pdc_pinmux_ops = { +static const struct pinmux_ops tz1090_pdc_pinmux_ops = { .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, .get_function_name = tz1090_pdc_pinctrl_get_func_name, .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, @@ -905,7 +905,7 @@ next_config: return 0; } -static struct pinconf_ops tz1090_pdc_pinconf_ops = { +static const struct pinconf_ops tz1090_pdc_pinconf_ops = { .is_generic = true, .pin_config_get = tz1090_pdc_pinconf_get, .pin_config_set = tz1090_pdc_pinconf_set, diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c index 04cbe530bf29..74d1ffcc2199 100644 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ b/drivers/pinctrl/pinctrl-tz1090.c @@ -1201,7 +1201,7 @@ static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops tz1090_pinctrl_ops = { +static const struct pinctrl_ops tz1090_pinctrl_ops = { .get_groups_count = tz1090_pinctrl_get_groups_count, .get_group_name = tz1090_pinctrl_get_group_name, .get_group_pins = tz1090_pinctrl_get_group_pins, @@ -1513,7 +1513,7 @@ static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, tz1090_pinctrl_gpio_select(pmx, pin, false); } -static struct pinmux_ops tz1090_pinmux_ops = { +static const struct pinmux_ops tz1090_pinmux_ops = { .get_functions_count = tz1090_pinctrl_get_funcs_count, .get_function_name = tz1090_pinctrl_get_func_name, .get_function_groups = tz1090_pinctrl_get_func_groups, @@ -1920,7 +1920,7 @@ next_config: return 0; } -static struct pinconf_ops tz1090_pinconf_ops = { +static const struct pinconf_ops tz1090_pinconf_ops = { .is_generic = true, .pin_config_get = tz1090_pinconf_get, .pin_config_set = tz1090_pinconf_set, diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index b51a46dfdcc3..a0daf27042bd 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -45,7 +45,7 @@ * @syscon: Syscon regmap * @pctrl_offset: Offset for pinctrl into the @syscon space * @groups: Pingroups - * @ngroupos: Number of @groups + * @ngroups: Number of @groups * @funcs: Pinmux functions * @nfuncs: Number of @funcs */ @@ -62,7 +62,7 @@ struct zynq_pinctrl { struct zynq_pctrl_group { const char *name; const unsigned int *pins; - const unsigned npins; + const unsigned int npins; }; /** @@ -841,7 +841,7 @@ static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev) } static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned int selector) { struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -849,9 +849,9 @@ static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev, } static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned selector, - const unsigned **pins, - unsigned *num_pins) + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) { struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -878,7 +878,7 @@ static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev) } static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev, - unsigned selector) + unsigned int selector) { struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -886,7 +886,7 @@ static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev, } static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev, - unsigned selector, + unsigned int selector, const char * const **groups, unsigned * const num_groups) { @@ -898,8 +898,8 @@ static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev, } static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) + unsigned int function, + unsigned int group) { int i, ret; struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -986,8 +986,8 @@ static const struct pinconf_generic_params zynq_dt_params[] = { }; #ifdef CONFIG_DEBUG_FS -static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] = { - PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true), +static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] + = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true), }; #endif @@ -997,7 +997,7 @@ static unsigned int zynq_pinconf_iostd_get(u32 reg) } static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *config) { u32 reg; @@ -1054,9 +1054,9 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, } static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, - unsigned pin, + unsigned int pin, unsigned long *configs, - unsigned num_configs) + unsigned int num_configs) { int i, ret; u32 reg; @@ -1130,9 +1130,9 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, } static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned selector, + unsigned int selector, unsigned long *configs, - unsigned num_configs) + unsigned int num_configs) { int i, ret; struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 16b3ae5e4f44..55502fc4479c 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -61,7 +61,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev) return 0; } -int pinmux_validate_map(struct pinctrl_map const *map, int i) +int pinmux_validate_map(const struct pinctrl_map *map, int i) { if (!map->data.mux.function) { pr_err("failed to register map %s (%d): no function given\n", @@ -312,7 +312,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, return -EINVAL; } -int pinmux_map_to_setting(struct pinctrl_map const *map, +int pinmux_map_to_setting(const struct pinctrl_map *map, struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; @@ -372,12 +372,12 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, return 0; } -void pinmux_free_setting(struct pinctrl_setting const *setting) +void pinmux_free_setting(const struct pinctrl_setting *setting) { /* This function is currently unused */ } -int pinmux_enable_setting(struct pinctrl_setting const *setting) +int pinmux_enable_setting(const struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; @@ -458,7 +458,7 @@ err_pin_request: return ret; } -void pinmux_disable_setting(struct pinctrl_setting const *setting) +void pinmux_disable_setting(const struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; @@ -627,7 +627,7 @@ static int pinmux_pins_show(struct seq_file *s, void *what) return 0; } -void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map) +void pinmux_show_map(struct seq_file *s, const struct pinctrl_map *map) { seq_printf(s, "group %s\nfunction %s\n", map->data.mux.group ? map->data.mux.group : "(default)", @@ -635,7 +635,7 @@ void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map) } void pinmux_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting) + const struct pinctrl_setting *setting) { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinmux_ops *pmxops = pctldev->desc->pmxops; @@ -833,7 +833,7 @@ EXPORT_SYMBOL_GPL(pinmux_generic_remove_function); void pinmux_generic_free_functions(struct pinctrl_dev *pctldev) { struct radix_tree_iter iter; - void **slot; + void __rcu **slot; radix_tree_for_each_slot(slot, &pctldev->pin_function_tree, &iter, 0) radix_tree_delete(&pctldev->pin_function_tree, iter.index); diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 248d8ea30e26..a331fcdbedd9 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -14,7 +14,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev); -int pinmux_validate_map(struct pinctrl_map const *map, int i); +int pinmux_validate_map(const struct pinctrl_map *map, int i); int pinmux_request_gpio(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, @@ -25,11 +25,11 @@ int pinmux_gpio_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, bool input); -int pinmux_map_to_setting(struct pinctrl_map const *map, +int pinmux_map_to_setting(const struct pinctrl_map *map, struct pinctrl_setting *setting); -void pinmux_free_setting(struct pinctrl_setting const *setting); -int pinmux_enable_setting(struct pinctrl_setting const *setting); -void pinmux_disable_setting(struct pinctrl_setting const *setting); +void pinmux_free_setting(const struct pinctrl_setting *setting); +int pinmux_enable_setting(const struct pinctrl_setting *setting); +void pinmux_disable_setting(const struct pinctrl_setting *setting); #else @@ -38,7 +38,7 @@ static inline int pinmux_check_ops(struct pinctrl_dev *pctldev) return 0; } -static inline int pinmux_validate_map(struct pinctrl_map const *map, int i) +static inline int pinmux_validate_map(const struct pinctrl_map *map, int i) { return 0; } @@ -63,23 +63,22 @@ static inline int pinmux_gpio_direction(struct pinctrl_dev *pctldev, return 0; } -static inline int pinmux_map_to_setting(struct pinctrl_map const *map, +static inline int pinmux_map_to_setting(const struct pinctrl_map *map, struct pinctrl_setting *setting) { return 0; } -static inline void pinmux_free_setting(struct pinctrl_setting const *setting) +static inline void pinmux_free_setting(const struct pinctrl_setting *setting) { } -static inline int pinmux_enable_setting(struct pinctrl_setting const *setting) +static inline int pinmux_enable_setting(const struct pinctrl_setting *setting) { return 0; } -static inline void pinmux_disable_setting( - struct pinctrl_setting const *setting) +static inline void pinmux_disable_setting(const struct pinctrl_setting *setting) { } @@ -87,21 +86,21 @@ static inline void pinmux_disable_setting( #if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS) -void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map); +void pinmux_show_map(struct seq_file *s, const struct pinctrl_map *map); void pinmux_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting); + const struct pinctrl_setting *setting); void pinmux_init_device_debugfs(struct dentry *devroot, struct pinctrl_dev *pctldev); #else static inline void pinmux_show_map(struct seq_file *s, - struct pinctrl_map const *map) + const struct pinctrl_map *map) { } static inline void pinmux_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting) + const struct pinctrl_setting *setting) { } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c index cd96699b1929..bcf9e615ff61 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -295,6 +295,12 @@ enum apq8064_functions { APQ_MUX_cam_mclk, APQ_MUX_codec_mic_i2s, APQ_MUX_codec_spkr_i2s, + APQ_MUX_gp_clk_0a, + APQ_MUX_gp_clk_0b, + APQ_MUX_gp_clk_1a, + APQ_MUX_gp_clk_1b, + APQ_MUX_gp_clk_2a, + APQ_MUX_gp_clk_2b, APQ_MUX_gpio, APQ_MUX_gsbi1, APQ_MUX_gsbi2, @@ -354,6 +360,24 @@ static const char * const gpio_groups[] = { "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89" }; +static const char * const gp_clk_0a_groups[] = { + "gpio3" +}; +static const char * const gp_clk_0b_groups[] = { + "gpio34" +}; +static const char * const gp_clk_1a_groups[] = { + "gpio4" +}; +static const char * const gp_clk_1b_groups[] = { + "gpio50" +}; +static const char * const gp_clk_2a_groups[] = { + "gpio32" +}; +static const char * const gp_clk_2b_groups[] = { + "gpio25" +}; static const char * const ps_hold_groups[] = { "gpio78" }; @@ -452,6 +476,12 @@ static const struct msm_function apq8064_functions[] = { FUNCTION(cam_mclk), FUNCTION(codec_mic_i2s), FUNCTION(codec_spkr_i2s), + FUNCTION(gp_clk_0a), + FUNCTION(gp_clk_0b), + FUNCTION(gp_clk_1a), + FUNCTION(gp_clk_1b), + FUNCTION(gp_clk_2a), + FUNCTION(gp_clk_2b), FUNCTION(gpio), FUNCTION(gsbi1), FUNCTION(gsbi2), @@ -490,8 +520,8 @@ static const struct msm_pingroup apq8064_groups[] = { PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, NA, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, NA, NA, cam_mclk, gp_clk_1a, NA, NA, NA, NA, NA, NA), PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), @@ -512,16 +542,16 @@ static const struct msm_pingroup apq8064_groups[] = { PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, gp_clk_2b, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), - PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), + PINGROUP(32, mi2s, gp_clk_2a, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), @@ -537,7 +567,7 @@ static const struct msm_pingroup apq8064_groups[] = { PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c index 743d1f458205..1979b14b6fc3 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c @@ -277,12 +277,49 @@ DECLARE_QCA_GPIO_PINS(99); enum ipq4019_functions { qca_mux_gpio, - qca_mux_blsp_uart1, + qca_mux_aud_pin, + qca_mux_audio_pwm, qca_mux_blsp_i2c0, qca_mux_blsp_i2c1, - qca_mux_blsp_uart0, - qca_mux_blsp_spi1, qca_mux_blsp_spi0, + qca_mux_blsp_spi1, + qca_mux_blsp_uart0, + qca_mux_blsp_uart1, + qca_mux_chip_rst, + qca_mux_i2s_rx, + qca_mux_i2s_spdif_in, + qca_mux_i2s_spdif_out, + qca_mux_i2s_td, + qca_mux_i2s_tx, + qca_mux_jtag, + qca_mux_led0, + qca_mux_led1, + qca_mux_led2, + qca_mux_led3, + qca_mux_led4, + qca_mux_led5, + qca_mux_led6, + qca_mux_led7, + qca_mux_led8, + qca_mux_led9, + qca_mux_led10, + qca_mux_led11, + qca_mux_mdc, + qca_mux_mdio, + qca_mux_pcie, + qca_mux_pmu, + qca_mux_prng_rosc, + qca_mux_qpic, + qca_mux_rgmii, + qca_mux_rmii, + qca_mux_sdio, + qca_mux_smart0, + qca_mux_smart1, + qca_mux_smart2, + qca_mux_smart3, + qca_mux_tm, + qca_mux_wifi0, + qca_mux_wifi1, qca_mux_NA, }; @@ -303,108 +340,331 @@ static const char * const gpio_groups[] = { "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", }; - -static const char * const blsp_uart1_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11", +static const char * const aud_pin_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; +static const char * const audio_pwm_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", "gpio64", "gpio65", "gpio66", + "gpio67", }; static const char * const blsp_i2c0_groups[] = { "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59", }; -static const char * const blsp_spi0_groups[] = { - "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", - "gpio54", "gpio55", "gpio56", "gpio57", -}; static const char * const blsp_i2c1_groups[] = { "gpio12", "gpio13", "gpio34", "gpio35", }; -static const char * const blsp_uart0_groups[] = { - "gpio16", "gpio17", "gpio60", "gpio61", +static const char * const blsp_spi0_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", "gpio45", "gpio54", "gpio55", + "gpio56", "gpio57", }; static const char * const blsp_spi1_groups[] = { "gpio44", "gpio45", "gpio46", "gpio47", }; +static const char * const blsp_uart0_groups[] = { + "gpio16", "gpio17", "gpio60", "gpio61", +}; +static const char * const blsp_uart1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const chip_rst_groups[] = { + "gpio62", +}; +static const char * const i2s_rx_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio58", "gpio60", "gpio61", "gpio63", +}; +static const char * const i2s_spdif_in_groups[] = { + "gpio34", "gpio59", "gpio63", +}; +static const char * const i2s_spdif_out_groups[] = { + "gpio35", "gpio62", "gpio63", +}; +static const char * const i2s_td_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio54", "gpio55", "gpio56", "gpio63", +}; +static const char * const i2s_tx_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio52", "gpio53", "gpio57", "gpio60", + "gpio61", +}; +static const char * const jtag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", +}; +static const char * const led0_groups[] = { + "gpio16", "gpio36", "gpio60", +}; +static const char * const led1_groups[] = { + "gpio17", "gpio37", "gpio61", +}; +static const char * const led2_groups[] = { + "gpio36", "gpio38", "gpio58", +}; +static const char * const led3_groups[] = { + "gpio39", +}; +static const char * const led4_groups[] = { + "gpio40", +}; +static const char * const led5_groups[] = { + "gpio44", +}; +static const char * const led6_groups[] = { + "gpio45", +}; +static const char * const led7_groups[] = { + "gpio46", +}; +static const char * const led8_groups[] = { + "gpio47", +}; +static const char * const led9_groups[] = { + "gpio48", +}; +static const char * const led10_groups[] = { + "gpio49", +}; +static const char * const led11_groups[] = { + "gpio50", +}; +static const char * const mdc_groups[] = { + "gpio7", "gpio52", +}; +static const char * const mdio_groups[] = { + "gpio6", "gpio53", +}; +static const char * const pcie_groups[] = { + "gpio39", "gpio52", +}; +static const char * const pmu_groups[] = { + "gpio54", "gpio55", +}; +static const char * const prng_rosc_groups[] = { + "gpio53", +}; +static const char * const qpic_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", +}; +static const char * const rgmii_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const rmii_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", +}; +static const char * const sdio_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", +}; +static const char * const smart0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46", + "gpio47", +}; +static const char * const smart1_groups[] = { + "gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60", + "gpio61", +}; +static const char * const smart2_groups[] = { + "gpio40", "gpio41", "gpio48", "gpio49", +}; +static const char * const smart3_groups[] = { + "gpio58", "gpio59", "gpio60", "gpio61", +}; +static const char * const tm_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const wifi0_groups[] = { + "gpio37", "gpio40", "gpio41", "gpio42", "gpio50", "gpio51", "gpio52", + "gpio53", "gpio56", "gpio57", "gpio58", "gpio98", +}; +static const char * const wifi1_groups[] = { + "gpio37", "gpio40", "gpio41", "gpio43", "gpio50", "gpio51", "gpio52", + "gpio53", "gpio56", "gpio57", "gpio58", "gpio98", +}; static const struct msm_function ipq4019_functions[] = { - FUNCTION(gpio), - FUNCTION(blsp_uart1), + FUNCTION(aud_pin), + FUNCTION(audio_pwm), FUNCTION(blsp_i2c0), FUNCTION(blsp_i2c1), - FUNCTION(blsp_uart0), - FUNCTION(blsp_spi1), FUNCTION(blsp_spi0), + FUNCTION(blsp_spi1), + FUNCTION(blsp_uart0), + FUNCTION(blsp_uart1), + FUNCTION(chip_rst), + FUNCTION(gpio), + FUNCTION(i2s_rx), + FUNCTION(i2s_spdif_in), + FUNCTION(i2s_spdif_out), + FUNCTION(i2s_td), + FUNCTION(i2s_tx), + FUNCTION(jtag), + FUNCTION(led0), + FUNCTION(led1), + FUNCTION(led2), + FUNCTION(led3), + FUNCTION(led4), + FUNCTION(led5), + FUNCTION(led6), + FUNCTION(led7), + FUNCTION(led8), + FUNCTION(led9), + FUNCTION(led10), + FUNCTION(led11), + FUNCTION(mdc), + FUNCTION(mdio), + FUNCTION(pcie), + FUNCTION(pmu), + FUNCTION(prng_rosc), + FUNCTION(qpic), + FUNCTION(rgmii), + FUNCTION(rmii), + FUNCTION(sdio), + FUNCTION(smart0), + FUNCTION(smart1), + FUNCTION(smart2), + FUNCTION(smart3), + FUNCTION(tm), + FUNCTION(wifi0), + FUNCTION(wifi1), }; static const struct msm_pingroup ipq4019_groups[] = { - PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA, + NA, NA, NA, NA, NA), + PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA, + NA, NA, NA, NA), + PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, + NA, NA, NA), + PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA, + NA, NA, NA), + PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA, + NA, NA, NA, NA, NA), + PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, + NA, NA, NA), + PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA, + NA, NA, NA), + PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA, + NA, NA, NA, NA), + PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA, + NA, NA, NA, NA), + PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm, + wifi0, wifi1, NA, NA, NA), + PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA, + NA, NA, tm, NA, NA, NA), + PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx, + NA, NA, NA, NA, NA, tm, NA), + PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx, + NA, NA, NA, NA, NA, tm, NA), + PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA, + tm, NA, NA, NA), + PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out, + i2s_spdif_in, NA, NA, NA, NA, tm, NA), + PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA, NA), + PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), @@ -433,7 +693,8 @@ static const struct msm_pingroup ipq4019_groups[] = { PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, + NA), PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), }; @@ -445,6 +706,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = { .groups = ipq4019_groups, .ngroups = ARRAY_SIZE(ipq4019_groups), .ngpios = 100, + .pull_no_keeper = true, }; static int ipq4019_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 273badd92561..ff491da64dab 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -202,10 +202,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, return 0; } -#define MSM_NO_PULL 0 -#define MSM_PULL_DOWN 1 -#define MSM_KEEPER 2 -#define MSM_PULL_UP 3 +#define MSM_NO_PULL 0 +#define MSM_PULL_DOWN 1 +#define MSM_KEEPER 2 +#define MSM_PULL_UP_NO_KEEPER 2 +#define MSM_PULL_UP 3 static unsigned msm_regval_to_drive(u32 val) { @@ -243,10 +244,16 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, arg = arg == MSM_PULL_DOWN; break; case PIN_CONFIG_BIAS_BUS_HOLD: + if (pctrl->soc->pull_no_keeper) + return -ENOTSUPP; + arg = arg == MSM_KEEPER; break; case PIN_CONFIG_BIAS_PULL_UP: - arg = arg == MSM_PULL_UP; + if (pctrl->soc->pull_no_keeper) + arg = arg == MSM_PULL_UP_NO_KEEPER; + else + arg = arg == MSM_PULL_UP; break; case PIN_CONFIG_DRIVE_STRENGTH: arg = msm_regval_to_drive(arg); @@ -309,10 +316,16 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, arg = MSM_PULL_DOWN; break; case PIN_CONFIG_BIAS_BUS_HOLD: + if (pctrl->soc->pull_no_keeper) + return -ENOTSUPP; + arg = MSM_KEEPER; break; case PIN_CONFIG_BIAS_PULL_UP: - arg = MSM_PULL_UP; + if (pctrl->soc->pull_no_keeper) + arg = MSM_PULL_UP_NO_KEEPER; + else + arg = MSM_PULL_UP; break; case PIN_CONFIG_DRIVE_STRENGTH: /* Check for invalid values */ @@ -521,7 +534,7 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) #define msm_gpio_dbg_show NULL #endif -static struct gpio_chip msm_gpio_template = { +static const struct gpio_chip msm_gpio_template = { .direction_input = msm_gpio_direction_input, .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 54fdd04ce9d5..9b9feea540ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -99,13 +99,14 @@ struct msm_pingroup { /** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration - * @pins: An array describing all pins the pin controller affects. - * @npins: The number of entries in @pins. - * @functions: An array describing all mux functions the SoC supports. - * @nfunctions: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The numbmer of entries in @groups. - * @ngpio: The number of pingroups the driver should expose as GPIOs. + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * @ngpio: The number of pingroups the driver should expose as GPIOs. + * @pull_no_keeper: The SoC does not support keeper bias. */ struct msm_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data { const struct msm_pingroup *groups; unsigned ngroups; unsigned ngpios; + bool pull_no_keeper; }; int msm_pinctrl_probe(struct platform_device *pdev, diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 664b641fd776..c2c0bab04257 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -40,6 +40,8 @@ #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd +#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 +#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 #define PMIC_MPP_REG_RT_STS 0x10 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 @@ -48,8 +50,11 @@ #define PMIC_GPIO_REG_MODE_CTL 0x40 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 +#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 +#define PMIC_GPIO_REG_DIG_IN_CTL 0x43 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 #define PMIC_GPIO_REG_EN_CTL 0x46 +#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A /* PMIC_GPIO_REG_MODE_CTL */ #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 @@ -58,6 +63,12 @@ #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 +#define PMIC_GPIO_MODE_DIGITAL_INPUT 0 +#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 +#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 +#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 +#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 + /* PMIC_GPIO_REG_DIG_VIN_CTL */ #define PMIC_GPIO_REG_VIN_SHIFT 0 #define PMIC_GPIO_REG_VIN_MASK 0x7 @@ -69,6 +80,16 @@ #define PMIC_GPIO_PULL_DOWN 4 #define PMIC_GPIO_PULL_DISABLE 5 +/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 +#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 +#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF + +/* PMIC_GPIO_REG_DIG_IN_CTL */ +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 +#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 +#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf + /* PMIC_GPIO_REG_DIG_OUT_CTL */ #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 @@ -88,9 +109,29 @@ #define PMIC_GPIO_PHYSICAL_OFFSET 1 +/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ +#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 + /* Qualcomm specific pin configurations */ #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) +#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) +#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) +#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) + +/* The index of each function in pmic_gpio_functions[] array */ +enum pmic_gpio_func_index { + PMIC_GPIO_FUNC_INDEX_NORMAL, + PMIC_GPIO_FUNC_INDEX_PAIRED, + PMIC_GPIO_FUNC_INDEX_FUNC1, + PMIC_GPIO_FUNC_INDEX_FUNC2, + PMIC_GPIO_FUNC_INDEX_FUNC3, + PMIC_GPIO_FUNC_INDEX_FUNC4, + PMIC_GPIO_FUNC_INDEX_DTEST1, + PMIC_GPIO_FUNC_INDEX_DTEST2, + PMIC_GPIO_FUNC_INDEX_DTEST3, + PMIC_GPIO_FUNC_INDEX_DTEST4, +}; /** * struct pmic_gpio_pad - keep current GPIO settings @@ -102,12 +143,16 @@ * open-drain or open-source mode. * @output_enabled: Set to true if GPIO output logic is enabled. * @input_enabled: Set to true if GPIO input buffer logic is enabled. + * @analog_pass: Set to true if GPIO is in analog-pass-through mode. + * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). * @num_sources: Number of power-sources supported by this GPIO. * @power_source: Current power-source used. * @buffer_type: Push-pull, open-drain or open-source. * @pullup: Constant current which flow trough GPIO output buffer. * @strength: No, Low, Medium, High * @function: See pmic_gpio_functions[] + * @atest: the ATEST selection for GPIO analog-pass-through mode + * @dtest_buffer: the DTEST buffer selection for digital input mode. */ struct pmic_gpio_pad { u16 base; @@ -117,12 +162,16 @@ struct pmic_gpio_pad { bool have_buffer; bool output_enabled; bool input_enabled; + bool analog_pass; + bool lv_mv_type; unsigned int num_sources; unsigned int power_source; unsigned int buffer_type; unsigned int pullup; unsigned int strength; unsigned int function; + unsigned int atest; + unsigned int dtest_buffer; }; struct pmic_gpio_state { @@ -135,12 +184,18 @@ struct pmic_gpio_state { static const struct pinconf_generic_params pmic_gpio_bindings[] = { {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, + {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, + {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, + {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, }; #ifdef CONFIG_DEBUG_FS static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), + PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), }; #endif @@ -153,10 +208,16 @@ static const char *const pmic_gpio_groups[] = { }; static const char *const pmic_gpio_functions[] = { - PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, - PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, - PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, - PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, + [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, + [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, + [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, + [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, + [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, + [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, + [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, + [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, + [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, + [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, }; static int pmic_gpio_read(struct pmic_gpio_state *state, @@ -244,25 +305,67 @@ static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned int val; int ret; + if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { + pr_err("function: %d is not defined\n", function); + return -EINVAL; + } + pad = pctldev->desc->pins[pin].drv_data; + /* + * Non-LV/MV subtypes only support 2 special functions, + * offsetting the dtestx function values by 2 + */ + if (!pad->lv_mv_type) { + if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || + function == PMIC_GPIO_FUNC_INDEX_FUNC4) { + pr_err("LV/MV subtype doesn't have func3/func4\n"); + return -EINVAL; + } + if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) + function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3); + } pad->function = function; - val = 0; - if (pad->output_enabled) { - if (pad->input_enabled) - val = 2; - else - val = 1; - } + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; - val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; - val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; - val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + if (pad->lv_mv_type) { + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; - ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); - if (ret < 0) - return ret; + val = pad->atest - 1; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; @@ -322,6 +425,15 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, case PMIC_GPIO_CONF_STRENGTH: arg = pad->strength; break; + case PMIC_GPIO_CONF_ATEST: + arg = pad->atest; + break; + case PMIC_GPIO_CONF_ANALOG_PASS: + arg = pad->analog_pass; + break; + case PMIC_GPIO_CONF_DTEST_BUFFER: + arg = pad->dtest_buffer; + break; default: return -EINVAL; } @@ -375,7 +487,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pad->is_enabled = false; break; case PIN_CONFIG_POWER_SOURCE: - if (arg > pad->num_sources) + if (arg >= pad->num_sources) return -EINVAL; pad->power_source = arg; break; @@ -396,6 +508,21 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; pad->strength = arg; break; + case PMIC_GPIO_CONF_ATEST: + if (!pad->lv_mv_type || arg > 4) + return -EINVAL; + pad->atest = arg; + break; + case PMIC_GPIO_CONF_ANALOG_PASS: + if (!pad->lv_mv_type) + return -EINVAL; + pad->analog_pass = true; + break; + case PMIC_GPIO_CONF_DTEST_BUFFER: + if (arg > 4) + return -EINVAL; + pad->dtest_buffer = arg; + break; default: return -EINVAL; } @@ -420,19 +547,60 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, if (ret < 0) return ret; - val = 0; - if (pad->output_enabled) { - if (pad->input_enabled) - val = 2; - else - val = 1; + if (pad->dtest_buffer == 0) { + val = 0; + } else { + if (pad->lv_mv_type) { + val = pad->dtest_buffer - 1; + val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; + } else { + val = BIT(pad->dtest_buffer - 1); + } } + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); + if (ret < 0) + return ret; + + if (pad->analog_pass) + val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; + else if (pad->output_enabled && pad->input_enabled) + val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; + else if (pad->output_enabled) + val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; + else + val = PMIC_GPIO_MODE_DIGITAL_INPUT; - val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; - val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; - val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + if (pad->lv_mv_type) { + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; - return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); + val = pad->atest - 1; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); + if (ret < 0) + return ret; + + val = pad->out_value + << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; + val |= pad->function + & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + ret = pmic_gpio_write(state, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); + if (ret < 0) + return ret; + } else { + val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; + val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); + if (ret < 0) + return ret; + } + + return ret; } static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, @@ -440,7 +608,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, { struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); struct pmic_gpio_pad *pad; - int ret, val; + int ret, val, function; static const char *const biases[] = { "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", @@ -462,7 +630,6 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { seq_puts(s, " ---"); } else { - if (pad->input_enabled) { ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); if (ret < 0) @@ -471,14 +638,29 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; pad->out_value = ret; } - - seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); - seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]); + /* + * For the non-LV/MV subtypes only 2 special functions are + * available, offsetting the dtest function values by 2. + */ + function = pad->function; + if (!pad->lv_mv_type && + pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) + function += PMIC_GPIO_FUNC_INDEX_DTEST1 - + PMIC_GPIO_FUNC_INDEX_FUNC3; + + if (pad->analog_pass) + seq_puts(s, " analog-pass"); + else + seq_printf(s, " %-4s", + pad->output_enabled ? "out" : "in"); + seq_printf(s, " %-7s", pmic_gpio_functions[function]); seq_printf(s, " vin-%d", pad->power_source); seq_printf(s, " %-27s", biases[pad->pullup]); seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); seq_printf(s, " %-7s", strengths[pad->strength]); + seq_printf(s, " atest-%d", pad->atest); + seq_printf(s, " dtest-%d", pad->dtest_buffer); } } @@ -618,40 +800,71 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state, case PMIC_GPIO_SUBTYPE_GPIOC_8CH: pad->num_sources = 8; break; + case PMIC_GPIO_SUBTYPE_GPIO_LV: + pad->num_sources = 1; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; + case PMIC_GPIO_SUBTYPE_GPIO_MV: + pad->num_sources = 2; + pad->have_buffer = true; + pad->lv_mv_type = true; + break; default: dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); return -ENODEV; } - val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); - if (val < 0) - return val; + if (pad->lv_mv_type) { + val = pmic_gpio_read(state, pad, + PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); + if (val < 0) + return val; + + pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); + pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; + + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; + } else { + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); + if (val < 0) + return val; + + pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; - pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; + dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; + dir &= PMIC_GPIO_REG_MODE_DIR_MASK; + pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; + pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; + } - dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; - dir &= PMIC_GPIO_REG_MODE_DIR_MASK; switch (dir) { - case 0: + case PMIC_GPIO_MODE_DIGITAL_INPUT: pad->input_enabled = true; pad->output_enabled = false; break; - case 1: + case PMIC_GPIO_MODE_DIGITAL_OUTPUT: pad->input_enabled = false; pad->output_enabled = true; break; - case 2: + case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: pad->input_enabled = true; pad->output_enabled = true; break; + case PMIC_GPIO_MODE_ANALOG_PASS_THRU: + if (!pad->lv_mv_type) + return -ENODEV; + pad->analog_pass = true; + break; default: dev_err(state->dev, "unknown GPIO direction\n"); return -ENODEV; } - pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; - pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; - val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); if (val < 0) return val; @@ -666,6 +879,18 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state, pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; pad->pullup &= PMIC_GPIO_REG_PULL_MASK; + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); + if (val < 0) + return val; + + if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) + pad->dtest_buffer = + (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; + else if (!pad->lv_mv_type) + pad->dtest_buffer = ffs(val); + else + pad->dtest_buffer = 0; + val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); if (val < 0) return val; @@ -676,6 +901,14 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state, pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; + if (pad->lv_mv_type) { + val = pmic_gpio_read(state, pad, + PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); + if (val < 0) + return val; + pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; + } + /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ pad->is_enabled = true; return 0; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index d3f5501d17ee..f53e32a9d8fc 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -588,7 +588,7 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) #define pm8xxx_gpio_dbg_show NULL #endif -static struct gpio_chip pm8xxx_gpio_template = { +static const struct gpio_chip pm8xxx_gpio_template = { .direction_input = pm8xxx_gpio_direction_input, .direction_output = pm8xxx_gpio_direction_output, .get = pm8xxx_gpio_get, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 0d1392fc32dd..1e513bd6d0a9 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -643,7 +643,7 @@ static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) #define pm8xxx_mpp_dbg_show NULL #endif -static struct gpio_chip pm8xxx_mpp_template = { +static const struct gpio_chip pm8xxx_mpp_template = { .direction_input = pm8xxx_mpp_direction_input, .direction_output = pm8xxx_mpp_direction_output, .get = pm8xxx_mpp_get, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 731530a9ce38..c8d0de7ea160 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -31,6 +31,8 @@ #include <linux/err.h> #include <linux/soc/samsung/exynos-pmu.h> +#include <dt-bindings/pinctrl/samsung.h> + #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" @@ -149,15 +151,10 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) static int exynos_irq_request_resources(struct irq_data *irqd) { - struct irq_chip *chip = irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); const struct samsung_pin_bank_type *bank_type = bank->type; - unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; - unsigned long reg_con = our_chip->eint_con + bank->eint_offset; - unsigned long flags; - unsigned int mask; - unsigned int con; + unsigned long reg_con, flags; + unsigned int shift, mask, con; int ret; ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); @@ -174,10 +171,10 @@ static int exynos_irq_request_resources(struct irq_data *irqd) spin_lock_irqsave(&bank->slock, flags); - con = readl(bank->eint_base + reg_con); + con = readl(bank->pctl_base + reg_con); con &= ~(mask << shift); - con |= EXYNOS_EINT_FUNC << shift; - writel(con, bank->eint_base + reg_con); + con |= EXYNOS_PIN_FUNC_EINT << shift; + writel(con, bank->pctl_base + reg_con); spin_unlock_irqrestore(&bank->slock, flags); @@ -186,15 +183,10 @@ static int exynos_irq_request_resources(struct irq_data *irqd) static void exynos_irq_release_resources(struct irq_data *irqd) { - struct irq_chip *chip = irq_data_get_irq_chip(irqd); - struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); const struct samsung_pin_bank_type *bank_type = bank->type; - unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; - unsigned long reg_con = our_chip->eint_con + bank->eint_offset; - unsigned long flags; - unsigned int mask; - unsigned int con; + unsigned long reg_con, flags; + unsigned int shift, mask, con; reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; @@ -202,10 +194,10 @@ static void exynos_irq_release_resources(struct irq_data *irqd) spin_lock_irqsave(&bank->slock, flags); - con = readl(bank->eint_base + reg_con); + con = readl(bank->pctl_base + reg_con); con &= ~(mask << shift); - con |= FUNC_INPUT << shift; - writel(con, bank->eint_base + reg_con); + con |= EXYNOS_PIN_FUNC_INPUT << shift; + writel(con, bank->pctl_base + reg_con); spin_unlock_irqrestore(&bank->slock, flags); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index b90139715c8f..7639b926c5c1 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -32,7 +32,6 @@ #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 #define EXYNOS_SVC_OFFSET 0xB08 -#define EXYNOS_EINT_FUNC 0xF /* helpers to access interrupt service register */ #define EXYNOS_SVC_GROUP_SHIFT 3 diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index 49774851e84a..edf27264b603 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -151,7 +151,7 @@ static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, u32 val; /* Make sure that pin is configured as interrupt */ - reg = bank->pctl_base + bank->pctl_offset; + reg = d->virt_base + bank->pctl_offset; shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; @@ -184,7 +184,7 @@ static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) s3c24xx_eint_set_handler(data, type); /* Set up interrupt trigger */ - reg = bank->eint_base + EINT_REG(index); + reg = d->virt_base + EINT_REG(index); shift = EINT_OFFS(index); val = readl(reg); @@ -259,29 +259,32 @@ static void s3c2410_demux_eint0_3(struct irq_desc *desc) static void s3c2412_eint0_3_ack(struct irq_data *data) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned long bitval = 1UL << data->hwirq; - writel(bitval, bank->eint_base + EINTPEND_REG); + writel(bitval, d->virt_base + EINTPEND_REG); } static void s3c2412_eint0_3_mask(struct irq_data *data) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned long mask; - mask = readl(bank->eint_base + EINTMASK_REG); + mask = readl(d->virt_base + EINTMASK_REG); mask |= (1UL << data->hwirq); - writel(mask, bank->eint_base + EINTMASK_REG); + writel(mask, d->virt_base + EINTMASK_REG); } static void s3c2412_eint0_3_unmask(struct irq_data *data) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned long mask; - mask = readl(bank->eint_base + EINTMASK_REG); + mask = readl(d->virt_base + EINTMASK_REG); mask &= ~(1UL << data->hwirq); - writel(mask, bank->eint_base + EINTMASK_REG); + writel(mask, d->virt_base + EINTMASK_REG); } static struct irq_chip s3c2412_eint0_3_chip = { @@ -316,31 +319,34 @@ static void s3c2412_demux_eint0_3(struct irq_desc *desc) static void s3c24xx_eint_ack(struct irq_data *data) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned char index = bank->eint_offset + data->hwirq; - writel(1UL << index, bank->eint_base + EINTPEND_REG); + writel(1UL << index, d->virt_base + EINTPEND_REG); } static void s3c24xx_eint_mask(struct irq_data *data) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned char index = bank->eint_offset + data->hwirq; unsigned long mask; - mask = readl(bank->eint_base + EINTMASK_REG); + mask = readl(d->virt_base + EINTMASK_REG); mask |= (1UL << index); - writel(mask, bank->eint_base + EINTMASK_REG); + writel(mask, d->virt_base + EINTMASK_REG); } static void s3c24xx_eint_unmask(struct irq_data *data) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned char index = bank->eint_offset + data->hwirq; unsigned long mask; - mask = readl(bank->eint_base + EINTMASK_REG); + mask = readl(d->virt_base + EINTMASK_REG); mask &= ~(1UL << index); - writel(mask, bank->eint_base + EINTMASK_REG); + writel(mask, d->virt_base + EINTMASK_REG); } static struct irq_chip s3c24xx_eint_chip = { @@ -356,14 +362,13 @@ static inline void s3c24xx_demux_eint(struct irq_desc *desc, { struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); - struct irq_data *irqd = irq_desc_get_irq_data(desc); - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = data->drvdata; unsigned int pend, mask; chained_irq_enter(chip, desc); - pend = readl(bank->eint_base + EINTPEND_REG); - mask = readl(bank->eint_base + EINTMASK_REG); + pend = readl(d->virt_base + EINTPEND_REG); + mask = readl(d->virt_base + EINTMASK_REG); pend &= ~mask; pend &= range; diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index 4a88d7446e87..e63663b32907 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -280,7 +280,7 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, u32 val; /* Make sure that pin is configured as interrupt */ - reg = bank->pctl_base + bank->pctl_offset; + reg = d->virt_base + bank->pctl_offset; shift = pin; if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) { /* 4-bit bank type with 2 con regs */ @@ -308,8 +308,9 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; - void __iomem *reg = bank->eint_base + EINTMASK_REG(bank->eint_offset); + void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset); u32 val; val = readl(reg); @@ -333,8 +334,9 @@ static void s3c64xx_gpio_irq_mask(struct irq_data *irqd) static void s3c64xx_gpio_irq_ack(struct irq_data *irqd) { struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *d = bank->drvdata; unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; - void __iomem *reg = bank->eint_base + EINTPEND_REG(bank->eint_offset); + void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset); writel(1 << index, reg); } @@ -357,7 +359,7 @@ static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) s3c64xx_irq_set_handler(irqd, type); /* Set up interrupt trigger */ - reg = bank->eint_base + EINTCON_REG(bank->eint_offset); + reg = d->virt_base + EINTCON_REG(bank->eint_offset); shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */ @@ -409,8 +411,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc); - struct irq_data *irqd = irq_desc_get_irq_data(desc); - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); + struct samsung_pinctrl_drv_data *drvdata = data->drvdata; chained_irq_enter(chip, desc); @@ -420,7 +421,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc) unsigned int pin; unsigned int virq; - svc = readl(bank->eint_base + SERVICE_REG); + svc = readl(drvdata->virt_base + SERVICE_REG); group = SVC_GROUP(svc); pin = svc & SVC_NUM_MASK; @@ -515,15 +516,15 @@ static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask) { struct s3c64xx_eint0_domain_data *ddata = irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank *bank = ddata->bank; + struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; u32 val; - val = readl(bank->eint_base + EINT0MASK_REG); + val = readl(d->virt_base + EINT0MASK_REG); if (mask) val |= 1 << ddata->eints[irqd->hwirq]; else val &= ~(1 << ddata->eints[irqd->hwirq]); - writel(val, bank->eint_base + EINT0MASK_REG); + writel(val, d->virt_base + EINT0MASK_REG); } static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd) @@ -540,10 +541,10 @@ static void s3c64xx_eint0_irq_ack(struct irq_data *irqd) { struct s3c64xx_eint0_domain_data *ddata = irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank *bank = ddata->bank; + struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; writel(1 << ddata->eints[irqd->hwirq], - bank->eint_base + EINT0PEND_REG); + d->virt_base + EINT0PEND_REG); } static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) @@ -551,7 +552,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) struct s3c64xx_eint0_domain_data *ddata = irq_data_get_irq_chip_data(irqd); struct samsung_pin_bank *bank = ddata->bank; - struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata; + struct samsung_pinctrl_drv_data *d = bank->drvdata; void __iomem *reg; int trigger; u8 shift; @@ -566,7 +567,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type) s3c64xx_irq_set_handler(irqd, type); /* Set up interrupt trigger */ - reg = bank->eint_base + EINT0CON0_REG; + reg = d->virt_base + EINT0CON0_REG; shift = ddata->eints[irqd->hwirq]; if (shift >= EINT_MAX_PER_REG) { reg += 4; @@ -598,19 +599,14 @@ static struct irq_chip s3c64xx_eint0_irq_chip = { static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range) { struct irq_chip *chip = irq_desc_get_chip(desc); - struct irq_data *irqd = irq_desc_get_irq_data(desc); - struct s3c64xx_eint0_domain_data *ddata = - irq_data_get_irq_chip_data(irqd); - struct samsung_pin_bank *bank = ddata->bank; - struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc); - + struct samsung_pinctrl_drv_data *drvdata = data->drvdata; unsigned int pend, mask; chained_irq_enter(chip, desc); - pend = readl(bank->eint_base + EINT0PEND_REG); - mask = readl(bank->eint_base + EINT0MASK_REG); + pend = readl(drvdata->virt_base + EINT0PEND_REG); + mask = readl(drvdata->virt_base + EINT0MASK_REG); pend = pend & range & ~mask; pend &= range; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index f542642eed8d..e04f7fe0a65d 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -30,6 +30,8 @@ #include <linux/of_device.h> #include <linux/spinlock.h> +#include <dt-bindings/pinctrl/samsung.h> + #include "../core.h" #include "pinctrl-samsung.h" @@ -586,7 +588,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc, data = readl(reg); data &= ~(mask << shift); if (!input) - data |= FUNC_OUTPUT << shift; + data |= EXYNOS_PIN_FUNC_OUTPUT << shift; writel(data, reg); return 0; @@ -679,7 +681,7 @@ static int samsung_pinctrl_create_function(struct device *dev, npins = of_property_count_strings(func_np, "samsung,pins"); if (npins < 1) { - dev_err(dev, "invalid pin list in %s node", func_np->name); + dev_err(dev, "invalid pin list in %pOFn node", func_np); return -EINVAL; } @@ -696,8 +698,8 @@ static int samsung_pinctrl_create_function(struct device *dev, i, &gname); if (ret) { dev_err(dev, - "failed to read pin name %d from %s node\n", - i, func_np->name); + "failed to read pin name %d from %pOFn node\n", + i, func_np); return ret; } @@ -958,7 +960,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, struct samsung_pin_bank *bank; struct resource *res; void __iomem *virt_base[SAMSUNG_PINCTRL_NUM_RESOURCES]; - int i; + unsigned int i; id = of_alias_get_id(node, "pinctrl"); if (id < 0) { @@ -1013,6 +1015,12 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, bank->eint_base = virt_base[0]; bank->pctl_base = virt_base[bdata->pctl_res_idx]; } + /* + * Legacy platforms should provide only one resource with IO memory. + * Store it as virt_base because legacy driver needs to access it + * through samsung_pinctrl_drv_data. + */ + d->virt_base = virt_base[0]; for_each_child_of_node(node, np) { if (!of_find_property(np, "gpio-controller", NULL)) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 515a61035e54..9af07af6cad6 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -25,10 +25,6 @@ #include <linux/gpio.h> -/* pinmux function number for pin as gpio output line */ -#define FUNC_INPUT 0x0 -#define FUNC_OUTPUT 0x1 - /** * enum pincfg_type - possible pin configuration types supported. * @PINCFG_TYPE_FUNC: Function configuration. @@ -234,8 +230,8 @@ struct samsung_retention_data { */ struct samsung_pin_ctrl { const struct samsung_pin_bank_data *pin_banks; - u32 nr_banks; - int nr_ext_resources; + unsigned int nr_banks; + unsigned int nr_ext_resources; const struct samsung_retention_data *retention_data; int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); @@ -247,6 +243,10 @@ struct samsung_pin_ctrl { /** * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. * @node: global list node + * @virt_base: register base address of the controller; this will be equal + * to each bank samsung_pin_bank->pctl_base and used on legacy + * platforms (like S3C24XX or S3C64XX) which has to access the base + * through samsung_pinctrl_drv_data, not samsung_pin_bank). * @dev: device instance representing the controller. * @irq: interrpt number used by the controller to notify gpio interrupts. * @ctrl: pin controller instance managed by the driver. @@ -262,6 +262,7 @@ struct samsung_pin_ctrl { */ struct samsung_pinctrl_drv_data { struct list_head node; + void __iomem *virt_base; struct device *dev; int irq; @@ -274,7 +275,7 @@ struct samsung_pinctrl_drv_data { unsigned int nr_functions; struct samsung_pin_bank *pin_banks; - u32 nr_banks; + unsigned int nr_banks; unsigned int pin_base; unsigned int nr_pins; diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 24f76a05a5a9..5d5312eb7102 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796 depends on ARCH_R8A7796 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A77995 + def_bool y + depends on ARCH_R8A77995 + select PINCTRL_SH_PFC + config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 33d28eed9ba3..1d4f05a96bd4 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o +obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index e72391d5e57d..0c5e952461fd 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -551,6 +551,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7796_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A77995 + { + .compatible = "renesas,pfc-r8a77995", + .data = &r8a77995_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 4c5ffbd75be7..10bd35f8c894 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -2589,6 +2589,17 @@ static const unsigned int mmc_data8_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; +static const unsigned int mmc_data8_b_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), +}; +static const unsigned int mmc_data8_b_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, +}; static const unsigned int mmc_ctrl_pins[] = { /* CLK, CMD */ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), @@ -4420,7 +4431,7 @@ static const unsigned int vin2_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[341]; + struct sh_pfc_pin_group common[342]; struct sh_pfc_pin_group r8a779x[9]; } pinmux_groups = { .common = { @@ -4523,6 +4534,7 @@ static const struct { SH_PFC_PIN_GROUP(mmc_data1), SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_data8_b), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4955,6 +4967,7 @@ static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", "mmc_data8", + "mmc_data8_b", "mmc_ctrl", }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 1656295af2b0..8b35772cda98 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -61,7 +61,7 @@ #define GPSR1_24 F_(RD_WR_N, IP4_31_28) #define GPSR1_23 F_(RD_N, IP4_27_24) #define GPSR1_22 F_(BS_N, IP4_23_20) -#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) +#define GPSR1_21 F_(CS1_N, IP4_19_16) #define GPSR1_20 F_(CS0_N, IP4_15_12) #define GPSR1_19 F_(A19, IP4_11_8) #define GPSR1_18 F_(A18, IP4_7_4) @@ -168,8 +168,8 @@ #define GPSR5_0 F_(SCK0, IP11_27_24) /* GPSR6 */ -#define GPSR6_31 F_(USB3_OVC, IP18_7_4) -#define GPSR6_30 F_(USB3_PWEN, IP18_3_0) +#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4) +#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0) #define GPSR6_29 F_(USB30_OVC, IP17_31_28) #define GPSR6_28 F_(USB30_PWEN, IP17_27_24) #define GPSR6_27 F_(USB1_OVC, IP17_23_20) @@ -215,8 +215,8 @@ #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -247,7 +247,7 @@ #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -270,7 +270,6 @@ #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ @@ -285,24 +284,24 @@ #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ @@ -361,8 +360,8 @@ #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) -#define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) +#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) +#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ \ @@ -413,7 +412,7 @@ FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_3 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ -FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ @@ -469,7 +468,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) +#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1) #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) @@ -480,7 +479,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) -#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) +#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) @@ -497,7 +496,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) @@ -514,7 +512,7 @@ MOD_SEL0_28_27 MOD_SEL2_28_27 \ MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ MOD_SEL0_23 MOD_SEL1_23_22_21 \ -MOD_SEL0_22 MOD_SEL2_22 \ +MOD_SEL0_22 \ MOD_SEL0_21 MOD_SEL2_21 \ MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ @@ -833,7 +831,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), - PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), + PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), @@ -986,8 +984,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), - PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), - PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), @@ -1023,35 +1019,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), + PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), + PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), + PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), + PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), + PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1201,7 +1197,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), PINMUX_IPSR_GPSR(IP12_31_28, SCK2), - PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), @@ -1271,12 +1267,12 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), - PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1), PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), @@ -1392,7 +1388,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), - PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), + PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), @@ -1409,17 +1405,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), PINMUX_IPSR_GPSR(IP16_31_28, SCK1), PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), + PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), - PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), - PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), + PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0), PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), @@ -1460,10 +1456,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), - PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), @@ -1479,7 +1475,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), /* IPSR18 */ - PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN), + PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN), PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), @@ -1489,7 +1485,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), - PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC), + PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC), PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), @@ -1744,6 +1740,704 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 17), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 22), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 8), +}; +static const unsigned int msiof1_clk_a_mux[] = { + MSIOF1_SCK_A_MARK, +}; +static const unsigned int msiof1_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 9), +}; +static const unsigned int msiof1_sync_a_mux[] = { + MSIOF1_SYNC_A_MARK, +}; +static const unsigned int msiof1_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 5), +}; +static const unsigned int msiof1_ss1_a_mux[] = { + MSIOF1_SS1_A_MARK, +}; +static const unsigned int msiof1_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 6), +}; +static const unsigned int msiof1_ss2_a_mux[] = { + MSIOF1_SS2_A_MARK, +}; +static const unsigned int msiof1_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int msiof1_txd_a_mux[] = { + MSIOF1_TXD_A_MARK, +}; +static const unsigned int msiof1_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int msiof1_rxd_a_mux[] = { + MSIOF1_RXD_A_MARK, +}; +static const unsigned int msiof1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 9), +}; +static const unsigned int msiof1_clk_b_mux[] = { + MSIOF1_SCK_B_MARK, +}; +static const unsigned int msiof1_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int msiof1_sync_b_mux[] = { + MSIOF1_SYNC_B_MARK, +}; +static const unsigned int msiof1_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int msiof1_ss1_b_mux[] = { + MSIOF1_SS1_B_MARK, +}; +static const unsigned int msiof1_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int msiof1_ss2_b_mux[] = { + MSIOF1_SS2_B_MARK, +}; +static const unsigned int msiof1_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 8), +}; +static const unsigned int msiof1_txd_b_mux[] = { + MSIOF1_TXD_B_MARK, +}; +static const unsigned int msiof1_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int msiof1_rxd_b_mux[] = { + MSIOF1_RXD_B_MARK, +}; +static const unsigned int msiof1_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 17), +}; +static const unsigned int msiof1_clk_c_mux[] = { + MSIOF1_SCK_C_MARK, +}; +static const unsigned int msiof1_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int msiof1_sync_c_mux[] = { + MSIOF1_SYNC_C_MARK, +}; +static const unsigned int msiof1_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int msiof1_ss1_c_mux[] = { + MSIOF1_SS1_C_MARK, +}; +static const unsigned int msiof1_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 27), +}; +static const unsigned int msiof1_ss2_c_mux[] = { + MSIOF1_SS2_C_MARK, +}; +static const unsigned int msiof1_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int msiof1_txd_c_mux[] = { + MSIOF1_TXD_C_MARK, +}; +static const unsigned int msiof1_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int msiof1_rxd_c_mux[] = { + MSIOF1_RXD_C_MARK, +}; +static const unsigned int msiof1_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int msiof1_clk_d_mux[] = { + MSIOF1_SCK_D_MARK, +}; +static const unsigned int msiof1_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int msiof1_sync_d_mux[] = { + MSIOF1_SYNC_D_MARK, +}; +static const unsigned int msiof1_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int msiof1_ss1_d_mux[] = { + MSIOF1_SS1_D_MARK, +}; +static const unsigned int msiof1_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int msiof1_ss2_d_mux[] = { + MSIOF1_SS2_D_MARK, +}; +static const unsigned int msiof1_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int msiof1_txd_d_mux[] = { + MSIOF1_TXD_D_MARK, +}; +static const unsigned int msiof1_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int msiof1_rxd_d_mux[] = { + MSIOF1_RXD_D_MARK, +}; +static const unsigned int msiof1_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int msiof1_clk_e_mux[] = { + MSIOF1_SCK_E_MARK, +}; +static const unsigned int msiof1_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int msiof1_sync_e_mux[] = { + MSIOF1_SYNC_E_MARK, +}; +static const unsigned int msiof1_ss1_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 4), +}; +static const unsigned int msiof1_ss1_e_mux[] = { + MSIOF1_SS1_E_MARK, +}; +static const unsigned int msiof1_ss2_e_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int msiof1_ss2_e_mux[] = { + MSIOF1_SS2_E_MARK, +}; +static const unsigned int msiof1_txd_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 3), +}; +static const unsigned int msiof1_txd_e_mux[] = { + MSIOF1_TXD_E_MARK, +}; +static const unsigned int msiof1_rxd_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int msiof1_rxd_e_mux[] = { + MSIOF1_RXD_E_MARK, +}; +static const unsigned int msiof1_clk_f_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 23), +}; +static const unsigned int msiof1_clk_f_mux[] = { + MSIOF1_SCK_F_MARK, +}; +static const unsigned int msiof1_sync_f_pins[] = { + /* SYNC */ + RCAR_GP_PIN(5, 24), +}; +static const unsigned int msiof1_sync_f_mux[] = { + MSIOF1_SYNC_F_MARK, +}; +static const unsigned int msiof1_ss1_f_pins[] = { + /* SS1 */ + RCAR_GP_PIN(6, 1), +}; +static const unsigned int msiof1_ss1_f_mux[] = { + MSIOF1_SS1_F_MARK, +}; +static const unsigned int msiof1_ss2_f_pins[] = { + /* SS2 */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int msiof1_ss2_f_mux[] = { + MSIOF1_SS2_F_MARK, +}; +static const unsigned int msiof1_txd_f_pins[] = { + /* TXD */ + RCAR_GP_PIN(6, 0), +}; +static const unsigned int msiof1_txd_f_mux[] = { + MSIOF1_TXD_F_MARK, +}; +static const unsigned int msiof1_rxd_f_pins[] = { + /* RXD */ + RCAR_GP_PIN(5, 25), +}; +static const unsigned int msiof1_rxd_f_mux[] = { + MSIOF1_RXD_F_MARK, +}; +static const unsigned int msiof1_clk_g_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int msiof1_clk_g_mux[] = { + MSIOF1_SCK_G_MARK, +}; +static const unsigned int msiof1_sync_g_pins[] = { + /* SYNC */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int msiof1_sync_g_mux[] = { + MSIOF1_SYNC_G_MARK, +}; +static const unsigned int msiof1_ss1_g_pins[] = { + /* SS1 */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int msiof1_ss1_g_mux[] = { + MSIOF1_SS1_G_MARK, +}; +static const unsigned int msiof1_ss2_g_pins[] = { + /* SS2 */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int msiof1_ss2_g_mux[] = { + MSIOF1_SS2_G_MARK, +}; +static const unsigned int msiof1_txd_g_pins[] = { + /* TXD */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int msiof1_txd_g_mux[] = { + MSIOF1_TXD_G_MARK, +}; +static const unsigned int msiof1_rxd_g_pins[] = { + /* RXD */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int msiof1_rxd_g_mux[] = { + MSIOF1_RXD_G_MARK, +}; +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 9), +}; +static const unsigned int msiof2_clk_a_mux[] = { + MSIOF2_SCK_A_MARK, +}; +static const unsigned int msiof2_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int msiof2_sync_a_mux[] = { + MSIOF2_SYNC_A_MARK, +}; +static const unsigned int msiof2_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof2_ss1_a_mux[] = { + MSIOF2_SS1_A_MARK, +}; +static const unsigned int msiof2_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof2_ss2_a_mux[] = { + MSIOF2_SS2_A_MARK, +}; +static const unsigned int msiof2_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int msiof2_txd_a_mux[] = { + MSIOF2_TXD_A_MARK, +}; +static const unsigned int msiof2_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 10), +}; +static const unsigned int msiof2_rxd_a_mux[] = { + MSIOF2_RXD_A_MARK, +}; +static const unsigned int msiof2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int msiof2_clk_b_mux[] = { + MSIOF2_SCK_B_MARK, +}; +static const unsigned int msiof2_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int msiof2_sync_b_mux[] = { + MSIOF2_SYNC_B_MARK, +}; +static const unsigned int msiof2_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof2_ss1_b_mux[] = { + MSIOF2_SS1_B_MARK, +}; +static const unsigned int msiof2_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof2_ss2_b_mux[] = { + MSIOF2_SS2_B_MARK, +}; +static const unsigned int msiof2_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int msiof2_txd_b_mux[] = { + MSIOF2_TXD_B_MARK, +}; +static const unsigned int msiof2_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int msiof2_rxd_b_mux[] = { + MSIOF2_RXD_B_MARK, +}; +static const unsigned int msiof2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int msiof2_clk_c_mux[] = { + MSIOF2_SCK_C_MARK, +}; +static const unsigned int msiof2_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int msiof2_sync_c_mux[] = { + MSIOF2_SYNC_C_MARK, +}; +static const unsigned int msiof2_ss1_c_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int msiof2_ss1_c_mux[] = { + MSIOF2_SS1_C_MARK, +}; +static const unsigned int msiof2_ss2_c_pins[] = { + /* SS2 */ + RCAR_GP_PIN(2, 9), +}; +static const unsigned int msiof2_ss2_c_mux[] = { + MSIOF2_SS2_C_MARK, +}; +static const unsigned int msiof2_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int msiof2_txd_c_mux[] = { + MSIOF2_TXD_C_MARK, +}; +static const unsigned int msiof2_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int msiof2_rxd_c_mux[] = { + MSIOF2_RXD_C_MARK, +}; +static const unsigned int msiof2_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int msiof2_clk_d_mux[] = { + MSIOF2_SCK_D_MARK, +}; +static const unsigned int msiof2_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 9), +}; +static const unsigned int msiof2_sync_d_mux[] = { + MSIOF2_SYNC_D_MARK, +}; +static const unsigned int msiof2_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int msiof2_ss1_d_mux[] = { + MSIOF2_SS1_D_MARK, +}; +static const unsigned int msiof2_ss2_d_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int msiof2_ss2_d_mux[] = { + MSIOF2_SS2_D_MARK, +}; +static const unsigned int msiof2_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int msiof2_txd_d_mux[] = { + MSIOF2_TXD_D_MARK, +}; +static const unsigned int msiof2_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int msiof2_rxd_d_mux[] = { + MSIOF2_RXD_D_MARK, +}; +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int msiof3_clk_a_mux[] = { + MSIOF3_SCK_A_MARK, +}; +static const unsigned int msiof3_sync_a_pins[] = { + /* SYNC */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_sync_a_mux[] = { + MSIOF3_SYNC_A_MARK, +}; +static const unsigned int msiof3_ss1_a_pins[] = { + /* SS1 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int msiof3_ss1_a_mux[] = { + MSIOF3_SS1_A_MARK, +}; +static const unsigned int msiof3_ss2_a_pins[] = { + /* SS2 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int msiof3_ss2_a_mux[] = { + MSIOF3_SS2_A_MARK, +}; +static const unsigned int msiof3_txd_a_pins[] = { + /* TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_txd_a_mux[] = { + MSIOF3_TXD_A_MARK, +}; +static const unsigned int msiof3_rxd_a_pins[] = { + /* RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rxd_a_mux[] = { + MSIOF3_RXD_A_MARK, +}; +static const unsigned int msiof3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof3_clk_b_mux[] = { + MSIOF3_SCK_B_MARK, +}; +static const unsigned int msiof3_sync_b_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int msiof3_sync_b_mux[] = { + MSIOF3_SYNC_B_MARK, +}; +static const unsigned int msiof3_ss1_b_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int msiof3_ss1_b_mux[] = { + MSIOF3_SS1_B_MARK, +}; +static const unsigned int msiof3_ss2_b_pins[] = { + /* SS2 */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int msiof3_ss2_b_mux[] = { + MSIOF3_SS2_B_MARK, +}; +static const unsigned int msiof3_txd_b_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int msiof3_txd_b_mux[] = { + MSIOF3_TXD_B_MARK, +}; +static const unsigned int msiof3_rxd_b_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof3_rxd_b_mux[] = { + MSIOF3_RXD_B_MARK, +}; +static const unsigned int msiof3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 12), +}; +static const unsigned int msiof3_clk_c_mux[] = { + MSIOF3_SCK_C_MARK, +}; +static const unsigned int msiof3_sync_c_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int msiof3_sync_c_mux[] = { + MSIOF3_SYNC_C_MARK, +}; +static const unsigned int msiof3_txd_c_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int msiof3_txd_c_mux[] = { + MSIOF3_TXD_C_MARK, +}; +static const unsigned int msiof3_rxd_c_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 14), +}; +static const unsigned int msiof3_rxd_c_mux[] = { + MSIOF3_RXD_C_MARK, +}; +static const unsigned int msiof3_clk_d_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int msiof3_clk_d_mux[] = { + MSIOF3_SCK_D_MARK, +}; +static const unsigned int msiof3_sync_d_pins[] = { + /* SYNC */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int msiof3_sync_d_mux[] = { + MSIOF3_SYNC_D_MARK, +}; +static const unsigned int msiof3_ss1_d_pins[] = { + /* SS1 */ + RCAR_GP_PIN(1, 26), +}; +static const unsigned int msiof3_ss1_d_mux[] = { + MSIOF3_SS1_D_MARK, +}; +static const unsigned int msiof3_txd_d_pins[] = { + /* TXD */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int msiof3_txd_d_mux[] = { + MSIOF3_TXD_D_MARK, +}; +static const unsigned int msiof3_rxd_d_pins[] = { + /* RXD */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int msiof3_rxd_d_mux[] = { + MSIOF3_RXD_D_MARK, +}; +static const unsigned int msiof3_clk_e_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int msiof3_clk_e_mux[] = { + MSIOF3_SCK_E_MARK, +}; +static const unsigned int msiof3_sync_e_pins[] = { + /* SYNC */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int msiof3_sync_e_mux[] = { + MSIOF3_SYNC_E_MARK, +}; +static const unsigned int msiof3_ss1_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int msiof3_ss1_e_mux[] = { + MSIOF3_SS1_E_MARK, +}; +static const unsigned int msiof3_ss2_e_pins[] = { + /* SS1 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int msiof3_ss2_e_mux[] = { + MSIOF3_SS2_E_MARK, +}; +static const unsigned int msiof3_txd_e_pins[] = { + /* TXD */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof3_txd_e_mux[] = { + MSIOF3_TXD_E_MARK, +}; +static const unsigned int msiof3_rxd_e_pins[] = { + /* RXD */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof3_rxd_e_mux[] = { + MSIOF3_RXD_E_MARK, +}; + /* - PWM0 --------------------------------------------------------------------*/ static const unsigned int pwm0_pins[] = { /* PWM */ @@ -2056,6 +2750,39 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, USB0_OVC_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, USB1_OVC_MARK, +}; +/* - USB2 ------------------------------------------------------------------- */ +static const unsigned int usb2_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int usb2_mux[] = { + USB2_PWEN_MARK, USB2_OVC_MARK, +}; +/* - USB2_CH3 --------------------------------------------------------------- */ +static const unsigned int usb2_ch3_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +}; +static const unsigned int usb2_ch3_mux[] = { + USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), @@ -2075,6 +2802,105 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk_a), + SH_PFC_PIN_GROUP(msiof1_sync_a), + SH_PFC_PIN_GROUP(msiof1_ss1_a), + SH_PFC_PIN_GROUP(msiof1_ss2_a), + SH_PFC_PIN_GROUP(msiof1_txd_a), + SH_PFC_PIN_GROUP(msiof1_rxd_a), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_txd_b), + SH_PFC_PIN_GROUP(msiof1_rxd_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_ss1_c), + SH_PFC_PIN_GROUP(msiof1_ss2_c), + SH_PFC_PIN_GROUP(msiof1_txd_c), + SH_PFC_PIN_GROUP(msiof1_rxd_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_ss2_d), + SH_PFC_PIN_GROUP(msiof1_txd_d), + SH_PFC_PIN_GROUP(msiof1_rxd_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_ss1_e), + SH_PFC_PIN_GROUP(msiof1_ss2_e), + SH_PFC_PIN_GROUP(msiof1_txd_e), + SH_PFC_PIN_GROUP(msiof1_rxd_e), + SH_PFC_PIN_GROUP(msiof1_clk_f), + SH_PFC_PIN_GROUP(msiof1_sync_f), + SH_PFC_PIN_GROUP(msiof1_ss1_f), + SH_PFC_PIN_GROUP(msiof1_ss2_f), + SH_PFC_PIN_GROUP(msiof1_txd_f), + SH_PFC_PIN_GROUP(msiof1_rxd_f), + SH_PFC_PIN_GROUP(msiof1_clk_g), + SH_PFC_PIN_GROUP(msiof1_sync_g), + SH_PFC_PIN_GROUP(msiof1_ss1_g), + SH_PFC_PIN_GROUP(msiof1_ss2_g), + SH_PFC_PIN_GROUP(msiof1_txd_g), + SH_PFC_PIN_GROUP(msiof1_rxd_g), + SH_PFC_PIN_GROUP(msiof2_clk_a), + SH_PFC_PIN_GROUP(msiof2_sync_a), + SH_PFC_PIN_GROUP(msiof2_ss1_a), + SH_PFC_PIN_GROUP(msiof2_ss2_a), + SH_PFC_PIN_GROUP(msiof2_txd_a), + SH_PFC_PIN_GROUP(msiof2_rxd_a), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_txd_b), + SH_PFC_PIN_GROUP(msiof2_rxd_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_ss1_c), + SH_PFC_PIN_GROUP(msiof2_ss2_c), + SH_PFC_PIN_GROUP(msiof2_txd_c), + SH_PFC_PIN_GROUP(msiof2_rxd_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_txd_d), + SH_PFC_PIN_GROUP(msiof2_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_a), + SH_PFC_PIN_GROUP(msiof3_sync_a), + SH_PFC_PIN_GROUP(msiof3_ss1_a), + SH_PFC_PIN_GROUP(msiof3_ss2_a), + SH_PFC_PIN_GROUP(msiof3_txd_a), + SH_PFC_PIN_GROUP(msiof3_rxd_a), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_ss1_b), + SH_PFC_PIN_GROUP(msiof3_ss2_b), + SH_PFC_PIN_GROUP(msiof3_txd_b), + SH_PFC_PIN_GROUP(msiof3_rxd_b), + SH_PFC_PIN_GROUP(msiof3_clk_c), + SH_PFC_PIN_GROUP(msiof3_sync_c), + SH_PFC_PIN_GROUP(msiof3_txd_c), + SH_PFC_PIN_GROUP(msiof3_rxd_c), + SH_PFC_PIN_GROUP(msiof3_clk_d), + SH_PFC_PIN_GROUP(msiof3_sync_d), + SH_PFC_PIN_GROUP(msiof3_ss1_d), + SH_PFC_PIN_GROUP(msiof3_txd_d), + SH_PFC_PIN_GROUP(msiof3_rxd_d), + SH_PFC_PIN_GROUP(msiof3_clk_e), + SH_PFC_PIN_GROUP(msiof3_sync_e), + SH_PFC_PIN_GROUP(msiof3_ss1_e), + SH_PFC_PIN_GROUP(msiof3_ss2_e), + SH_PFC_PIN_GROUP(msiof3_txd_e), + SH_PFC_PIN_GROUP(msiof3_rxd_e), SH_PFC_PIN_GROUP(pwm0), SH_PFC_PIN_GROUP(pwm1_a), SH_PFC_PIN_GROUP(pwm1_b), @@ -2117,6 +2943,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(usb2_ch3), }; static const char * const avb_groups[] = { @@ -2143,6 +2973,117 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk_a", + "msiof1_sync_a", + "msiof1_ss1_a", + "msiof1_ss2_a", + "msiof1_txd_a", + "msiof1_rxd_a", + "msiof1_clk_b", + "msiof1_sync_b", + "msiof1_ss1_b", + "msiof1_ss2_b", + "msiof1_txd_b", + "msiof1_rxd_b", + "msiof1_clk_c", + "msiof1_sync_c", + "msiof1_ss1_c", + "msiof1_ss2_c", + "msiof1_txd_c", + "msiof1_rxd_c", + "msiof1_clk_d", + "msiof1_sync_d", + "msiof1_ss1_d", + "msiof1_ss2_d", + "msiof1_txd_d", + "msiof1_rxd_d", + "msiof1_clk_e", + "msiof1_sync_e", + "msiof1_ss1_e", + "msiof1_ss2_e", + "msiof1_txd_e", + "msiof1_rxd_e", + "msiof1_clk_f", + "msiof1_sync_f", + "msiof1_ss1_f", + "msiof1_ss2_f", + "msiof1_txd_f", + "msiof1_rxd_f", + "msiof1_clk_g", + "msiof1_sync_g", + "msiof1_ss1_g", + "msiof1_ss2_g", + "msiof1_txd_g", + "msiof1_rxd_g", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk_a", + "msiof2_sync_a", + "msiof2_ss1_a", + "msiof2_ss2_a", + "msiof2_txd_a", + "msiof2_rxd_a", + "msiof2_clk_b", + "msiof2_sync_b", + "msiof2_ss1_b", + "msiof2_ss2_b", + "msiof2_txd_b", + "msiof2_rxd_b", + "msiof2_clk_c", + "msiof2_sync_c", + "msiof2_ss1_c", + "msiof2_ss2_c", + "msiof2_txd_c", + "msiof2_rxd_c", + "msiof2_clk_d", + "msiof2_sync_d", + "msiof2_ss1_d", + "msiof2_ss2_d", + "msiof2_txd_d", + "msiof2_rxd_d", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", + "msiof3_clk_c", + "msiof3_sync_c", + "msiof3_txd_c", + "msiof3_rxd_c", + "msiof3_clk_d", + "msiof3_sync_d", + "msiof3_ss1_d", + "msiof3_txd_d", + "msiof3_rxd_d", + "msiof3_clk_e", + "msiof3_sync_e", + "msiof3_ss1_e", + "msiof3_ss2_e", + "msiof3_txd_e", + "msiof3_rxd_e", +}; + static const char * const pwm0_groups[] = { "pwm0", }; @@ -2227,9 +3168,29 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + +static const char * const usb2_groups[] = { + "usb2", +}; + +static const char * const usb2_ch3_groups[] = { + "usb2_ch3", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), SH_PFC_FUNCTION(pwm0), SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), @@ -2244,6 +3205,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(usb2_ch3), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -2601,7 +3566,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_27_24 IP7_23_20 IP7_19_16 - IP7_15_12 + /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 IP7_3_0 } @@ -2782,7 +3747,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL2_28_27 MOD_SEL2_26 MOD_SEL2_25_24_23 - MOD_SEL2_22 + /* RESERVED 22 */ + 0, 0, MOD_SEL2_21 MOD_SEL2_20 MOD_SEL2_19 @@ -3049,8 +4015,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */ - { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */ + { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */ + { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */ } }, { }, }; @@ -3177,7 +4143,7 @@ static const struct sh_pfc_bias_info bias_info[] = { { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ @@ -3280,8 +4246,8 @@ static const struct sh_pfc_bias_info bias_info[] = { { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */ + { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */ + { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 98bf5d0e078e..200e1f4f6db9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -67,7 +67,7 @@ #define GPSR1_24 F_(RD_WR_N, IP4_31_28) #define GPSR1_23 F_(RD_N, IP4_27_24) #define GPSR1_22 F_(BS_N, IP4_23_20) -#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) +#define GPSR1_21 F_(CS1_N, IP4_19_16) #define GPSR1_20 F_(CS0_N, IP4_15_12) #define GPSR1_19 F_(A19, IP4_11_8) #define GPSR1_18 F_(A18, IP4_7_4) @@ -221,8 +221,8 @@ #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -253,7 +253,7 @@ #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -278,7 +278,6 @@ #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -291,24 +290,24 @@ #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ @@ -319,14 +318,14 @@ #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -366,9 +365,9 @@ #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) -#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) -#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) +#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) +#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ \ @@ -419,7 +418,7 @@ FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_3 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ -FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ @@ -463,7 +462,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) -#define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1) #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) @@ -472,7 +470,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) -#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -488,7 +485,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) -#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) +#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) @@ -529,7 +526,7 @@ MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ MOD_SEL2_17 \ MOD_SEL0_16 MOD_SEL1_16 \ -MOD_SEL0_15 MOD_SEL1_15_14 \ + MOD_SEL1_15_14 \ MOD_SEL0_14_13 \ MOD_SEL1_13 \ MOD_SEL0_12 MOD_SEL1_12 \ @@ -541,7 +538,7 @@ MOD_SEL0_7_6 \ MOD_SEL0_5 MOD_SEL1_5 \ MOD_SEL0_4_3 MOD_SEL1_4 \ MOD_SEL1_3 \ -MOD_SEL0_2 MOD_SEL1_2 \ + MOD_SEL1_2 \ MOD_SEL1_1 \ MOD_SEL1_0 MOD_SEL2_0 @@ -645,7 +642,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), - PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4), + PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), /* IPSR1 */ PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), @@ -837,7 +834,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), - PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), + PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), @@ -990,8 +987,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), - PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), - PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), @@ -1173,7 +1168,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), - PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0), PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), @@ -1205,7 +1199,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), PINMUX_IPSR_GPSR(IP12_31_28, SCK2), - PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), @@ -1218,14 +1212,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), - PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1), + PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), - PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1), + PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), @@ -1393,7 +1387,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), - PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), + PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), @@ -1410,14 +1404,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), PINMUX_IPSR_GPSR(IP16_31_28, SCK1), PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), - PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), + PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), - PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), @@ -1461,10 +1455,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), - PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), + PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), @@ -1476,7 +1470,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), - PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1), + PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), /* IPSR18 */ @@ -1487,7 +1481,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), - PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0), PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), @@ -1498,7 +1491,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), - PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), @@ -3082,7 +3074,7 @@ static const unsigned int msiof3_ss2_e_pins[] = { RCAR_GP_PIN(2, 0), }; static const unsigned int msiof3_ss2_e_mux[] = { - MSIOF3_SS1_E_MARK, + MSIOF3_SS2_E_MARK, }; static const unsigned int msiof3_txd_e_pins[] = { /* TXD */ @@ -3796,6 +3788,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = { SSI_SCK9_B_MARK, SSI_WS9_B_MARK, }; +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, USB0_OVC_MARK, +}; +/* - USB1 ------------------------------------------------------------------- */ +static const unsigned int usb1_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int usb1_mux[] = { + USB1_PWEN_MARK, USB1_OVC_MARK, +}; + +/* - USB30 ------------------------------------------------------------------ */ +static const unsigned int usb30_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int usb30_mux[] = { + USB30_PWEN_MARK, USB30_OVC_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -4096,6 +4114,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi9_data_b), SH_PFC_PIN_GROUP(ssi9_ctrl_a), SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb30), }; static const char * const audio_clk_groups[] = { @@ -4526,6 +4547,18 @@ static const char * const ssi_groups[] = { "ssi9_ctrl_b", }; +static const char * const usb0_groups[] = { + "usb0", +}; + +static const char * const usb1_groups[] = { + "usb1", +}; + +static const char * const usb30_groups[] = { + "usb30", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), @@ -4570,6 +4603,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb30), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -4927,7 +4963,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_27_24 IP7_23_20 IP7_19_16 - IP7_15_12 + /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 IP7_3_0 } @@ -5060,7 +5096,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_19 MOD_SEL0_18_17 MOD_SEL0_16 - MOD_SEL0_15 + 0, 0, /* RESERVED 15 */ MOD_SEL0_14_13 MOD_SEL0_12 MOD_SEL0_11 @@ -5502,7 +5538,7 @@ static const struct sh_pfc_bias_info bias_info[] = { { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ + { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c new file mode 100644 index 000000000000..4f5ee1d7317d --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -0,0 +1,1812 @@ +/* + * R8A77995 processor support - PFC hardware block. + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +#include <linux/kernel.h> + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_9(0, fn, sfx), \ + PORT_GP_32(1, fn, sfx), \ + PORT_GP_32(2, fn, sfx), \ + PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_32(4, fn, sfx), \ + PORT_GP_21(5, fn, sfx), \ + PORT_GP_14(6, fn, sfx) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_8 F_(MLB_SIG, IP0_27_24) +#define GPSR0_7 F_(MLB_DAT, IP0_23_20) +#define GPSR0_6 F_(MLB_CLK, IP0_19_16) +#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12) +#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8) +#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4) +#define GPSR0_2 F_(IRQ0_A, IP0_3_0) +#define GPSR0_1 FM(USB0_OVC) +#define GPSR0_0 FM(USB0_PWEN) + +/* GPSR1 */ +#define GPSR1_31 F_(QPOLB, IP4_27_24) +#define GPSR1_30 F_(QPOLA, IP4_23_20) +#define GPSR1_29 F_(DU_CDE, IP4_19_16) +#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12) +#define GPSR1_27 F_(DU_DISP, IP4_11_8) +#define GPSR1_26 F_(DU_VSYNC, IP4_7_4) +#define GPSR1_25 F_(DU_HSYNC, IP4_3_0) +#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28) +#define GPSR1_23 F_(DU_DR7, IP3_27_24) +#define GPSR1_22 F_(DU_DR6, IP3_23_20) +#define GPSR1_21 F_(DU_DR5, IP3_19_16) +#define GPSR1_20 F_(DU_DR4, IP3_15_12) +#define GPSR1_19 F_(DU_DR3, IP3_11_8) +#define GPSR1_18 F_(DU_DR2, IP3_7_4) +#define GPSR1_17 F_(DU_DR1, IP3_3_0) +#define GPSR1_16 F_(DU_DR0, IP2_31_28) +#define GPSR1_15 F_(DU_DG7, IP2_27_24) +#define GPSR1_14 F_(DU_DG6, IP2_23_20) +#define GPSR1_13 F_(DU_DG5, IP2_19_16) +#define GPSR1_12 F_(DU_DG4, IP2_15_12) +#define GPSR1_11 F_(DU_DG3, IP2_11_8) +#define GPSR1_10 F_(DU_DG2, IP2_7_4) +#define GPSR1_9 F_(DU_DG1, IP2_3_0) +#define GPSR1_8 F_(DU_DG0, IP1_31_28) +#define GPSR1_7 F_(DU_DB7, IP1_27_24) +#define GPSR1_6 F_(DU_DB6, IP1_23_20) +#define GPSR1_5 F_(DU_DB5, IP1_19_16) +#define GPSR1_4 F_(DU_DB4, IP1_15_12) +#define GPSR1_3 F_(DU_DB3, IP1_11_8) +#define GPSR1_2 F_(DU_DB2, IP1_7_4) +#define GPSR1_1 F_(DU_DB1, IP1_3_0) +#define GPSR1_0 F_(DU_DB0, IP0_31_28) + +/* GPSR2 */ +#define GPSR2_31 F_(NFCE_N, IP8_19_16) +#define GPSR2_30 F_(NFCLE, IP8_15_12) +#define GPSR2_29 F_(NFALE, IP8_11_8) +#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4) +#define GPSR2_27 F_(VI4_FIELD, IP8_3_0) +#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28) +#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24) +#define GPSR2_24 F_(VI4_DATA23, IP7_23_20) +#define GPSR2_23 F_(VI4_DATA22, IP7_19_16) +#define GPSR2_22 F_(VI4_DATA21, IP7_15_12) +#define GPSR2_21 F_(VI4_DATA20, IP7_11_8) +#define GPSR2_20 F_(VI4_DATA19, IP7_7_4) +#define GPSR2_19 F_(VI4_DATA18, IP7_3_0) +#define GPSR2_18 F_(VI4_DATA17, IP6_31_28) +#define GPSR2_17 F_(VI4_DATA16, IP6_27_24) +#define GPSR2_16 F_(VI4_DATA15, IP6_23_20) +#define GPSR2_15 F_(VI4_DATA14, IP6_19_16) +#define GPSR2_14 F_(VI4_DATA13, IP6_15_12) +#define GPSR2_13 F_(VI4_DATA12, IP6_11_8) +#define GPSR2_12 F_(VI4_DATA11, IP6_7_4) +#define GPSR2_11 F_(VI4_DATA10, IP6_3_0) +#define GPSR2_10 F_(VI4_DATA9, IP5_31_28) +#define GPSR2_9 F_(VI4_DATA8, IP5_27_24) +#define GPSR2_8 F_(VI4_DATA7, IP5_23_20) +#define GPSR2_7 F_(VI4_DATA6, IP5_19_16) +#define GPSR2_6 F_(VI4_DATA5, IP5_15_12) +#define GPSR2_5 FM(VI4_DATA4) +#define GPSR2_4 F_(VI4_DATA3, IP5_11_8) +#define GPSR2_3 F_(VI4_DATA2, IP5_7_4) +#define GPSR2_2 F_(VI4_DATA1, IP5_3_0) +#define GPSR2_1 F_(VI4_DATA0, IP4_31_28) +#define GPSR2_0 FM(VI4_CLK) + +/* GPSR3 */ +#define GPSR3_9 F_(NFDATA7, IP9_31_28) +#define GPSR3_8 F_(NFDATA6, IP9_27_24) +#define GPSR3_7 F_(NFDATA5, IP9_23_20) +#define GPSR3_6 F_(NFDATA4, IP9_19_16) +#define GPSR3_5 F_(NFDATA3, IP9_15_12) +#define GPSR3_4 F_(NFDATA2, IP9_11_8) +#define GPSR3_3 F_(NFDATA1, IP9_7_4) +#define GPSR3_2 F_(NFDATA0, IP9_3_0) +#define GPSR3_1 F_(NFWE_N, IP8_31_28) +#define GPSR3_0 F_(NFRE_N, IP8_27_24) + +/* GPSR4 */ +#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24) +#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4) +#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0) +#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28) +#define GPSR4_27 FM(TX2) +#define GPSR4_26 FM(RX2) +#define GPSR4_25 F_(SCK2, IP12_11_8) +#define GPSR4_24 F_(TX1_A, IP12_7_4) +#define GPSR4_23 F_(RX1_A, IP12_3_0) +#define GPSR4_22 F_(SCK1_A, IP11_31_28) +#define GPSR4_21 F_(TX0_A, IP11_27_24) +#define GPSR4_20 F_(RX0_A, IP11_23_20) +#define GPSR4_19 F_(SCK0_A, IP11_19_16) +#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12) +#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8) +#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4) +#define GPSR4_15 FM(MSIOF0_RXD) +#define GPSR4_14 FM(MSIOF0_TXD) +#define GPSR4_13 FM(MSIOF0_SYNC) +#define GPSR4_12 FM(MSIOF0_SCK) +#define GPSR4_11 F_(SDA1, IP11_3_0) +#define GPSR4_10 F_(SCL1, IP10_31_28) +#define GPSR4_9 FM(SDA0) +#define GPSR4_8 FM(SCL0) +#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24) +#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20) +#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16) +#define GPSR4_4 F_(SSI_WS34, IP10_15_12) +#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8) +#define GPSR4_2 F_(SSI_SCK34, IP10_7_4) +#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0) +#define GPSR4_0 F_(NFRB_N, IP8_23_20) + +/* GPSR5 */ +#define GPSR5_20 FM(AVB0_LINK) +#define GPSR5_19 FM(AVB0_PHY_INT) +#define GPSR5_18 FM(AVB0_MAGIC) +#define GPSR5_17 FM(AVB0_MDC) +#define GPSR5_16 FM(AVB0_MDIO) +#define GPSR5_15 FM(AVB0_TXCREFCLK) +#define GPSR5_14 FM(AVB0_TD3) +#define GPSR5_13 FM(AVB0_TD2) +#define GPSR5_12 FM(AVB0_TD1) +#define GPSR5_11 FM(AVB0_TD0) +#define GPSR5_10 FM(AVB0_TXC) +#define GPSR5_9 FM(AVB0_TX_CTL) +#define GPSR5_8 FM(AVB0_RD3) +#define GPSR5_7 FM(AVB0_RD2) +#define GPSR5_6 FM(AVB0_RD1) +#define GPSR5_5 FM(AVB0_RD0) +#define GPSR5_4 FM(AVB0_RXC) +#define GPSR5_3 FM(AVB0_RX_CTL) +#define GPSR5_2 F_(CAN_CLK, IP12_23_20) +#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16) +#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12) + +/* GPSR6 */ +#define GPSR6_13 FM(RPC_INT_N) +#define GPSR6_12 FM(RPC_RESET_N) +#define GPSR6_11 FM(QSPI1_SSL) +#define GPSR6_10 FM(QSPI1_IO3) +#define GPSR6_9 FM(QSPI1_IO2) +#define GPSR6_8 FM(QSPI1_MISO_IO1) +#define GPSR6_7 FM(QSPI1_MOSI_IO0) +#define GPSR6_6 FM(QSPI1_SPCLK) +#define GPSR6_5 FM(QSPI0_SSL) +#define GPSR6_4 FM(QSPI0_IO3) +#define GPSR6_3 FM(QSPI0_IO2) +#define GPSR6_2 FM(QSPI0_MISO_IO1) +#define GPSR6_1 FM(QSPI0_MOSI_IO0) +#define GPSR6_0 FM(QSPI0_SPCLK) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ +\ + GPSR1_31 GPSR2_31 GPSR4_31 \ + GPSR1_30 GPSR2_30 GPSR4_30 \ + GPSR1_29 GPSR2_29 GPSR4_29 \ + GPSR1_28 GPSR2_28 GPSR4_28 \ + GPSR1_27 GPSR2_27 GPSR4_27 \ + GPSR1_26 GPSR2_26 GPSR4_26 \ + GPSR1_25 GPSR2_25 GPSR4_25 \ + GPSR1_24 GPSR2_24 GPSR4_24 \ + GPSR1_23 GPSR2_23 GPSR4_23 \ + GPSR1_22 GPSR2_22 GPSR4_22 \ + GPSR1_21 GPSR2_21 GPSR4_21 \ + GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \ + GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \ + GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \ + GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \ + GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \ + GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \ + GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \ + GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \ + GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \ + GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \ + GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \ + GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 + +#define PINMUX_IPSR \ +\ +FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ +FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ +FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ +FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ +FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ +FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ +FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ +FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ +\ +FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ +FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ +FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ +FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ +FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ +FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ +\ +FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ +FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ +FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ +FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ +FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ +\ +FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \ +FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \ +FM(IP12_11_8) IP12_11_8 \ +FM(IP12_15_12) IP12_15_12 \ +FM(IP12_19_16) IP12_19_16 \ +FM(IP12_23_20) IP12_23_20 \ +FM(IP12_27_24) IP12_27_24 \ +FM(IP12_31_28) IP12_31_28 \ + +/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) +#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) +#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) +#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) +#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) +#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) +#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3) +#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3) +#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3) +#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3) +#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) +#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) +#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) +#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1) +#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1) +#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1) +#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1) +#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1) +#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) +#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) +#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1) +#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1) + +#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1) +#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1) +#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1) +#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) +#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) +#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) + + +#define PINMUX_MOD_SELS \ +\ + MOD_SEL1_31 \ +MOD_SEL0_30 MOD_SEL1_30 \ +MOD_SEL0_29 MOD_SEL1_29 \ +MOD_SEL0_28 MOD_SEL1_28 \ +MOD_SEL0_27 MOD_SEL1_27 \ +MOD_SEL0_26 MOD_SEL1_26 \ +MOD_SEL0_25 \ +MOD_SEL0_24_23 \ +MOD_SEL0_22_21 \ +MOD_SEL0_20_19 \ +MOD_SEL0_18_17 \ +MOD_SEL0_15 \ +MOD_SEL0_14 \ +MOD_SEL0_13 \ +MOD_SEL0_12 \ +MOD_SEL0_11 \ +MOD_SEL0_10 \ +MOD_SEL0_5 \ +MOD_SEL0_4 \ +MOD_SEL0_3 \ +MOD_SEL0_2 \ +MOD_SEL0_1 \ +MOD_SEL0_0 + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \ + PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr) + +#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \ + PINMUX_DATA(fn##_MARK, FN_##msel) + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(USB0_OVC), + PINMUX_SINGLE(USB0_PWEN), + PINMUX_SINGLE(VI4_DATA4), + PINMUX_SINGLE(VI4_CLK), + PINMUX_SINGLE(TX2), + PINMUX_SINGLE(RX2), + PINMUX_SINGLE(AVB0_LINK), + PINMUX_SINGLE(AVB0_PHY_INT), + PINMUX_SINGLE(AVB0_MAGIC), + PINMUX_SINGLE(AVB0_MDC), + PINMUX_SINGLE(AVB0_MDIO), + PINMUX_SINGLE(AVB0_TXCREFCLK), + PINMUX_SINGLE(AVB0_TD3), + PINMUX_SINGLE(AVB0_TD2), + PINMUX_SINGLE(AVB0_TD1), + PINMUX_SINGLE(AVB0_TD0), + PINMUX_SINGLE(AVB0_TXC), + PINMUX_SINGLE(AVB0_TX_CTL), + PINMUX_SINGLE(AVB0_RD3), + PINMUX_SINGLE(AVB0_RD2), + PINMUX_SINGLE(AVB0_RD1), + PINMUX_SINGLE(AVB0_RD0), + PINMUX_SINGLE(AVB0_RXC), + PINMUX_SINGLE(AVB0_RX_CTL), + PINMUX_SINGLE(RPC_INT_N), + PINMUX_SINGLE(RPC_RESET_N), + PINMUX_SINGLE(QSPI1_SSL), + PINMUX_SINGLE(QSPI1_IO3), + PINMUX_SINGLE(QSPI1_IO2), + PINMUX_SINGLE(QSPI1_MISO_IO1), + PINMUX_SINGLE(QSPI1_MOSI_IO0), + PINMUX_SINGLE(QSPI1_SPCLK), + PINMUX_SINGLE(QSPI0_SSL), + PINMUX_SINGLE(QSPI0_IO3), + PINMUX_SINGLE(QSPI0_IO2), + PINMUX_SINGLE(QSPI0_MISO_IO1), + PINMUX_SINGLE(QSPI0_MOSI_IO0), + PINMUX_SINGLE(QSPI0_SPCLK), + + /* IPSR0 */ + PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), + PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN), + + PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), + PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU), + + PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), + PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), + + PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD), + PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0), + + PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK), + PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0), + + PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT), + PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1), + PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1), + + PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG), + PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2), + PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1), + + PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0), + PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0), + PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1), + PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1), + PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1), + + PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2), + PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2), + PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1), + + PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3), + PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3), + PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4), + PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4), + PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5), + PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5), + PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6), + PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6), + PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1), + + PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7), + PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7), + PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1), + + PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0), + PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8), + PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1), + PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9), + PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1), + + PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2), + PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10), + + PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3), + PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11), + PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0), + + PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4), + PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12), + PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1), + + PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5), + PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13), + PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1), + + PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6), + PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14), + PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1), + + PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), + PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), + PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), + + PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0), + PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16), + PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1), + PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17), + PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1), + + PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2), + PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18), + PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2), + + PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3), + PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19), + PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2), + + PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4), + PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20), + PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1), + + PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5), + PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21), + PINMUX_IPSR_GPSR(IP3_19_16, NMI), + + PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6), + PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22), + PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2), + + PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7), + PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23), + PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1), + + PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0), + PINMUX_IPSR_GPSR(IP3_31_28, QCLK), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC), + PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS), + PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0), + + PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC), + PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS), + PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0), + + PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP), + PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE), + PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2), + + PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE), + PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE), + PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1), + PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1), + + PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE), + PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE), + PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1), + + PINMUX_IPSR_GPSR(IP4_23_20, QPOLA), + PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1), + + PINMUX_IPSR_GPSR(IP4_27_24, QPOLB), + PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1), + + PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0), + PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1), + PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0), + + PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2), + PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0), + + PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3), + PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0), + + PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5), + PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6), + PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0), + + PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7), + PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0), + + PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8), + + PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9), + PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10), + PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11), + PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12), + PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0), + + PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13), + PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N), + + PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14), + PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1), + PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N), + + PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15), + PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1), + + PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), + PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), + + PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), + PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18), + PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0), + + PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19), + PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1), + PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15), + + PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20), + PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14), + + PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21), + PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0), + + PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13), + PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22), + PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0), + + PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12), + PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23), + PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), + + PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11), + + PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N), + PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1), + PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10), + + PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N), + PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9), + + /* IPSR8 */ + PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD), + PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB), + PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0), + PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK), + PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8), + + PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB), + PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N), + PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0), + + PINMUX_IPSR_GPSR(IP8_11_8, NFALE), + PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1), + PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1), + + PINMUX_IPSR_GPSR(IP8_15_12, NFCLE), + PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1), + + PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N), + PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1), + + PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N), + PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1), + + PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N), + PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD), + + PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N), + PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK), + + /* IPSR9 */ + PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0), + PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0), + + PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1), + PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1), + + PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2), + PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2), + + PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3), + PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3), + + PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4), + PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4), + + PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5), + PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5), + + PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6), + PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6), + + PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7), + PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7), + + /* IPSR10 */ + PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA), + PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1), + + PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34), + PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0), + + PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3), + PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0), + + PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34), + PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0), + + PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0), + PINMUX_IPSR_GPSR(IP10_19_16, HSCK0), + PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT), + PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1), + + PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0), + PINMUX_IPSR_GPSR(IP10_23_20, HTX0), + PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1), + + PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0), + PINMUX_IPSR_GPSR(IP10_27_24, HRX0), + PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1), + + PINMUX_IPSR_GPSR(IP10_31_28, SCL1), + PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N), + + /* IPSR11 */ + PINMUX_IPSR_GPSR(IP11_3_0, SDA1), + PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), + + PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), + PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), + + PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD), + PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1), + + PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD), + PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1), + + PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0), + PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC), + PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), + + PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0), + PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1), + PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), + + PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0), + PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2), + PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1), + + PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0), + PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B), + PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1), + + /* IPSR12 */ + PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N), + PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), + + PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), + + PINMUX_IPSR_GPSR(IP12_11_8, SCK2), + PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B), + + PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A), + PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0), + PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N), + + PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A), + PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0), + PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N), + + PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK), + PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1), + PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1), + + PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0), + PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX), + PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1), + + PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0), + PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX), + PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1), + + /* IPSR13 */ + PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0), + PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX), + PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A), + + PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0), + PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX), + PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), +}; +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; +static const unsigned int i2c1_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), +}; +static const unsigned int i2c1_mux[] = { + SCL1_MARK, SDA1_MARK, +}; +static const unsigned int i2c2_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), +}; +static const unsigned int i2c2_a_mux[] = { + SCL2_A_MARK, SDA2_A_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30), +}; +static const unsigned int i2c2_b_mux[] = { + SCL2_B_MARK, SDA2_B_MARK, +}; +static const unsigned int i2c3_a_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int i2c3_a_mux[] = { + SCL3_A_MARK, SDA3_A_MARK, +}; +static const unsigned int i2c3_b_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), +}; +static const unsigned int i2c3_b_mux[] = { + SCL3_B_MARK, SDA3_B_MARK, +}; + +/* - MMC ------------------------------------------------------------------- */ +static const unsigned int mmc_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, + MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, + MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), +}; +static const unsigned int scif0_data_a_mux[] = { + RX0_A_MARK, TX0_A_MARK, +}; +static const unsigned int scif0_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int scif0_clk_a_mux[] = { + SCK0_A_MARK, +}; +static const unsigned int scif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28), +}; +static const unsigned int scif0_data_b_mux[] = { + RX0_B_MARK, TX0_B_MARK, +}; +static const unsigned int scif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int scif0_clk_b_mux[] = { + SCK0_B_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_TANS_MARK, CTS0_N_MARK, +}; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int scif1_clk_a_mux[] = { + SCK1_A_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; +static const unsigned int scif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 25), +}; +static const unsigned int scif1_clk_b_mux[] = { + SCK1_B_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; + +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), +}; +static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(4, 25), +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00), +}; +static const unsigned int scif3_data_a_mux[] = { + RX3_A_MARK, TX3_A_MARK, +}; +static const unsigned int scif3_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 30), +}; +static const unsigned int scif3_clk_a_mux[] = { + SCK3_A_MARK, +}; +static const unsigned int scif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31), +}; +static const unsigned int scif3_data_b_mux[] = { + RX3_B_MARK, TX3_B_MARK, +}; +static const unsigned int scif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 29), +}; +static const unsigned int scif3_clk_b_mux[] = { + SCK3_B_MARK, +}; +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +}; +static const unsigned int scif4_data_a_mux[] = { + RX4_A_MARK, TX4_A_MARK, +}; +static const unsigned int scif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int scif4_clk_a_mux[] = { + SCK4_A_MARK, +}; +static const unsigned int scif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), +}; +static const unsigned int scif4_data_b_mux[] = { + RX4_B_MARK, TX4_B_MARK, +}; +static const unsigned int scif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 15), +}; +static const unsigned int scif4_clk_b_mux[] = { + SCK4_B_MARK, +}; +/* - SCIF5 ------------------------------------------------------------------ */ +static const unsigned int scif5_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), +}; +static const unsigned int scif5_data_a_mux[] = { + RX5_A_MARK, TX5_A_MARK, +}; +static const unsigned int scif5_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int scif5_clk_a_mux[] = { + SCK5_A_MARK, +}; +static const unsigned int scif5_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif5_data_b_mux[] = { + RX5_B_MARK, TX5_B_MARK, +}; +static const unsigned int scif5_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif5_clk_b_mux[] = { + SCK5_B_MARK, +}; +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3_a), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(scif0_data_a), + SH_PFC_PIN_GROUP(scif0_clk_a), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_clk_b), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk_a), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif3_data_a), + SH_PFC_PIN_GROUP(scif3_clk_a), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif4_data_a), + SH_PFC_PIN_GROUP(scif4_clk_a), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_clk_b), + SH_PFC_PIN_GROUP(scif5_data_a), + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), + SH_PFC_PIN_GROUP(scif_clk), +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", +}; + +static const char * const i2c3_groups[] = { + "i2c3_a", + "i2c3_b", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", +}; + +static const char * const scif0_groups[] = { + "scif0_data_a", + "scif0_clk_a", + "scif0_data_b", + "scif0_clk_b", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_clk_a", + "scif1_data_b", + "scif1_clk_b", + "scif1_ctrl", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", +}; + +static const char * const scif3_groups[] = { + "scif3_data_a", + "scif3_clk_a", + "scif3_data_b", + "scif3_clk_b", +}; + +static const char * const scif4_groups[] = { + "scif4_data_a", + "scif4_clk_a", + "scif4_data_b", + "scif4_clk_b", +}; + +static const char * const scif5_groups[] = { + "scif5_data_a", + "scif5_clk_a", + "scif5_data_b", + "scif5_clk_b", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scif_clk), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + GP_1_31_FN, GPSR1_31, + GP_1_30_FN, GPSR1_30, + GP_1_29_FN, GPSR1_29, + GP_1_28_FN, GPSR1_28, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, } + }, + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + GP_2_31_FN, GPSR2_31, + GP_2_30_FN, GPSR2_30, + GP_2_29_FN, GPSR2_29, + GP_2_28_FN, GPSR2_28, + GP_2_27_FN, GPSR2_27, + GP_2_26_FN, GPSR2_26, + GP_2_25_FN, GPSR2_25, + GP_2_24_FN, GPSR2_24, + GP_2_23_FN, GPSR2_23, + GP_2_22_FN, GPSR2_22, + GP_2_21_FN, GPSR2_21, + GP_2_20_FN, GPSR2_20, + GP_2_19_FN, GPSR2_19, + GP_2_18_FN, GPSR2_18, + GP_2_17_FN, GPSR2_17, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, } + }, + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, } + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + GP_4_31_FN, GPSR4_31, + GP_4_30_FN, GPSR4_30, + GP_4_29_FN, GPSR4_29, + GP_4_28_FN, GPSR4_28, + GP_4_27_FN, GPSR4_27, + GP_4_26_FN, GPSR4_26, + GP_4_25_FN, GPSR4_25, + GP_4_24_FN, GPSR4_24, + GP_4_23_FN, GPSR4_23, + GP_4_22_FN, GPSR4_22, + GP_4_21_FN, GPSR4_21, + GP_4_20_FN, GPSR4_20, + GP_4_19_FN, GPSR4_19, + GP_4_18_FN, GPSR4_18, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, } + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, } + }, + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + IP0_31_28 + IP0_27_24 + IP0_23_20 + IP0_19_16 + IP0_15_12 + IP0_11_8 + IP0_7_4 + IP0_3_0 } + }, + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + IP1_31_28 + IP1_27_24 + IP1_23_20 + IP1_19_16 + IP1_15_12 + IP1_11_8 + IP1_7_4 + IP1_3_0 } + }, + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + IP2_31_28 + IP2_27_24 + IP2_23_20 + IP2_19_16 + IP2_15_12 + IP2_11_8 + IP2_7_4 + IP2_3_0 } + }, + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + IP3_31_28 + IP3_27_24 + IP3_23_20 + IP3_19_16 + IP3_15_12 + IP3_11_8 + IP3_7_4 + IP3_3_0 } + }, + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + IP4_31_28 + IP4_27_24 + IP4_23_20 + IP4_19_16 + IP4_15_12 + IP4_11_8 + IP4_7_4 + IP4_3_0 } + }, + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + IP5_31_28 + IP5_27_24 + IP5_23_20 + IP5_19_16 + IP5_15_12 + IP5_11_8 + IP5_7_4 + IP5_3_0 } + }, + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + IP6_31_28 + IP6_27_24 + IP6_23_20 + IP6_19_16 + IP6_15_12 + IP6_11_8 + IP6_7_4 + IP6_3_0 } + }, + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + IP7_31_28 + IP7_27_24 + IP7_23_20 + IP7_19_16 + IP7_15_12 + IP7_11_8 + IP7_7_4 + IP7_3_0 } + }, + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + IP8_31_28 + IP8_27_24 + IP8_23_20 + IP8_19_16 + IP8_15_12 + IP8_11_8 + IP8_7_4 + IP8_3_0 } + }, + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + IP9_31_28 + IP9_27_24 + IP9_23_20 + IP9_19_16 + IP9_15_12 + IP9_11_8 + IP9_7_4 + IP9_3_0 } + }, + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + IP10_31_28 + IP10_27_24 + IP10_23_20 + IP10_19_16 + IP10_15_12 + IP10_11_8 + IP10_7_4 + IP10_3_0 } + }, + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + IP11_31_28 + IP11_27_24 + IP11_23_20 + IP11_19_16 + IP11_15_12 + IP11_11_8 + IP11_7_4 + IP11_3_0 } + }, + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + IP12_31_28 + IP12_27_24 + IP12_23_20 + IP12_19_16 + IP12_15_12 + IP12_11_8 + IP12_7_4 + IP12_3_0 } + }, + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IP13_7_4 + IP13_3_0 } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, + 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { + /* RESERVED 31 */ + 0, 0, + MOD_SEL0_30 + MOD_SEL0_29 + MOD_SEL0_28 + MOD_SEL0_27 + MOD_SEL0_26 + MOD_SEL0_25 + MOD_SEL0_24_23 + MOD_SEL0_22_21 + MOD_SEL0_20_19 + MOD_SEL0_18_17 + /* RESERVED 16 */ + 0, 0, + MOD_SEL0_15 + MOD_SEL0_14 + MOD_SEL0_13 + MOD_SEL0_12 + MOD_SEL0_11 + MOD_SEL0_10 + /* RESERVED 9, 8, 7, 6 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL0_5 + MOD_SEL0_4 + MOD_SEL0_3 + MOD_SEL0_2 + MOD_SEL0_1 + MOD_SEL0_0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 1, 1, 1, 1, 1, 1, 2, 4, 4, + 4, 4, 4, 4) { + MOD_SEL1_31 + MOD_SEL1_30 + MOD_SEL1_29 + MOD_SEL1_28 + MOD_SEL1_27 + MOD_SEL1_26 + /* RESERVED 25, 24 */ + 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 11, 10, 9, 8 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 7, 6, 5, 4 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 3, 2, 1, 0 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { }, +}; + +static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = 0xe6060380; + + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9)) + bit = 29 - (pin - RCAR_GP_PIN(3, 0)); + + return bit; +} + +static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { + .pin_to_pocctrl = r8a77995_pin_to_pocctrl, +}; + +const struct sh_pfc_soc_info r8a77995_pinmux_info = { + .name = "r8a77995_pfc", + .ops = &r8a77995_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index a70157f0acf4..5c9d79981e6d 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -290,7 +290,7 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, if (*num_maps) return 0; - dev_err(dev, "no mapping found in node %s\n", np->full_name); + dev_err(dev, "no mapping found in node %pOF\n", np); ret = -EINVAL; done: @@ -742,13 +742,16 @@ static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); const unsigned int *pins; unsigned int num_pins; - unsigned int i; + unsigned int i, ret; pins = pmx->pfc->info->groups[group].pins; num_pins = pmx->pfc->info->groups[group].nr_pins; - for (i = 0; i < num_pins; ++i) - sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); + for (i = 0; i < num_pins; ++i) { + ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } return 0; } diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 4376397123de..8688b405e081 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -271,6 +271,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; +extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; @@ -389,9 +390,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) -#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ PORT_GP_CFG_9(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) +#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) + +#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ + PORT_GP_CFG_10(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) @@ -422,11 +427,19 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) -#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ PORT_GP_CFG_18(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) +#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) + +#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ + PORT_GP_CFG_20(bank, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) +#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) + +#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ + PORT_GP_CFG_21(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 1efa315a7dbe..4db9323251e3 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -549,7 +549,7 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = { PINCTRL_PIN(163, "jtag_trstn"), }; -struct atlas7_pad_config atlas7_ioc_pad_confs[] = { +static struct atlas7_pad_config atlas7_ioc_pad_confs[] = { /* The Configuration of IOC_RTC Pads */ PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0), PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0), @@ -1002,7 +1002,7 @@ static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, }; /* definition of pin group table */ -struct atlas7_pin_group altas7_pin_groups[] = { +static struct atlas7_pin_group altas7_pin_groups[] = { GROUP("gnss_gpio_grp", gnss_gpio_pins), GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins), GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), @@ -4764,7 +4764,7 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = { &vi_vip1_high8bit_grp_mux), }; -struct atlas7_pinctrl_data atlas7_ioc_data = { +static struct atlas7_pinctrl_data atlas7_ioc_data = { .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads, .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads), .grps = (struct atlas7_pin_group *)altas7_pin_groups, @@ -5261,7 +5261,7 @@ static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops atlas7_pinmux_ops = { +static const struct pinmux_ops atlas7_pinmux_ops = { .get_functions_count = atlas7_pmx_get_funcs_count, .get_function_name = atlas7_pmx_get_func_name, .get_function_groups = atlas7_pmx_get_func_groups, @@ -6078,12 +6078,15 @@ static int atlas7_gpio_probe(struct platform_device *pdev) bank = &a7gc->banks[idx]; /* Set ctrl registers' base of this bank */ bank->base = ATLAS7_GPIO_BASE(a7gc, idx); + bank->gpio_offset = idx * NGPIO_OF_BANK; /* Get interrupt number from DTS */ ret = of_irq_get(np, idx); - if (ret == -EPROBE_DEFER) { + if (ret <= 0) { dev_err(&pdev->dev, "Unable to find IRQ number. ret=%d\n", ret); + if (!ret) + ret = -ENXIO; goto failed; } bank->irq = ret; diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 0df72be60704..d3ef05973901 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -133,7 +133,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops sirfsoc_pctrl_ops = { +static const struct pinctrl_ops sirfsoc_pctrl_ops = { .get_groups_count = sirfsoc_get_groups_count, .get_group_name = sirfsoc_get_group_name, .get_group_pins = sirfsoc_get_group_pins, @@ -229,7 +229,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, return 0; } -static struct pinmux_ops sirfsoc_pinmux_ops = { +static const struct pinmux_ops sirfsoc_pinmux_ops = { .set_mux = sirfsoc_pinmux_set_mux, .get_functions_count = sirfsoc_pinmux_get_funcs_count, .get_function_name = sirfsoc_pinmux_get_func_name, @@ -810,7 +810,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) sgpio->chip.gc.set = sirfsoc_gpio_set_value; sgpio->chip.gc.base = 0; sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; - sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); + sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np); sgpio->chip.gc.of_node = np; sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; sgpio->chip.gc.of_gpio_n_cells = 2; @@ -819,8 +819,8 @@ static int sirfsoc_gpio_probe(struct device_node *np) err = gpiochip_add_data(&sgpio->chip.gc, sgpio); if (err) { - dev_err(&pdev->dev, "%s: error in probe function with status %d\n", - np->full_name, err); + dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n", + np, err); goto out; } diff --git a/drivers/pinctrl/sprd/Kconfig b/drivers/pinctrl/sprd/Kconfig new file mode 100644 index 000000000000..6f4a7f9ac6fd --- /dev/null +++ b/drivers/pinctrl/sprd/Kconfig @@ -0,0 +1,17 @@ +# +# Spreadtrum pin control drivers +# + +config PINCTRL_SPRD + bool "Spreadtrum pinctrl driver" + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINMUX_FUNCTIONS + help + Say Y here to enable Spreadtrum pinctrl driver + +config PINCTRL_SPRD_SC9860 + bool "Spreadtrum SC9860 pinctrl driver" + help + Say Y here to enable Spreadtrum SC9860 pinctrl driver diff --git a/drivers/pinctrl/sprd/Makefile b/drivers/pinctrl/sprd/Makefile new file mode 100644 index 000000000000..b6caa8cbc6dd --- /dev/null +++ b/drivers/pinctrl/sprd/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PINCTRL_SPRD) += pinctrl-sprd.o +obj-$(CONFIG_PINCTRL_SPRD_SC9860) += pinctrl-sprd-sc9860.o diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c new file mode 100644 index 000000000000..3cdad8bc8f93 --- /dev/null +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c @@ -0,0 +1,972 @@ +/* + * Spreadtrum pin controller driver + * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "pinctrl-sprd.h" + +enum sprd_sc9860_pins { + /* pin global control register 0 */ + SC9860_VIO28_0_IRTE = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 11, 1, 0), + SC9860_VIO_SD2_IRTE = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 10, 1, 0), + SC9860_VIO_SD0_IRTE = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 9, 1, 0), + SC9860_VIO_SIM2_IRTE = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 8, 1, 0), + SC9860_VIO_SIM1_IRTE = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 7, 1, 0), + SC9860_VIO_SIM0_IRTE = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 6, 1, 0), + SC9860_VIO28_0_MS = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 5, 1, 0), + SC9860_VIO_SD2_MS = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 4, 1, 0), + SC9860_VIO_SD0_MS = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 3, 1, 0), + SC9860_VIO_SIM2_MS = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 2, 1, 0), + SC9860_VIO_SIM1_MS = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 1, 1, 0), + SC9860_VIO_SIM0_MS = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 0, 1, 0), + + /* pin global control register 2 */ + SC9860_SPSPI_PIN_IN_SEL = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 31, 1, 2), + SC9860_UART1_USB30_PHY_SEL = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 30, 1, 2), + SC9860_USB30_PHY_DM_OE = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 29, 1, 2), + SC9860_USB30_PHY_DP_OE = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 28, 1, 2), + SC9860_UART5_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 25, 3, 2), + SC9860_ORP_URXD_PIN_IN_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 24, 1, 2), + SC9860_SIM2_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 23, 1, 2), + SC9860_SIM1_SYS_SEL = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 22, 1, 2), + SC9860_SIM0_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 21, 1, 2), + SC9860_CLK26MHZ_BUF_OUT_SEL = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 20, 1, 2), + SC9860_UART4_SYS_SEL = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 16, 3, 2), + SC9860_UART3_SYS_SEL = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 13, 3, 2), + SC9860_UART2_SYS_SEL = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 10, 3, 2), + SC9860_UART1_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 7, 3, 2), + SC9860_UART0_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 4, 3, 2), + SC9860_UART24_LOOP_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 3, 1, 2), + SC9860_UART23_LOOP_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 2, 1, 2), + SC9860_UART14_LOOP_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 1, 1, 2), + SC9860_UART13_LOOP_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 0, 1, 2), + + /* pin global control register 3 */ + SC9860_IIS3_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 18, 4, 3), + SC9860_IIS2_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 14, 4, 3), + SC9860_IIS1_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 10, 4, 3), + SC9860_IIS0_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 6, 4, 3), + SC9860_IIS23_LOOP_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 5, 1, 3), + SC9860_IIS13_LOOP_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 4, 1, 3), + SC9860_IIS12_LOOP_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 3, 1, 3), + SC9860_IIS03_LOOP_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 2, 1, 3), + SC9860_IIS02_LOOP_SEL = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 1, 1, 3), + SC9860_IIS01_LOOP_SEL = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 0, 1, 3), + + /* pin global control register 4 */ + SC9860_IIS6_SYS_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 27, 4, 4), + SC9860_IIS5_SYS_SEL = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 23, 4, 4), + SC9860_IIS4_SYS_SEL = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 19, 4, 4), + SC9860_I2C_INF6_SYS_SEL = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 8, 2, 4), + SC9860_I2C_INF4_SYS_SEL = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 6, 2, 4), + SC9860_I2C_INF2_SYS_SEL = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 4, 2, 4), + SC9860_I2C_INF1_SYS_SEL = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 2, 2, 4), + SC9860_I2C_INF0_SYS_SEL = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 0, 2, 4), + + /* pin global control register 5 */ + SC9860_GPIO_INF7_SYS_SEL = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 27, 1, 5), + SC9860_GPIO_INF6_SYS_SEL = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 26, 1, 5), + SC9860_GPIO_INF5_SYS_SEL = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 25, 1, 5), + SC9860_GPIO_INF4_SYS_SEL = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 24, 1, 5), + SC9860_GPIO_INF3_SYS_SEL = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 23, 1, 5), + SC9860_GPIO_INF2_SYS_SEL = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 22, 1, 5), + SC9860_GPIO_INF1_SYS_SEL = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 21, 1, 5), + SC9860_GPIO_INF0_SYS_SEL = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 20, 1, 5), + SC9860_WDRST_OUT_SEL = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 16, 3, 5), + SC9860_ADI_SYNC_PIN_OUT_SEL = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 14, 1, 5), + SC9860_CMRST_SEL = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 13, 1, 5), + SC9860_CMPD_SEL = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 12, 1, 5), + SC9860_TEST_DBG_MODE11 = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 11, 1, 5), + SC9860_TEST_DBG_MODE10 = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 10, 1, 5), + SC9860_TEST_DBG_MODE9 = SPRD_PIN_INFO(63, GLOBAL_CTRL_PIN, 9, 1, 5), + SC9860_TEST_DBG_MODE8 = SPRD_PIN_INFO(64, GLOBAL_CTRL_PIN, 8, 1, 5), + SC9860_TEST_DBG_MODE7 = SPRD_PIN_INFO(65, GLOBAL_CTRL_PIN, 7, 1, 5), + SC9860_TEST_DBG_MODE6 = SPRD_PIN_INFO(66, GLOBAL_CTRL_PIN, 6, 1, 5), + SC9860_TEST_DBG_MODE5 = SPRD_PIN_INFO(67, GLOBAL_CTRL_PIN, 5, 1, 5), + SC9860_TEST_DBG_MODE4 = SPRD_PIN_INFO(68, GLOBAL_CTRL_PIN, 4, 1, 5), + SC9860_TEST_DBG_MODE3 = SPRD_PIN_INFO(69, GLOBAL_CTRL_PIN, 3, 1, 5), + SC9860_TEST_DBG_MODE2 = SPRD_PIN_INFO(70, GLOBAL_CTRL_PIN, 2, 1, 5), + SC9860_TEST_DBG_MODE1 = SPRD_PIN_INFO(71, GLOBAL_CTRL_PIN, 1, 1, 5), + SC9860_TEST_DBG_MODE0 = SPRD_PIN_INFO(72, GLOBAL_CTRL_PIN, 0, 1, 5), + + /* pin global control register 6 */ + SC9860_SP_EIC_DPAD3_SEL = SPRD_PIN_INFO(73, GLOBAL_CTRL_PIN, 24, 8, 6), + SC9860_SP_EIC_DPAD2_SEL = SPRD_PIN_INFO(74, GLOBAL_CTRL_PIN, 16, 8, 6), + SC9860_SP_EIC_DPAD1_SEL = SPRD_PIN_INFO(75, GLOBAL_CTRL_PIN, 8, 8, 6), + SC9860_SP_EIC_DPAD0_SEL = SPRD_PIN_INFO(76, GLOBAL_CTRL_PIN, 0, 8, 6), + + /* pin global control register 7 */ + SC9860_SP_EIC_DPAD7_SEL = SPRD_PIN_INFO(77, GLOBAL_CTRL_PIN, 24, 8, 7), + SC9860_SP_EIC_DPAD6_SEL = SPRD_PIN_INFO(78, GLOBAL_CTRL_PIN, 16, 8, 7), + SC9860_SP_EIC_DPAD5_SEL = SPRD_PIN_INFO(79, GLOBAL_CTRL_PIN, 8, 8, 7), + SC9860_SP_EIC_DPAD4_SEL = SPRD_PIN_INFO(80, GLOBAL_CTRL_PIN, 0, 8, 7), + + /* common pin registers definitions */ + SC9860_RFCTL20 = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL21 = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL30 = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL31 = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL32 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL33 = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL34 = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL35 = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL36 = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL37 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL22 = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL23 = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL24 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL25 = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL26 = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL27 = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL28 = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL29 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0), + SC9860_SCL2 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0), + SC9860_SDA2 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0), + SC9860_MTCK_ARM = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0), + SC9860_MTMS_ARM = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0), + SC9860_XTL_EN0 = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0), + SC9860_PTEST = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0), + SC9860_AUD_DAD1 = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0), + SC9860_AUD_ADD0 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0), + SC9860_AUD_ADSYNC = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0), + SC9860_AUD_SCLK = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0), + SC9860_CHIP_SLEEP = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0), + SC9860_CLK_32K = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0), + SC9860_DCDC_ARM_EN = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0), + SC9860_EXT_RST_B = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0), + SC9860_ADI_D = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0), + SC9860_ADI_SCLK = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0), + SC9860_XTL_EN1 = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0), + SC9860_ANA_INT = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0), + SC9860_AUD_DAD0 = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0), + SC9860_AUD_DASYNC = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0), + SC9860_LCM_RSTN = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0), + SC9860_DSI_TE = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0), + SC9860_PWMA = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0), + SC9860_EXTINT0 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0), + SC9860_EXTINT1 = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0), + SC9860_SDA1 = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0), + SC9860_SCL1 = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0), + SC9860_SIMCLK2 = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0), + SC9860_SIMDA2 = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0), + SC9860_SIMRST2 = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0), + SC9860_SIMCLK1 = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0), + SC9860_SIMDA1 = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0), + SC9860_SIMRST1 = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0), + SC9860_SIMCLK0 = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0), + SC9860_SIMDA0 = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0), + SC9860_SIMRST0 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0), + SC9860_SD2_CMD = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0), + SC9860_SD2_D0 = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0), + SC9860_SD2_D1 = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0), + SC9860_SD2_CLK = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0), + SC9860_SD2_D2 = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0), + SC9860_SD2_D3 = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0), + SC9860_SD0_D3 = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0), + SC9860_SD0_D2 = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0), + SC9860_SD0_CMD = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0), + SC9860_SD0_D0 = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0), + SC9860_SD0_D1 = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0), + SC9860_SD0_CLK = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_CMD_reserved = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_CMD = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D6 = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D7 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_CLK = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D5 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D4 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_DS = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D3_reserved = SPRD_PIN_INFO(229, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D3 = SPRD_PIN_INFO(231, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_RST = SPRD_PIN_INFO(233, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D1 = SPRD_PIN_INFO(235, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D2 = SPRD_PIN_INFO(237, COMMON_PIN, 0, 0, 0), + SC9860_EMMC_D0 = SPRD_PIN_INFO(239, COMMON_PIN, 0, 0, 0), + SC9860_IIS0DI = SPRD_PIN_INFO(241, COMMON_PIN, 0, 0, 0), + SC9860_IIS0DO = SPRD_PIN_INFO(243, COMMON_PIN, 0, 0, 0), + SC9860_IIS0CLK = SPRD_PIN_INFO(245, COMMON_PIN, 0, 0, 0), + SC9860_IIS0LRCK = SPRD_PIN_INFO(247, COMMON_PIN, 0, 0, 0), + SC9860_SD1_CLK = SPRD_PIN_INFO(249, COMMON_PIN, 0, 0, 0), + SC9860_SD1_CMD = SPRD_PIN_INFO(251, COMMON_PIN, 0, 0, 0), + SC9860_SD1_D0 = SPRD_PIN_INFO(253, COMMON_PIN, 0, 0, 0), + SC9860_SD1_D1 = SPRD_PIN_INFO(255, COMMON_PIN, 0, 0, 0), + SC9860_SD1_D2 = SPRD_PIN_INFO(257, COMMON_PIN, 0, 0, 0), + SC9860_SD1_D3 = SPRD_PIN_INFO(259, COMMON_PIN, 0, 0, 0), + SC9860_CLK_AUX0 = SPRD_PIN_INFO(261, COMMON_PIN, 0, 0, 0), + SC9860_WIFI_COEXIST = SPRD_PIN_INFO(263, COMMON_PIN, 0, 0, 0), + SC9860_BEIDOU_COEXIST = SPRD_PIN_INFO(265, COMMON_PIN, 0, 0, 0), + SC9860_U3TXD = SPRD_PIN_INFO(267, COMMON_PIN, 0, 0, 0), + SC9860_U3RXD = SPRD_PIN_INFO(269, COMMON_PIN, 0, 0, 0), + SC9860_U3CTS = SPRD_PIN_INFO(271, COMMON_PIN, 0, 0, 0), + SC9860_U3RTS = SPRD_PIN_INFO(273, COMMON_PIN, 0, 0, 0), + SC9860_U0TXD = SPRD_PIN_INFO(275, COMMON_PIN, 0, 0, 0), + SC9860_U0RXD = SPRD_PIN_INFO(277, COMMON_PIN, 0, 0, 0), + SC9860_U0CTS = SPRD_PIN_INFO(279, COMMON_PIN, 0, 0, 0), + SC9860_U0RTS = SPRD_PIN_INFO(281, COMMON_PIN, 0, 0, 0), + SC9860_IIS1DI = SPRD_PIN_INFO(283, COMMON_PIN, 0, 0, 0), + SC9860_IIS1DO = SPRD_PIN_INFO(285, COMMON_PIN, 0, 0, 0), + SC9860_IIS1CLK = SPRD_PIN_INFO(287, COMMON_PIN, 0, 0, 0), + SC9860_IIS1LRCK = SPRD_PIN_INFO(289, COMMON_PIN, 0, 0, 0), + SC9860_SPI0_CSN = SPRD_PIN_INFO(291, COMMON_PIN, 0, 0, 0), + SC9860_SPI0_DO = SPRD_PIN_INFO(293, COMMON_PIN, 0, 0, 0), + SC9860_SPI0_DI = SPRD_PIN_INFO(295, COMMON_PIN, 0, 0, 0), + SC9860_SPI0_CLK = SPRD_PIN_INFO(297, COMMON_PIN, 0, 0, 0), + SC9860_U2TXD = SPRD_PIN_INFO(299, COMMON_PIN, 0, 0, 0), + SC9860_U2RXD = SPRD_PIN_INFO(301, COMMON_PIN, 0, 0, 0), + SC9860_U4TXD = SPRD_PIN_INFO(303, COMMON_PIN, 0, 0, 0), + SC9860_U4RXD = SPRD_PIN_INFO(305, COMMON_PIN, 0, 0, 0), + SC9860_CMMCLK1 = SPRD_PIN_INFO(307, COMMON_PIN, 0, 0, 0), + SC9860_CMRST1 = SPRD_PIN_INFO(309, COMMON_PIN, 0, 0, 0), + SC9860_CMMCLK0 = SPRD_PIN_INFO(311, COMMON_PIN, 0, 0, 0), + SC9860_CMRST0 = SPRD_PIN_INFO(313, COMMON_PIN, 0, 0, 0), + SC9860_CMPD0 = SPRD_PIN_INFO(315, COMMON_PIN, 0, 0, 0), + SC9860_CMPD1 = SPRD_PIN_INFO(317, COMMON_PIN, 0, 0, 0), + SC9860_SCL0 = SPRD_PIN_INFO(319, COMMON_PIN, 0, 0, 0), + SC9860_SDA0 = SPRD_PIN_INFO(321, COMMON_PIN, 0, 0, 0), + SC9860_SDA6 = SPRD_PIN_INFO(323, COMMON_PIN, 0, 0, 0), + SC9860_SCL6 = SPRD_PIN_INFO(325, COMMON_PIN, 0, 0, 0), + SC9860_U1TXD = SPRD_PIN_INFO(327, COMMON_PIN, 0, 0, 0), + SC9860_U1RXD = SPRD_PIN_INFO(329, COMMON_PIN, 0, 0, 0), + SC9860_KEYOUT0 = SPRD_PIN_INFO(331, COMMON_PIN, 0, 0, 0), + SC9860_KEYOUT1 = SPRD_PIN_INFO(333, COMMON_PIN, 0, 0, 0), + SC9860_KEYOUT2 = SPRD_PIN_INFO(335, COMMON_PIN, 0, 0, 0), + SC9860_KEYIN0 = SPRD_PIN_INFO(337, COMMON_PIN, 0, 0, 0), + SC9860_KEYIN1 = SPRD_PIN_INFO(339, COMMON_PIN, 0, 0, 0), + SC9860_KEYIN2 = SPRD_PIN_INFO(341, COMMON_PIN, 0, 0, 0), + SC9860_IIS3DI = SPRD_PIN_INFO(343, COMMON_PIN, 0, 0, 0), + SC9860_IIS3DO = SPRD_PIN_INFO(345, COMMON_PIN, 0, 0, 0), + SC9860_IIS3CLK = SPRD_PIN_INFO(347, COMMON_PIN, 0, 0, 0), + SC9860_IIS3LRCK = SPRD_PIN_INFO(349, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL0 = SPRD_PIN_INFO(351, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL1 = SPRD_PIN_INFO(353, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL10 = SPRD_PIN_INFO(355, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL11 = SPRD_PIN_INFO(357, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL12 = SPRD_PIN_INFO(359, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL13 = SPRD_PIN_INFO(361, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL14 = SPRD_PIN_INFO(363, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL15 = SPRD_PIN_INFO(365, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL16 = SPRD_PIN_INFO(367, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL17 = SPRD_PIN_INFO(369, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL18 = SPRD_PIN_INFO(371, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL19 = SPRD_PIN_INFO(373, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL2 = SPRD_PIN_INFO(375, COMMON_PIN, 0, 0, 0), + SC9860_EXTINT5 = SPRD_PIN_INFO(377, COMMON_PIN, 0, 0, 0), + SC9860_EXTINT6 = SPRD_PIN_INFO(379, COMMON_PIN, 0, 0, 0), + SC9860_EXTINT7 = SPRD_PIN_INFO(381, COMMON_PIN, 0, 0, 0), + SC9860_GPIO30 = SPRD_PIN_INFO(383, COMMON_PIN, 0, 0, 0), + SC9860_GPIO31 = SPRD_PIN_INFO(385, COMMON_PIN, 0, 0, 0), + SC9860_GPIO32 = SPRD_PIN_INFO(387, COMMON_PIN, 0, 0, 0), + SC9860_GPIO33 = SPRD_PIN_INFO(389, COMMON_PIN, 0, 0, 0), + SC9860_GPIO34 = SPRD_PIN_INFO(391, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL3 = SPRD_PIN_INFO(393, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL4 = SPRD_PIN_INFO(395, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL5 = SPRD_PIN_INFO(397, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL6 = SPRD_PIN_INFO(399, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL7 = SPRD_PIN_INFO(401, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL8 = SPRD_PIN_INFO(403, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL9 = SPRD_PIN_INFO(405, COMMON_PIN, 0, 0, 0), + SC9860_RFFE0_SCK0 = SPRD_PIN_INFO(407, COMMON_PIN, 0, 0, 0), + SC9860_GPIO38 = SPRD_PIN_INFO(409, COMMON_PIN, 0, 0, 0), + SC9860_RFFE0_SDA0 = SPRD_PIN_INFO(411, COMMON_PIN, 0, 0, 0), + SC9860_GPIO39 = SPRD_PIN_INFO(413, COMMON_PIN, 0, 0, 0), + SC9860_RFFE1_SCK0 = SPRD_PIN_INFO(415, COMMON_PIN, 0, 0, 0), + SC9860_GPIO181 = SPRD_PIN_INFO(417, COMMON_PIN, 0, 0, 0), + SC9860_RFFE1_SDA0 = SPRD_PIN_INFO(419, COMMON_PIN, 0, 0, 0), + SC9860_GPIO182 = SPRD_PIN_INFO(421, COMMON_PIN, 0, 0, 0), + SC9860_RF_LVDS0_ADC_ON = SPRD_PIN_INFO(423, COMMON_PIN, 0, 0, 0), + SC9860_RF_LVDS0_DAC_ON = SPRD_PIN_INFO(425, COMMON_PIN, 0, 0, 0), + SC9860_RFSCK0 = SPRD_PIN_INFO(427, COMMON_PIN, 0, 0, 0), + SC9860_RFSDA0 = SPRD_PIN_INFO(429, COMMON_PIN, 0, 0, 0), + SC9860_RFSEN0 = SPRD_PIN_INFO(431, COMMON_PIN, 0, 0, 0), + SC9860_RF_LVDS1_ADC_ON = SPRD_PIN_INFO(433, COMMON_PIN, 0, 0, 0), + SC9860_RF_LVDS1_DAC_ON = SPRD_PIN_INFO(435, COMMON_PIN, 0, 0, 0), + SC9860_RFSCK1 = SPRD_PIN_INFO(437, COMMON_PIN, 0, 0, 0), + SC9860_RFSDA1 = SPRD_PIN_INFO(439, COMMON_PIN, 0, 0, 0), + SC9860_RFSEN1 = SPRD_PIN_INFO(441, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL38 = SPRD_PIN_INFO(443, COMMON_PIN, 0, 0, 0), + SC9860_RFCTL39 = SPRD_PIN_INFO(445, COMMON_PIN, 0, 0, 0), + + /* MSIC pin registers definitions */ + SC9860_RFCTL20_MISC = SPRD_PIN_INFO(82, MISC_PIN, 0, 0, 0), + SC9860_RFCTL21_MISC = SPRD_PIN_INFO(84, MISC_PIN, 0, 0, 0), + SC9860_RFCTL30_MISC = SPRD_PIN_INFO(86, MISC_PIN, 0, 0, 0), + SC9860_RFCTL31_MISC = SPRD_PIN_INFO(88, MISC_PIN, 0, 0, 0), + SC9860_RFCTL32_MISC = SPRD_PIN_INFO(90, MISC_PIN, 0, 0, 0), + SC9860_RFCTL33_MISC = SPRD_PIN_INFO(92, MISC_PIN, 0, 0, 0), + SC9860_RFCTL34_MISC = SPRD_PIN_INFO(94, MISC_PIN, 0, 0, 0), + SC9860_RFCTL35_MISC = SPRD_PIN_INFO(96, MISC_PIN, 0, 0, 0), + SC9860_RFCTL36_MISC = SPRD_PIN_INFO(98, MISC_PIN, 0, 0, 0), + SC9860_RFCTL37_MISC = SPRD_PIN_INFO(100, MISC_PIN, 0, 0, 0), + SC9860_RFCTL22_MISC = SPRD_PIN_INFO(102, MISC_PIN, 0, 0, 0), + SC9860_RFCTL23_MISC = SPRD_PIN_INFO(104, MISC_PIN, 0, 0, 0), + SC9860_RFCTL24_MISC = SPRD_PIN_INFO(106, MISC_PIN, 0, 0, 0), + SC9860_RFCTL25_MISC = SPRD_PIN_INFO(108, MISC_PIN, 0, 0, 0), + SC9860_RFCTL26_MISC = SPRD_PIN_INFO(110, MISC_PIN, 0, 0, 0), + SC9860_RFCTL27_MISC = SPRD_PIN_INFO(112, MISC_PIN, 0, 0, 0), + SC9860_RFCTL28_MISC = SPRD_PIN_INFO(114, MISC_PIN, 0, 0, 0), + SC9860_RFCTL29_MISC = SPRD_PIN_INFO(116, MISC_PIN, 0, 0, 0), + SC9860_SCL2_MISC = SPRD_PIN_INFO(118, MISC_PIN, 0, 0, 0), + SC9860_SDA2_MISC = SPRD_PIN_INFO(120, MISC_PIN, 0, 0, 0), + SC9860_MTCK_ARM_MISC = SPRD_PIN_INFO(122, MISC_PIN, 0, 0, 0), + SC9860_MTMS_ARM_MISC = SPRD_PIN_INFO(124, MISC_PIN, 0, 0, 0), + SC9860_XTL_EN0_MISC = SPRD_PIN_INFO(126, MISC_PIN, 0, 0, 0), + SC9860_PTEST_MISC = SPRD_PIN_INFO(128, MISC_PIN, 0, 0, 0), + SC9860_AUD_DAD1_MISC = SPRD_PIN_INFO(130, MISC_PIN, 0, 0, 0), + SC9860_AUD_ADD0_MISC = SPRD_PIN_INFO(132, MISC_PIN, 0, 0, 0), + SC9860_AUD_ADSYNC_MISC = SPRD_PIN_INFO(134, MISC_PIN, 0, 0, 0), + SC9860_AUD_SCLK_MISC = SPRD_PIN_INFO(136, MISC_PIN, 0, 0, 0), + SC9860_CHIP_SLEEP_MISC = SPRD_PIN_INFO(138, MISC_PIN, 0, 0, 0), + SC9860_CLK_32K_MISC = SPRD_PIN_INFO(140, MISC_PIN, 0, 0, 0), + SC9860_DCDC_ARM_EN_MISC = SPRD_PIN_INFO(142, MISC_PIN, 0, 0, 0), + SC9860_EXT_RST_B_MISC = SPRD_PIN_INFO(144, MISC_PIN, 0, 0, 0), + SC9860_ADI_D_MISC = SPRD_PIN_INFO(146, MISC_PIN, 0, 0, 0), + SC9860_ADI_SCLK_MISC = SPRD_PIN_INFO(148, MISC_PIN, 0, 0, 0), + SC9860_XTL_EN1_MISC = SPRD_PIN_INFO(150, MISC_PIN, 0, 0, 0), + SC9860_ANA_INT_MISC = SPRD_PIN_INFO(152, MISC_PIN, 0, 0, 0), + SC9860_AUD_DAD0_MISC = SPRD_PIN_INFO(154, MISC_PIN, 0, 0, 0), + SC9860_AUD_DASYNC_MISC = SPRD_PIN_INFO(156, MISC_PIN, 0, 0, 0), + SC9860_LCM_RSTN_MISC = SPRD_PIN_INFO(158, MISC_PIN, 0, 0, 0), + SC9860_DSI_TE_MISC = SPRD_PIN_INFO(160, MISC_PIN, 0, 0, 0), + SC9860_PWMA_MISC = SPRD_PIN_INFO(162, MISC_PIN, 0, 0, 0), + SC9860_EXTINT0_MISC = SPRD_PIN_INFO(164, MISC_PIN, 0, 0, 0), + SC9860_EXTINT1_MISC = SPRD_PIN_INFO(166, MISC_PIN, 0, 0, 0), + SC9860_SDA1_MISC = SPRD_PIN_INFO(168, MISC_PIN, 0, 0, 0), + SC9860_SCL1_MISC = SPRD_PIN_INFO(170, MISC_PIN, 0, 0, 0), + SC9860_SIMCLK2_MISC = SPRD_PIN_INFO(172, MISC_PIN, 0, 0, 0), + SC9860_SIMDA2_MISC = SPRD_PIN_INFO(174, MISC_PIN, 0, 0, 0), + SC9860_SIMRST2_MISC = SPRD_PIN_INFO(176, MISC_PIN, 0, 0, 0), + SC9860_SIMCLK1_MISC = SPRD_PIN_INFO(178, MISC_PIN, 0, 0, 0), + SC9860_SIMDA1_MISC = SPRD_PIN_INFO(180, MISC_PIN, 0, 0, 0), + SC9860_SIMRST1_MISC = SPRD_PIN_INFO(182, MISC_PIN, 0, 0, 0), + SC9860_SIMCLK0_MISC = SPRD_PIN_INFO(184, MISC_PIN, 0, 0, 0), + SC9860_SIMDA0_MISC = SPRD_PIN_INFO(186, MISC_PIN, 0, 0, 0), + SC9860_SIMRST0_MISC = SPRD_PIN_INFO(188, MISC_PIN, 0, 0, 0), + SC9860_SD2_CMD_MISC = SPRD_PIN_INFO(190, MISC_PIN, 0, 0, 0), + SC9860_SD2_D0_MISC = SPRD_PIN_INFO(192, MISC_PIN, 0, 0, 0), + SC9860_SD2_D1_MISC = SPRD_PIN_INFO(194, MISC_PIN, 0, 0, 0), + SC9860_SD2_CLK_MISC = SPRD_PIN_INFO(196, MISC_PIN, 0, 0, 0), + SC9860_SD2_D2_MISC = SPRD_PIN_INFO(198, MISC_PIN, 0, 0, 0), + SC9860_SD2_D3_MISC = SPRD_PIN_INFO(200, MISC_PIN, 0, 0, 0), + SC9860_SD0_D3_MISC = SPRD_PIN_INFO(202, MISC_PIN, 0, 0, 0), + SC9860_SD0_D2_MISC = SPRD_PIN_INFO(204, MISC_PIN, 0, 0, 0), + SC9860_SD0_CMD_MISC = SPRD_PIN_INFO(206, MISC_PIN, 0, 0, 0), + SC9860_SD0_D0_MISC = SPRD_PIN_INFO(208, MISC_PIN, 0, 0, 0), + SC9860_SD0_D1_MISC = SPRD_PIN_INFO(210, MISC_PIN, 0, 0, 0), + SC9860_SD0_CLK_MISC = SPRD_PIN_INFO(212, MISC_PIN, 0, 0, 0), + SC9860_EMMC_CMD_reserved_MISC = SPRD_PIN_INFO(214, MISC_PIN, 0, 0, 0), + SC9860_EMMC_CMD_MISC = SPRD_PIN_INFO(216, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D6_MISC = SPRD_PIN_INFO(218, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D7_MISC = SPRD_PIN_INFO(220, MISC_PIN, 0, 0, 0), + SC9860_EMMC_CLK_MISC = SPRD_PIN_INFO(222, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D5_MISC = SPRD_PIN_INFO(224, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D4_MISC = SPRD_PIN_INFO(226, MISC_PIN, 0, 0, 0), + SC9860_EMMC_DS_MISC = SPRD_PIN_INFO(228, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D3_reserved_MISC = SPRD_PIN_INFO(230, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D3_MISC = SPRD_PIN_INFO(232, MISC_PIN, 0, 0, 0), + SC9860_EMMC_RST_MISC = SPRD_PIN_INFO(234, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D1_MISC = SPRD_PIN_INFO(236, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D2_MISC = SPRD_PIN_INFO(238, MISC_PIN, 0, 0, 0), + SC9860_EMMC_D0_MISC = SPRD_PIN_INFO(240, MISC_PIN, 0, 0, 0), + SC9860_IIS0DI_MISC = SPRD_PIN_INFO(242, MISC_PIN, 0, 0, 0), + SC9860_IIS0DO_MISC = SPRD_PIN_INFO(244, MISC_PIN, 0, 0, 0), + SC9860_IIS0CLK_MISC = SPRD_PIN_INFO(246, MISC_PIN, 0, 0, 0), + SC9860_IIS0LRCK_MISC = SPRD_PIN_INFO(248, MISC_PIN, 0, 0, 0), + SC9860_SD1_CLK_MISC = SPRD_PIN_INFO(250, MISC_PIN, 0, 0, 0), + SC9860_SD1_CMD_MISC = SPRD_PIN_INFO(252, MISC_PIN, 0, 0, 0), + SC9860_SD1_D0_MISC = SPRD_PIN_INFO(254, MISC_PIN, 0, 0, 0), + SC9860_SD1_D1_MISC = SPRD_PIN_INFO(256, MISC_PIN, 0, 0, 0), + SC9860_SD1_D2_MISC = SPRD_PIN_INFO(258, MISC_PIN, 0, 0, 0), + SC9860_SD1_D3_MISC = SPRD_PIN_INFO(260, MISC_PIN, 0, 0, 0), + SC9860_CLK_AUX0_MISC = SPRD_PIN_INFO(262, MISC_PIN, 0, 0, 0), + SC9860_WIFI_COEXIST_MISC = SPRD_PIN_INFO(264, MISC_PIN, 0, 0, 0), + SC9860_BEIDOU_COEXIST_MISC = SPRD_PIN_INFO(266, MISC_PIN, 0, 0, 0), + SC9860_U3TXD_MISC = SPRD_PIN_INFO(268, MISC_PIN, 0, 0, 0), + SC9860_U3RXD_MISC = SPRD_PIN_INFO(270, MISC_PIN, 0, 0, 0), + SC9860_U3CTS_MISC = SPRD_PIN_INFO(272, MISC_PIN, 0, 0, 0), + SC9860_U3RTS_MISC = SPRD_PIN_INFO(274, MISC_PIN, 0, 0, 0), + SC9860_U0TXD_MISC = SPRD_PIN_INFO(276, MISC_PIN, 0, 0, 0), + SC9860_U0RXD_MISC = SPRD_PIN_INFO(278, MISC_PIN, 0, 0, 0), + SC9860_U0CTS_MISC = SPRD_PIN_INFO(280, MISC_PIN, 0, 0, 0), + SC9860_U0RTS_MISC = SPRD_PIN_INFO(282, MISC_PIN, 0, 0, 0), + SC9860_IIS1DI_MISC = SPRD_PIN_INFO(284, MISC_PIN, 0, 0, 0), + SC9860_IIS1DO_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0), + SC9860_IIS1CLK_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0), + SC9860_IIS1LRCK_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0), + SC9860_SPI0_CSN_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0), + SC9860_SPI0_DO_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0), + SC9860_SPI0_DI_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0), + SC9860_SPI0_CLK_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0), + SC9860_U2TXD_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0), + SC9860_U2RXD_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0), + SC9860_U4TXD_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0), + SC9860_U4RXD_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0), + SC9860_CMMCLK1_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0), + SC9860_CMRST1_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0), + SC9860_CMMCLK0_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0), + SC9860_CMRST0_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0), + SC9860_CMPD0_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0), + SC9860_CMPD1_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0), + SC9860_SCL0_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0), + SC9860_SDA0_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0), + SC9860_SDA6_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0), + SC9860_SCL6_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0), + SC9860_U1TXD_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0), + SC9860_U1RXD_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0), + SC9860_KEYOUT0_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0), + SC9860_KEYOUT1_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0), + SC9860_KEYOUT2_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0), + SC9860_KEYIN0_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0), + SC9860_KEYIN1_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0), + SC9860_KEYIN2_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0), + SC9860_IIS3DI_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0), + SC9860_IIS3DO_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0), + SC9860_IIS3CLK_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0), + SC9860_IIS3LRCK_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0), + SC9860_RFCTL0_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0), + SC9860_RFCTL1_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0), + SC9860_RFCTL10_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0), + SC9860_RFCTL11_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0), + SC9860_RFCTL12_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0), + SC9860_RFCTL13_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0), + SC9860_RFCTL14_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0), + SC9860_RFCTL15_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0), + SC9860_RFCTL16_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0), + SC9860_RFCTL17_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0), + SC9860_RFCTL18_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0), + SC9860_RFCTL19_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0), + SC9860_RFCTL2_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0), + SC9860_EXTINT5_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0), + SC9860_EXTINT6_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0), + SC9860_EXTINT7_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0), + SC9860_GPIO30_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0), + SC9860_GPIO31_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0), + SC9860_GPIO32_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0), + SC9860_GPIO33_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0), + SC9860_GPIO34_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0), + SC9860_RFCTL3_MISC = SPRD_PIN_INFO(394, MISC_PIN, 0, 0, 0), + SC9860_RFCTL4_MISC = SPRD_PIN_INFO(396, MISC_PIN, 0, 0, 0), + SC9860_RFCTL5_MISC = SPRD_PIN_INFO(398, MISC_PIN, 0, 0, 0), + SC9860_RFCTL6_MISC = SPRD_PIN_INFO(400, MISC_PIN, 0, 0, 0), + SC9860_RFCTL7_MISC = SPRD_PIN_INFO(402, MISC_PIN, 0, 0, 0), + SC9860_RFCTL8_MISC = SPRD_PIN_INFO(404, MISC_PIN, 0, 0, 0), + SC9860_RFCTL9_MISC = SPRD_PIN_INFO(406, MISC_PIN, 0, 0, 0), + SC9860_RFFE0_SCK0_MISC = SPRD_PIN_INFO(408, MISC_PIN, 0, 0, 0), + SC9860_GPIO38_MISC = SPRD_PIN_INFO(410, MISC_PIN, 0, 0, 0), + SC9860_RFFE0_SDA0_MISC = SPRD_PIN_INFO(412, MISC_PIN, 0, 0, 0), + SC9860_GPIO39_MISC = SPRD_PIN_INFO(414, MISC_PIN, 0, 0, 0), + SC9860_RFFE1_SCK0_MISC = SPRD_PIN_INFO(416, MISC_PIN, 0, 0, 0), + SC9860_GPIO181_MISC = SPRD_PIN_INFO(418, MISC_PIN, 0, 0, 0), + SC9860_RFFE1_SDA0_MISC = SPRD_PIN_INFO(420, MISC_PIN, 0, 0, 0), + SC9860_GPIO182_MISC = SPRD_PIN_INFO(422, MISC_PIN, 0, 0, 0), + SC9860_RF_LVDS0_ADC_ON_MISC = SPRD_PIN_INFO(424, MISC_PIN, 0, 0, 0), + SC9860_RF_LVDS0_DAC_ON_MISC = SPRD_PIN_INFO(426, MISC_PIN, 0, 0, 0), + SC9860_RFSCK0_MISC = SPRD_PIN_INFO(428, MISC_PIN, 0, 0, 0), + SC9860_RFSDA0_MISC = SPRD_PIN_INFO(430, MISC_PIN, 0, 0, 0), + SC9860_RFSEN0_MISC = SPRD_PIN_INFO(432, MISC_PIN, 0, 0, 0), + SC9860_RF_LVDS1_ADC_ON_MISC = SPRD_PIN_INFO(434, MISC_PIN, 0, 0, 0), + SC9860_RF_LVDS1_DAC_ON_MISC = SPRD_PIN_INFO(436, MISC_PIN, 0, 0, 0), + SC9860_RFSCK1_MISC = SPRD_PIN_INFO(438, MISC_PIN, 0, 0, 0), + SC9860_RFSDA1_MISC = SPRD_PIN_INFO(440, MISC_PIN, 0, 0, 0), + SC9860_RFSEN1_MISC = SPRD_PIN_INFO(442, MISC_PIN, 0, 0, 0), + SC9860_RFCTL38_MISC = SPRD_PIN_INFO(444, MISC_PIN, 0, 0, 0), + SC9860_RFCTL39_MISC = SPRD_PIN_INFO(446, MISC_PIN, 0, 0, 0), +}; + +static struct sprd_pins_info sprd_sc9860_pins_info[] = { + SPRD_PINCTRL_PIN(SC9860_VIO28_0_IRTE), + SPRD_PINCTRL_PIN(SC9860_VIO_SD2_IRTE), + SPRD_PINCTRL_PIN(SC9860_VIO_SD0_IRTE), + SPRD_PINCTRL_PIN(SC9860_VIO_SIM2_IRTE), + SPRD_PINCTRL_PIN(SC9860_VIO_SIM1_IRTE), + SPRD_PINCTRL_PIN(SC9860_VIO_SIM0_IRTE), + SPRD_PINCTRL_PIN(SC9860_VIO28_0_MS), + SPRD_PINCTRL_PIN(SC9860_VIO_SD2_MS), + SPRD_PINCTRL_PIN(SC9860_VIO_SD0_MS), + SPRD_PINCTRL_PIN(SC9860_VIO_SIM2_MS), + SPRD_PINCTRL_PIN(SC9860_VIO_SIM1_MS), + SPRD_PINCTRL_PIN(SC9860_VIO_SIM0_MS), + SPRD_PINCTRL_PIN(SC9860_SPSPI_PIN_IN_SEL), + SPRD_PINCTRL_PIN(SC9860_UART1_USB30_PHY_SEL), + SPRD_PINCTRL_PIN(SC9860_USB30_PHY_DM_OE), + SPRD_PINCTRL_PIN(SC9860_USB30_PHY_DP_OE), + SPRD_PINCTRL_PIN(SC9860_UART5_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_ORP_URXD_PIN_IN_SEL), + SPRD_PINCTRL_PIN(SC9860_SIM2_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_SIM1_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_SIM0_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_CLK26MHZ_BUF_OUT_SEL), + SPRD_PINCTRL_PIN(SC9860_UART4_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_UART3_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_UART2_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_UART1_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_UART0_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_UART24_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_UART23_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_UART14_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_UART13_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS3_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS2_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS1_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS0_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS23_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS13_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS12_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS03_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS02_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS01_LOOP_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS6_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS5_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_IIS4_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_I2C_INF6_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_I2C_INF4_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_I2C_INF2_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_I2C_INF1_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_I2C_INF0_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF7_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF6_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF5_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF4_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF3_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF2_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF1_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_GPIO_INF0_SYS_SEL), + SPRD_PINCTRL_PIN(SC9860_WDRST_OUT_SEL), + SPRD_PINCTRL_PIN(SC9860_ADI_SYNC_PIN_OUT_SEL), + SPRD_PINCTRL_PIN(SC9860_CMRST_SEL), + SPRD_PINCTRL_PIN(SC9860_CMPD_SEL), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE11), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE10), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE9), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE8), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE7), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE6), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE5), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE4), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE3), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE2), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE1), + SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE0), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD3_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD2_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD1_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD0_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD7_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD6_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD5_SEL), + SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD4_SEL), + SPRD_PINCTRL_PIN(SC9860_RFCTL20), + SPRD_PINCTRL_PIN(SC9860_RFCTL21), + SPRD_PINCTRL_PIN(SC9860_RFCTL30), + SPRD_PINCTRL_PIN(SC9860_RFCTL31), + SPRD_PINCTRL_PIN(SC9860_RFCTL32), + SPRD_PINCTRL_PIN(SC9860_RFCTL33), + SPRD_PINCTRL_PIN(SC9860_RFCTL34), + SPRD_PINCTRL_PIN(SC9860_RFCTL35), + SPRD_PINCTRL_PIN(SC9860_RFCTL36), + SPRD_PINCTRL_PIN(SC9860_RFCTL37), + SPRD_PINCTRL_PIN(SC9860_RFCTL22), + SPRD_PINCTRL_PIN(SC9860_RFCTL23), + SPRD_PINCTRL_PIN(SC9860_RFCTL24), + SPRD_PINCTRL_PIN(SC9860_RFCTL25), + SPRD_PINCTRL_PIN(SC9860_RFCTL26), + SPRD_PINCTRL_PIN(SC9860_RFCTL27), + SPRD_PINCTRL_PIN(SC9860_RFCTL28), + SPRD_PINCTRL_PIN(SC9860_RFCTL29), + SPRD_PINCTRL_PIN(SC9860_SCL2), + SPRD_PINCTRL_PIN(SC9860_SDA2), + SPRD_PINCTRL_PIN(SC9860_MTCK_ARM), + SPRD_PINCTRL_PIN(SC9860_MTMS_ARM), + SPRD_PINCTRL_PIN(SC9860_XTL_EN0), + SPRD_PINCTRL_PIN(SC9860_PTEST), + SPRD_PINCTRL_PIN(SC9860_AUD_DAD1), + SPRD_PINCTRL_PIN(SC9860_AUD_ADD0), + SPRD_PINCTRL_PIN(SC9860_AUD_ADSYNC), + SPRD_PINCTRL_PIN(SC9860_AUD_SCLK), + SPRD_PINCTRL_PIN(SC9860_CHIP_SLEEP), + SPRD_PINCTRL_PIN(SC9860_CLK_32K), + SPRD_PINCTRL_PIN(SC9860_DCDC_ARM_EN), + SPRD_PINCTRL_PIN(SC9860_EXT_RST_B), + SPRD_PINCTRL_PIN(SC9860_ADI_D), + SPRD_PINCTRL_PIN(SC9860_ADI_SCLK), + SPRD_PINCTRL_PIN(SC9860_XTL_EN1), + SPRD_PINCTRL_PIN(SC9860_ANA_INT), + SPRD_PINCTRL_PIN(SC9860_AUD_DAD0), + SPRD_PINCTRL_PIN(SC9860_AUD_DASYNC), + SPRD_PINCTRL_PIN(SC9860_LCM_RSTN), + SPRD_PINCTRL_PIN(SC9860_DSI_TE), + SPRD_PINCTRL_PIN(SC9860_PWMA), + SPRD_PINCTRL_PIN(SC9860_EXTINT0), + SPRD_PINCTRL_PIN(SC9860_EXTINT1), + SPRD_PINCTRL_PIN(SC9860_SDA1), + SPRD_PINCTRL_PIN(SC9860_SCL1), + SPRD_PINCTRL_PIN(SC9860_SIMCLK2), + SPRD_PINCTRL_PIN(SC9860_SIMDA2), + SPRD_PINCTRL_PIN(SC9860_SIMRST2), + SPRD_PINCTRL_PIN(SC9860_SIMCLK1), + SPRD_PINCTRL_PIN(SC9860_SIMDA1), + SPRD_PINCTRL_PIN(SC9860_SIMRST1), + SPRD_PINCTRL_PIN(SC9860_SIMCLK0), + SPRD_PINCTRL_PIN(SC9860_SIMDA0), + SPRD_PINCTRL_PIN(SC9860_SIMRST0), + SPRD_PINCTRL_PIN(SC9860_SD2_CMD), + SPRD_PINCTRL_PIN(SC9860_SD2_D0), + SPRD_PINCTRL_PIN(SC9860_SD2_D1), + SPRD_PINCTRL_PIN(SC9860_SD2_CLK), + SPRD_PINCTRL_PIN(SC9860_SD2_D2), + SPRD_PINCTRL_PIN(SC9860_SD2_D3), + SPRD_PINCTRL_PIN(SC9860_SD0_D3), + SPRD_PINCTRL_PIN(SC9860_SD0_D2), + SPRD_PINCTRL_PIN(SC9860_SD0_CMD), + SPRD_PINCTRL_PIN(SC9860_SD0_D0), + SPRD_PINCTRL_PIN(SC9860_SD0_D1), + SPRD_PINCTRL_PIN(SC9860_SD0_CLK), + SPRD_PINCTRL_PIN(SC9860_EMMC_CMD), + SPRD_PINCTRL_PIN(SC9860_EMMC_D6), + SPRD_PINCTRL_PIN(SC9860_EMMC_D7), + SPRD_PINCTRL_PIN(SC9860_EMMC_CLK), + SPRD_PINCTRL_PIN(SC9860_EMMC_D5), + SPRD_PINCTRL_PIN(SC9860_EMMC_D4), + SPRD_PINCTRL_PIN(SC9860_EMMC_DS), + SPRD_PINCTRL_PIN(SC9860_EMMC_D3), + SPRD_PINCTRL_PIN(SC9860_EMMC_RST), + SPRD_PINCTRL_PIN(SC9860_EMMC_D1), + SPRD_PINCTRL_PIN(SC9860_EMMC_D2), + SPRD_PINCTRL_PIN(SC9860_EMMC_D0), + SPRD_PINCTRL_PIN(SC9860_IIS0DI), + SPRD_PINCTRL_PIN(SC9860_IIS0DO), + SPRD_PINCTRL_PIN(SC9860_IIS0CLK), + SPRD_PINCTRL_PIN(SC9860_IIS0LRCK), + SPRD_PINCTRL_PIN(SC9860_SD1_CLK), + SPRD_PINCTRL_PIN(SC9860_SD1_CMD), + SPRD_PINCTRL_PIN(SC9860_SD1_D0), + SPRD_PINCTRL_PIN(SC9860_SD1_D1), + SPRD_PINCTRL_PIN(SC9860_SD1_D2), + SPRD_PINCTRL_PIN(SC9860_SD1_D3), + SPRD_PINCTRL_PIN(SC9860_CLK_AUX0), + SPRD_PINCTRL_PIN(SC9860_WIFI_COEXIST), + SPRD_PINCTRL_PIN(SC9860_BEIDOU_COEXIST), + SPRD_PINCTRL_PIN(SC9860_U3TXD), + SPRD_PINCTRL_PIN(SC9860_U3RXD), + SPRD_PINCTRL_PIN(SC9860_U3CTS), + SPRD_PINCTRL_PIN(SC9860_U3RTS), + SPRD_PINCTRL_PIN(SC9860_U0TXD), + SPRD_PINCTRL_PIN(SC9860_U0RXD), + SPRD_PINCTRL_PIN(SC9860_U0CTS), + SPRD_PINCTRL_PIN(SC9860_U0RTS), + SPRD_PINCTRL_PIN(SC9860_IIS1DI), + SPRD_PINCTRL_PIN(SC9860_IIS1DO), + SPRD_PINCTRL_PIN(SC9860_IIS1CLK), + SPRD_PINCTRL_PIN(SC9860_IIS1LRCK), + SPRD_PINCTRL_PIN(SC9860_SPI0_CSN), + SPRD_PINCTRL_PIN(SC9860_SPI0_DO), + SPRD_PINCTRL_PIN(SC9860_SPI0_DI), + SPRD_PINCTRL_PIN(SC9860_SPI0_CLK), + SPRD_PINCTRL_PIN(SC9860_U2TXD), + SPRD_PINCTRL_PIN(SC9860_U2RXD), + SPRD_PINCTRL_PIN(SC9860_U4TXD), + SPRD_PINCTRL_PIN(SC9860_U4RXD), + SPRD_PINCTRL_PIN(SC9860_CMMCLK1), + SPRD_PINCTRL_PIN(SC9860_CMRST1), + SPRD_PINCTRL_PIN(SC9860_CMMCLK0), + SPRD_PINCTRL_PIN(SC9860_CMRST0), + SPRD_PINCTRL_PIN(SC9860_CMPD0), + SPRD_PINCTRL_PIN(SC9860_CMPD1), + SPRD_PINCTRL_PIN(SC9860_SCL0), + SPRD_PINCTRL_PIN(SC9860_SDA0), + SPRD_PINCTRL_PIN(SC9860_SDA6), + SPRD_PINCTRL_PIN(SC9860_SCL6), + SPRD_PINCTRL_PIN(SC9860_U1TXD), + SPRD_PINCTRL_PIN(SC9860_U1RXD), + SPRD_PINCTRL_PIN(SC9860_KEYOUT0), + SPRD_PINCTRL_PIN(SC9860_KEYOUT1), + SPRD_PINCTRL_PIN(SC9860_KEYOUT2), + SPRD_PINCTRL_PIN(SC9860_KEYIN0), + SPRD_PINCTRL_PIN(SC9860_KEYIN1), + SPRD_PINCTRL_PIN(SC9860_KEYIN2), + SPRD_PINCTRL_PIN(SC9860_IIS3DI), + SPRD_PINCTRL_PIN(SC9860_IIS3DO), + SPRD_PINCTRL_PIN(SC9860_IIS3CLK), + SPRD_PINCTRL_PIN(SC9860_IIS3LRCK), + SPRD_PINCTRL_PIN(SC9860_RFCTL0), + SPRD_PINCTRL_PIN(SC9860_RFCTL1), + SPRD_PINCTRL_PIN(SC9860_RFCTL10), + SPRD_PINCTRL_PIN(SC9860_RFCTL11), + SPRD_PINCTRL_PIN(SC9860_RFCTL12), + SPRD_PINCTRL_PIN(SC9860_RFCTL13), + SPRD_PINCTRL_PIN(SC9860_RFCTL14), + SPRD_PINCTRL_PIN(SC9860_RFCTL15), + SPRD_PINCTRL_PIN(SC9860_RFCTL16), + SPRD_PINCTRL_PIN(SC9860_RFCTL17), + SPRD_PINCTRL_PIN(SC9860_RFCTL18), + SPRD_PINCTRL_PIN(SC9860_RFCTL19), + SPRD_PINCTRL_PIN(SC9860_RFCTL2), + SPRD_PINCTRL_PIN(SC9860_EXTINT5), + SPRD_PINCTRL_PIN(SC9860_EXTINT6), + SPRD_PINCTRL_PIN(SC9860_EXTINT7), + SPRD_PINCTRL_PIN(SC9860_GPIO30), + SPRD_PINCTRL_PIN(SC9860_GPIO31), + SPRD_PINCTRL_PIN(SC9860_GPIO32), + SPRD_PINCTRL_PIN(SC9860_GPIO33), + SPRD_PINCTRL_PIN(SC9860_GPIO34), + SPRD_PINCTRL_PIN(SC9860_RFCTL3), + SPRD_PINCTRL_PIN(SC9860_RFCTL4), + SPRD_PINCTRL_PIN(SC9860_RFCTL5), + SPRD_PINCTRL_PIN(SC9860_RFCTL6), + SPRD_PINCTRL_PIN(SC9860_RFCTL7), + SPRD_PINCTRL_PIN(SC9860_RFCTL8), + SPRD_PINCTRL_PIN(SC9860_RFCTL9), + SPRD_PINCTRL_PIN(SC9860_RFFE0_SCK0), + SPRD_PINCTRL_PIN(SC9860_GPIO38), + SPRD_PINCTRL_PIN(SC9860_RFFE0_SDA0), + SPRD_PINCTRL_PIN(SC9860_GPIO39), + SPRD_PINCTRL_PIN(SC9860_RFFE1_SCK0), + SPRD_PINCTRL_PIN(SC9860_GPIO181), + SPRD_PINCTRL_PIN(SC9860_RFFE1_SDA0), + SPRD_PINCTRL_PIN(SC9860_GPIO182), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_ADC_ON), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_DAC_ON), + SPRD_PINCTRL_PIN(SC9860_RFSCK0), + SPRD_PINCTRL_PIN(SC9860_RFSDA0), + SPRD_PINCTRL_PIN(SC9860_RFSEN0), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_ADC_ON), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_DAC_ON), + SPRD_PINCTRL_PIN(SC9860_RFSCK1), + SPRD_PINCTRL_PIN(SC9860_RFSDA1), + SPRD_PINCTRL_PIN(SC9860_RFSEN1), + SPRD_PINCTRL_PIN(SC9860_RFCTL38), + SPRD_PINCTRL_PIN(SC9860_RFCTL39), + SPRD_PINCTRL_PIN(SC9860_RFCTL20_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL21_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL30_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL31_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL32_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL33_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL34_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL35_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL36_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL37_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL22_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL23_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL24_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL25_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL26_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL27_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL28_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL29_MISC), + SPRD_PINCTRL_PIN(SC9860_SCL2_MISC), + SPRD_PINCTRL_PIN(SC9860_SDA2_MISC), + SPRD_PINCTRL_PIN(SC9860_MTCK_ARM_MISC), + SPRD_PINCTRL_PIN(SC9860_MTMS_ARM_MISC), + SPRD_PINCTRL_PIN(SC9860_XTL_EN0_MISC), + SPRD_PINCTRL_PIN(SC9860_PTEST_MISC), + SPRD_PINCTRL_PIN(SC9860_AUD_DAD1_MISC), + SPRD_PINCTRL_PIN(SC9860_AUD_ADD0_MISC), + SPRD_PINCTRL_PIN(SC9860_AUD_ADSYNC_MISC), + SPRD_PINCTRL_PIN(SC9860_AUD_SCLK_MISC), + SPRD_PINCTRL_PIN(SC9860_CHIP_SLEEP_MISC), + SPRD_PINCTRL_PIN(SC9860_CLK_32K_MISC), + SPRD_PINCTRL_PIN(SC9860_DCDC_ARM_EN_MISC), + SPRD_PINCTRL_PIN(SC9860_EXT_RST_B_MISC), + SPRD_PINCTRL_PIN(SC9860_ADI_D_MISC), + SPRD_PINCTRL_PIN(SC9860_ADI_SCLK_MISC), + SPRD_PINCTRL_PIN(SC9860_XTL_EN1_MISC), + SPRD_PINCTRL_PIN(SC9860_ANA_INT_MISC), + SPRD_PINCTRL_PIN(SC9860_AUD_DAD0_MISC), + SPRD_PINCTRL_PIN(SC9860_AUD_DASYNC_MISC), + SPRD_PINCTRL_PIN(SC9860_LCM_RSTN_MISC), + SPRD_PINCTRL_PIN(SC9860_DSI_TE_MISC), + SPRD_PINCTRL_PIN(SC9860_PWMA_MISC), + SPRD_PINCTRL_PIN(SC9860_EXTINT0_MISC), + SPRD_PINCTRL_PIN(SC9860_EXTINT1_MISC), + SPRD_PINCTRL_PIN(SC9860_SDA1_MISC), + SPRD_PINCTRL_PIN(SC9860_SCL1_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMCLK2_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMDA2_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMRST2_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMCLK1_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMDA1_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMRST1_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMCLK0_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMDA0_MISC), + SPRD_PINCTRL_PIN(SC9860_SIMRST0_MISC), + SPRD_PINCTRL_PIN(SC9860_SD2_CMD_MISC), + SPRD_PINCTRL_PIN(SC9860_SD2_D0_MISC), + SPRD_PINCTRL_PIN(SC9860_SD2_D1_MISC), + SPRD_PINCTRL_PIN(SC9860_SD2_CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_SD2_D2_MISC), + SPRD_PINCTRL_PIN(SC9860_SD2_D3_MISC), + SPRD_PINCTRL_PIN(SC9860_SD0_D3_MISC), + SPRD_PINCTRL_PIN(SC9860_SD0_D2_MISC), + SPRD_PINCTRL_PIN(SC9860_SD0_CMD_MISC), + SPRD_PINCTRL_PIN(SC9860_SD0_D0_MISC), + SPRD_PINCTRL_PIN(SC9860_SD0_D1_MISC), + SPRD_PINCTRL_PIN(SC9860_SD0_CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_CMD_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D6_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D7_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D5_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D4_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_DS_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D3_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_RST_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D1_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D2_MISC), + SPRD_PINCTRL_PIN(SC9860_EMMC_D0_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS0DI_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS0DO_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS0CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS0LRCK_MISC), + SPRD_PINCTRL_PIN(SC9860_SD1_CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_SD1_CMD_MISC), + SPRD_PINCTRL_PIN(SC9860_SD1_D0_MISC), + SPRD_PINCTRL_PIN(SC9860_SD1_D1_MISC), + SPRD_PINCTRL_PIN(SC9860_SD1_D2_MISC), + SPRD_PINCTRL_PIN(SC9860_SD1_D3_MISC), + SPRD_PINCTRL_PIN(SC9860_CLK_AUX0_MISC), + SPRD_PINCTRL_PIN(SC9860_WIFI_COEXIST_MISC), + SPRD_PINCTRL_PIN(SC9860_BEIDOU_COEXIST_MISC), + SPRD_PINCTRL_PIN(SC9860_U3TXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U3RXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U3CTS_MISC), + SPRD_PINCTRL_PIN(SC9860_U3RTS_MISC), + SPRD_PINCTRL_PIN(SC9860_U0TXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U0RXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U0CTS_MISC), + SPRD_PINCTRL_PIN(SC9860_U0RTS_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS1DI_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS1DO_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS1CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS1LRCK_MISC), + SPRD_PINCTRL_PIN(SC9860_SPI0_CSN_MISC), + SPRD_PINCTRL_PIN(SC9860_SPI0_DO_MISC), + SPRD_PINCTRL_PIN(SC9860_SPI0_DI_MISC), + SPRD_PINCTRL_PIN(SC9860_SPI0_CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_U2TXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U2RXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U4TXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U4RXD_MISC), + SPRD_PINCTRL_PIN(SC9860_CMMCLK1_MISC), + SPRD_PINCTRL_PIN(SC9860_CMRST1_MISC), + SPRD_PINCTRL_PIN(SC9860_CMMCLK0_MISC), + SPRD_PINCTRL_PIN(SC9860_CMRST0_MISC), + SPRD_PINCTRL_PIN(SC9860_CMPD0_MISC), + SPRD_PINCTRL_PIN(SC9860_CMPD1_MISC), + SPRD_PINCTRL_PIN(SC9860_SCL0_MISC), + SPRD_PINCTRL_PIN(SC9860_SDA0_MISC), + SPRD_PINCTRL_PIN(SC9860_SDA6_MISC), + SPRD_PINCTRL_PIN(SC9860_SCL6_MISC), + SPRD_PINCTRL_PIN(SC9860_U1TXD_MISC), + SPRD_PINCTRL_PIN(SC9860_U1RXD_MISC), + SPRD_PINCTRL_PIN(SC9860_KEYOUT0_MISC), + SPRD_PINCTRL_PIN(SC9860_KEYOUT1_MISC), + SPRD_PINCTRL_PIN(SC9860_KEYOUT2_MISC), + SPRD_PINCTRL_PIN(SC9860_KEYIN0_MISC), + SPRD_PINCTRL_PIN(SC9860_KEYIN1_MISC), + SPRD_PINCTRL_PIN(SC9860_KEYIN2_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS3DI_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS3DO_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS3CLK_MISC), + SPRD_PINCTRL_PIN(SC9860_IIS3LRCK_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL0_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL1_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL10_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL11_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL12_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL13_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL14_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL15_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL16_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL17_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL18_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL19_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL2_MISC), + SPRD_PINCTRL_PIN(SC9860_EXTINT5_MISC), + SPRD_PINCTRL_PIN(SC9860_EXTINT6_MISC), + SPRD_PINCTRL_PIN(SC9860_EXTINT7_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO30_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO31_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO32_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO33_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO34_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL3_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL4_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL5_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL6_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL7_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL8_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL9_MISC), + SPRD_PINCTRL_PIN(SC9860_RFFE0_SCK0_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO38_MISC), + SPRD_PINCTRL_PIN(SC9860_RFFE0_SDA0_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO39_MISC), + SPRD_PINCTRL_PIN(SC9860_RFFE1_SCK0_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO181_MISC), + SPRD_PINCTRL_PIN(SC9860_RFFE1_SDA0_MISC), + SPRD_PINCTRL_PIN(SC9860_GPIO182_MISC), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_ADC_ON_MISC), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_DAC_ON_MISC), + SPRD_PINCTRL_PIN(SC9860_RFSCK0_MISC), + SPRD_PINCTRL_PIN(SC9860_RFSDA0_MISC), + SPRD_PINCTRL_PIN(SC9860_RFSEN0_MISC), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_ADC_ON_MISC), + SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_DAC_ON_MISC), + SPRD_PINCTRL_PIN(SC9860_RFSCK1_MISC), + SPRD_PINCTRL_PIN(SC9860_RFSDA1_MISC), + SPRD_PINCTRL_PIN(SC9860_RFSEN1_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL38_MISC), + SPRD_PINCTRL_PIN(SC9860_RFCTL39_MISC), +}; + +static int sprd_pinctrl_probe(struct platform_device *pdev) +{ + return sprd_pinctrl_core_probe(pdev, sprd_sc9860_pins_info, + ARRAY_SIZE(sprd_sc9860_pins_info)); +} + +static const struct of_device_id sprd_pinctrl_of_match[] = { + { + .compatible = "sprd,sc9860-pinctrl", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match); + +static struct platform_driver sprd_pinctrl_driver = { + .driver = { + .name = "sprd-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sprd_pinctrl_of_match, + }, + .probe = sprd_pinctrl_probe, + .remove = sprd_pinctrl_remove, + .shutdown = sprd_pinctrl_shutdown, +}; + +static int sprd_pinctrl_init(void) +{ + return platform_driver_register(&sprd_pinctrl_driver); +} +module_init(sprd_pinctrl_init); + +static void sprd_pinctrl_exit(void) +{ + platform_driver_unregister(&sprd_pinctrl_driver); +} +module_exit(sprd_pinctrl_exit); + +MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver"); +MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c new file mode 100644 index 000000000000..7e7b9ac7e836 --- /dev/null +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -0,0 +1,1113 @@ +/* + * Spreadtrum pin controller driver + * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include <linux/debugfs.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinmux.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" +#include "pinctrl-sprd.h" + +#define PINCTRL_BIT_MASK(width) (~(~0UL << (width))) +#define PINCTRL_REG_OFFSET 0x20 +#define PINCTRL_REG_MISC_OFFSET 0x4020 +#define PINCTRL_REG_LEN 0x4 + +#define PIN_FUNC_MASK (BIT(4) | BIT(5)) +#define PIN_FUNC_SEL_1 ~PIN_FUNC_MASK +#define PIN_FUNC_SEL_2 BIT(4) +#define PIN_FUNC_SEL_3 BIT(5) +#define PIN_FUNC_SEL_4 PIN_FUNC_MASK + +#define AP_SLEEP_MODE BIT(13) +#define PUBCP_SLEEP_MODE BIT(14) +#define TGLDSP_SLEEP_MODE BIT(15) +#define AGDSP_SLEEP_MODE BIT(16) +#define SLEEP_MODE_MASK GENMASK(3, 0) +#define SLEEP_MODE_SHIFT 13 + +#define SLEEP_INPUT BIT(1) +#define SLEEP_INPUT_MASK 0x1 +#define SLEEP_INPUT_SHIFT 1 + +#define SLEEP_OUTPUT BIT(0) +#define SLEEP_OUTPUT_MASK 0x1 +#define SLEEP_OUTPUT_SHIFT 0 + +#define DRIVE_STRENGTH_MASK GENMASK(3, 0) +#define DRIVE_STRENGTH_SHIFT 19 + +#define SLEEP_PULL_DOWN BIT(2) +#define SLEEP_PULL_DOWN_MASK 0x1 +#define SLEEP_PULL_DOWN_SHIFT 2 + +#define PULL_DOWN BIT(6) +#define PULL_DOWN_MASK 0x1 +#define PULL_DOWN_SHIFT 6 + +#define SLEEP_PULL_UP BIT(3) +#define SLEEP_PULL_UP_MASK 0x1 +#define SLEEP_PULL_UP_SHIFT 3 + +#define PULL_UP_20K (BIT(12) | BIT(7)) +#define PULL_UP_4_7K BIT(12) +#define PULL_UP_MASK 0x21 +#define PULL_UP_SHIFT 7 + +#define INPUT_SCHMITT BIT(11) +#define INPUT_SCHMITT_MASK 0x1 +#define INPUT_SCHMITT_SHIFT 11 + +enum pin_sleep_mode { + AP_SLEEP = BIT(0), + PUBCP_SLEEP = BIT(1), + TGLDSP_SLEEP = BIT(2), + AGDSP_SLEEP = BIT(3), +}; + +enum pin_func_sel { + PIN_FUNC_1, + PIN_FUNC_2, + PIN_FUNC_3, + PIN_FUNC_4, + PIN_FUNC_MAX, +}; + +/** + * struct sprd_pin: represent one pin's description + * @name: pin name + * @number: pin number + * @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN + * @reg: pin register address + * @bit_offset: bit offset in pin register + * @bit_width: bit width in pin register + */ +struct sprd_pin { + const char *name; + unsigned int number; + enum pin_type type; + unsigned long reg; + unsigned long bit_offset; + unsigned long bit_width; +}; + +/** + * struct sprd_pin_group: represent one group's description + * @name: group name + * @npins: pin numbers of this group + * @pins: pointer to pins array + */ +struct sprd_pin_group { + const char *name; + unsigned int npins; + unsigned int *pins; +}; + +/** + * struct sprd_pinctrl_soc_info: represent the SoC's pins description + * @groups: pointer to groups of pins + * @ngroups: group numbers of the whole SoC + * @pins: pointer to pins description + * @npins: pin numbers of the whole SoC + * @grp_names: pointer to group names array + */ +struct sprd_pinctrl_soc_info { + struct sprd_pin_group *groups; + unsigned int ngroups; + struct sprd_pin *pins; + unsigned int npins; + const char **grp_names; +}; + +/** + * struct sprd_pinctrl: represent the pin controller device + * @dev: pointer to the device structure + * @pctl: pointer to the pinctrl handle + * @base: base address of the controller + * @info: pointer to SoC's pins description information + */ +struct sprd_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + struct sprd_pinctrl_soc_info *info; +}; + +enum sprd_pinconf_params { + SPRD_PIN_CONFIG_CONTROL = PIN_CONFIG_END + 1, + SPRD_PIN_CONFIG_SLEEP_MODE = PIN_CONFIG_END + 2, +}; + +static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl, + const char *name) +{ + struct sprd_pinctrl_soc_info *info = sprd_pctl->info; + int i; + + for (i = 0; i < info->npins; i++) { + if (!strcmp(info->pins[i].name, name)) + return info->pins[i].number; + } + + return -ENODEV; +} + +static struct sprd_pin * +sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id) +{ + struct sprd_pinctrl_soc_info *info = sprd_pctl->info; + struct sprd_pin *pin = NULL; + int i; + + for (i = 0; i < info->npins; i++) { + if (info->pins[i].number == id) { + pin = &info->pins[i]; + break; + } + } + + return pin; +} + +static const struct sprd_pin_group * +sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl, + const char *name) +{ + struct sprd_pinctrl_soc_info *info = sprd_pctl->info; + const struct sprd_pin_group *grp = NULL; + int i; + + for (i = 0; i < info->ngroups; i++) { + if (!strcmp(info->groups[i].name, name)) { + grp = &info->groups[i]; + break; + } + } + + return grp; +} + +static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + + return info->ngroups; +} + +static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + + return info->groups[selector].name; +} + +static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + + if (selector >= info->ngroups) + return -EINVAL; + + *pins = info->groups[selector].pins; + *npins = info->groups[selector].npins; + + return 0; +} + +static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct sprd_pin_group *grp; + unsigned long *configs = NULL; + unsigned int num_configs = 0; + unsigned int reserved_maps = 0; + unsigned int reserve = 0; + const char *function; + enum pinctrl_map_type type; + int ret; + + grp = sprd_pinctrl_find_group_by_name(pctl, np->name); + if (!grp) { + dev_err(pctl->dev, "unable to find group for node %s\n", + of_node_full_name(np)); + return -EINVAL; + } + + ret = of_property_count_strings(np, "pins"); + if (ret < 0) + return ret; + + if (ret == 1) + type = PIN_MAP_TYPE_CONFIGS_PIN; + else + type = PIN_MAP_TYPE_CONFIGS_GROUP; + + ret = of_property_read_string(np, "function", &function); + if (ret < 0) { + if (ret != -EINVAL) + dev_err(pctl->dev, + "%s: could not parse property function\n", + of_node_full_name(np)); + function = NULL; + } + + ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, + &num_configs); + if (ret < 0) { + dev_err(pctl->dev, "%s: could not parse node property\n", + of_node_full_name(np)); + return ret; + } + + *map = NULL; + *num_maps = 0; + + if (function != NULL) + reserve++; + if (num_configs) + reserve++; + + ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, + num_maps, reserve); + if (ret < 0) + goto out; + + if (function) { + ret = pinctrl_utils_add_map_mux(pctldev, map, + &reserved_maps, num_maps, + grp->name, function); + if (ret < 0) + goto out; + } + + if (num_configs) { + const char *group_or_pin; + unsigned int pin_id; + + if (type == PIN_MAP_TYPE_CONFIGS_PIN) { + pin_id = grp->pins[0]; + group_or_pin = pin_get_name(pctldev, pin_id); + } else { + group_or_pin = grp->name; + } + + ret = pinctrl_utils_add_map_configs(pctldev, map, + &reserved_maps, num_maps, + group_or_pin, configs, + num_configs, type); + } + +out: + kfree(configs); + return ret; +} + +static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, "%s", dev_name(pctldev->dev)); +} + +static const struct pinctrl_ops sprd_pctrl_ops = { + .get_groups_count = sprd_pctrl_group_count, + .get_group_name = sprd_pctrl_group_name, + .get_group_pins = sprd_pctrl_group_pins, + .pin_dbg_show = sprd_pctrl_dbg_show, + .dt_node_to_map = sprd_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev) +{ + return PIN_FUNC_MAX; +} + +const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + switch (selector) { + case PIN_FUNC_1: + return "func1"; + case PIN_FUNC_2: + return "func2"; + case PIN_FUNC_3: + return "func3"; + case PIN_FUNC_4: + return "func4"; + default: + return "null"; + } +} + +int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + + *groups = info->grp_names; + *num_groups = info->ngroups; + + return 0; +} + +static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + struct sprd_pin_group *grp = &info->groups[group_selector]; + unsigned int i, grp_pins = grp->npins; + unsigned long reg; + unsigned int val = 0; + + if (group_selector > info->ngroups) + return -EINVAL; + + switch (func_selector) { + case PIN_FUNC_1: + val &= PIN_FUNC_SEL_1; + break; + case PIN_FUNC_2: + val |= PIN_FUNC_SEL_2; + break; + case PIN_FUNC_3: + val |= PIN_FUNC_SEL_3; + break; + case PIN_FUNC_4: + val |= PIN_FUNC_SEL_4; + break; + default: + break; + } + + for (i = 0; i < grp_pins; i++) { + unsigned int pin_id = grp->pins[i]; + struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); + + if (!pin || pin->type != COMMON_PIN) + continue; + + reg = readl((void __iomem *)pin->reg); + reg &= ~PIN_FUNC_MASK; + reg |= val; + writel(reg, (void __iomem *)pin->reg); + } + + return 0; +} + +static const struct pinmux_ops sprd_pmx_ops = { + .get_functions_count = sprd_pmx_get_function_count, + .get_function_name = sprd_pmx_get_function_name, + .get_function_groups = sprd_pmx_get_function_groups, + .set_mux = sprd_pmx_set_mux, +}; + +static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *config) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); + unsigned int param = pinconf_to_config_param(*config); + unsigned int reg, arg; + + if (!pin) + return -EINVAL; + + if (pin->type == GLOBAL_CTRL_PIN) { + reg = (readl((void __iomem *)pin->reg) >> + pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); + } else { + reg = readl((void __iomem *)pin->reg); + } + + if (pin->type == GLOBAL_CTRL_PIN && + param == SPRD_PIN_CONFIG_CONTROL) { + arg = reg; + } else if (pin->type == COMMON_PIN) { + switch (param) { + case SPRD_PIN_CONFIG_SLEEP_MODE: + arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK; + break; + case PIN_CONFIG_INPUT_ENABLE: + arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK; + break; + case PIN_CONFIG_OUTPUT: + arg = reg & SLEEP_OUTPUT_MASK; + break; + case PIN_CONFIG_SLEEP_HARDWARE_STATE: + arg = 0; + break; + default: + return -ENOTSUPP; + } + } else if (pin->type == MISC_PIN) { + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + arg = (reg >> DRIVE_STRENGTH_SHIFT) & + DRIVE_STRENGTH_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + /* combine sleep pull down and pull down config */ + arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) & + SLEEP_PULL_DOWN_MASK) << 16; + arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK; + break; + case PIN_CONFIG_BIAS_PULL_UP: + /* combine sleep pull up and pull up config */ + arg = ((reg >> SLEEP_PULL_UP_SHIFT) & + SLEEP_PULL_UP_MASK) << 16; + arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK; + break; + case PIN_CONFIG_SLEEP_HARDWARE_STATE: + arg = 0; + break; + default: + return -ENOTSUPP; + } + } else { + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static unsigned int sprd_pinconf_drive(unsigned int mA) +{ + unsigned int val = 0; + + switch (mA) { + case 2: + break; + case 4: + val |= BIT(19); + break; + case 6: + val |= BIT(20); + break; + case 8: + val |= BIT(19) | BIT(20); + break; + case 10: + val |= BIT(21); + break; + case 12: + val |= BIT(21) | BIT(19); + break; + case 14: + val |= BIT(21) | BIT(20); + break; + case 16: + val |= BIT(19) | BIT(20) | BIT(21); + break; + case 20: + val |= BIT(22); + break; + case 21: + val |= BIT(22) | BIT(19); + break; + case 24: + val |= BIT(22) | BIT(20); + break; + case 25: + val |= BIT(22) | BIT(20) | BIT(19); + break; + case 27: + val |= BIT(22) | BIT(21); + break; + case 29: + val |= BIT(22) | BIT(21) | BIT(19); + break; + case 31: + val |= BIT(22) | BIT(21) | BIT(20); + break; + case 33: + val |= BIT(22) | BIT(21) | BIT(20) | BIT(19); + break; + default: + break; + } + + return val; +} + +static bool sprd_pinctrl_check_sleep_config(unsigned long *configs, + unsigned int num_configs) +{ + unsigned int param; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE) + return true; + } + + return false; +} + +static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *configs, unsigned int num_configs) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); + bool is_sleep_config; + unsigned long reg; + int i; + + if (!pin) + return -EINVAL; + + is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs); + + for (i = 0; i < num_configs; i++) { + unsigned int param, arg, shift, mask, val; + + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + val = 0; + shift = 0; + mask = 0; + if (pin->type == GLOBAL_CTRL_PIN && + param == SPRD_PIN_CONFIG_CONTROL) { + val = arg; + } else if (pin->type == COMMON_PIN) { + switch (param) { + case SPRD_PIN_CONFIG_SLEEP_MODE: + if (arg & AP_SLEEP) + val |= AP_SLEEP_MODE; + if (arg & PUBCP_SLEEP) + val |= PUBCP_SLEEP_MODE; + if (arg & TGLDSP_SLEEP) + val |= TGLDSP_SLEEP_MODE; + if (arg & AGDSP_SLEEP) + val |= AGDSP_SLEEP_MODE; + + mask = SLEEP_MODE_MASK; + shift = SLEEP_MODE_SHIFT; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (is_sleep_config == true) { + if (arg > 0) + val |= SLEEP_INPUT; + else + val &= ~SLEEP_INPUT; + + mask = SLEEP_INPUT_MASK; + shift = SLEEP_INPUT_SHIFT; + } + break; + case PIN_CONFIG_OUTPUT: + if (is_sleep_config == true) { + val |= SLEEP_OUTPUT; + mask = SLEEP_OUTPUT_MASK; + shift = SLEEP_OUTPUT_SHIFT; + } + break; + case PIN_CONFIG_SLEEP_HARDWARE_STATE: + continue; + default: + return -ENOTSUPP; + } + } else if (pin->type == MISC_PIN) { + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + if (arg < 2 || arg > 60) + return -EINVAL; + + val = sprd_pinconf_drive(arg); + mask = DRIVE_STRENGTH_MASK; + shift = DRIVE_STRENGTH_SHIFT; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (is_sleep_config == true) { + val |= SLEEP_PULL_DOWN; + mask = SLEEP_PULL_DOWN_MASK; + shift = SLEEP_PULL_DOWN_SHIFT; + } else { + val |= PULL_DOWN; + mask = PULL_DOWN_MASK; + shift = PULL_DOWN_SHIFT; + } + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg > 0) + val |= INPUT_SCHMITT; + else + val &= ~INPUT_SCHMITT; + + mask = INPUT_SCHMITT_MASK; + shift = INPUT_SCHMITT_SHIFT; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (is_sleep_config == true) { + val |= SLEEP_PULL_UP; + mask = SLEEP_PULL_UP_MASK; + shift = SLEEP_PULL_UP_SHIFT; + } else { + if (arg == 20000) + val |= PULL_UP_20K; + else if (arg == 4700) + val |= PULL_UP_4_7K; + + mask = PULL_UP_MASK; + shift = PULL_UP_SHIFT; + } + break; + case PIN_CONFIG_SLEEP_HARDWARE_STATE: + continue; + default: + return -ENOTSUPP; + } + } else { + return -ENOTSUPP; + } + + if (pin->type == GLOBAL_CTRL_PIN) { + reg = readl((void __iomem *)pin->reg); + reg &= ~(PINCTRL_BIT_MASK(pin->bit_width) + << pin->bit_offset); + reg |= (val & PINCTRL_BIT_MASK(pin->bit_width)) + << pin->bit_offset; + writel(reg, (void __iomem *)pin->reg); + } else { + reg = readl((void __iomem *)pin->reg); + reg &= ~(mask << shift); + reg |= val; + writel(reg, (void __iomem *)pin->reg); + } + } + + return 0; +} + +static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned long *config) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + struct sprd_pin_group *grp; + unsigned int pin_id; + + if (selector > info->ngroups) + return -EINVAL; + + grp = &info->groups[selector]; + pin_id = grp->pins[0]; + + return sprd_pinconf_get(pctldev, pin_id, config); +} + +static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + struct sprd_pin_group *grp; + int ret, i; + + if (selector > info->ngroups) + return -EINVAL; + + grp = &info->groups[selector]; + + for (i = 0; i < grp->npins; i++) { + unsigned int pin_id = grp->pins[i]; + + ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev, + unsigned int pin_id, + unsigned long *config) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id); + + if (!pin) + return -EINVAL; + + if (pin->type == GLOBAL_CTRL_PIN) { + *config = (readl((void __iomem *)pin->reg) >> + pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); + } else { + *config = readl((void __iomem *)pin->reg); + } + + return 0; +} + +static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin_id) +{ + unsigned long config; + int ret; + + ret = sprd_pinconf_get_config(pctldev, pin_id, &config); + if (ret) + return; + + seq_printf(s, "0x%lx", config); +} + +static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int selector) +{ + struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sprd_pinctrl_soc_info *info = pctl->info; + struct sprd_pin_group *grp; + unsigned long config; + const char *name; + int i, ret; + + if (selector > info->ngroups) + return; + + grp = &info->groups[selector]; + + seq_printf(s, "\n"); + for (i = 0; i < grp->npins; i++, config++) { + unsigned int pin_id = grp->pins[i]; + + name = pin_get_name(pctldev, pin_id); + ret = sprd_pinconf_get_config(pctldev, pin_id, &config); + if (ret) + return; + + seq_printf(s, "%s: 0x%lx ", name, config); + } +} + +static const struct pinconf_ops sprd_pinconf_ops = { + .is_generic = true, + .pin_config_get = sprd_pinconf_get, + .pin_config_set = sprd_pinconf_set, + .pin_config_group_get = sprd_pinconf_group_get, + .pin_config_group_set = sprd_pinconf_group_set, + .pin_config_dbg_show = sprd_pinconf_dbg_show, + .pin_config_group_dbg_show = sprd_pinconf_group_dbg_show, +}; + +static const struct pinconf_generic_params sprd_dt_params[] = { + {"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0}, + {"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0}, +}; + +#ifdef CONFIG_DEBUG_FS +static const struct pin_config_item sprd_conf_items[] = { + PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true), + PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true), +}; +#endif + +static struct pinctrl_desc sprd_pinctrl_desc = { + .pctlops = &sprd_pctrl_ops, + .pmxops = &sprd_pmx_ops, + .confops = &sprd_pinconf_ops, + .num_custom_params = ARRAY_SIZE(sprd_dt_params), + .custom_params = sprd_dt_params, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items = sprd_conf_items, +#endif + .owner = THIS_MODULE, +}; + +static int sprd_pinctrl_parse_groups(struct device_node *np, + struct sprd_pinctrl *sprd_pctl, + struct sprd_pin_group *grp) +{ + struct property *prop; + const char *pin_name; + int ret, i = 0; + + ret = of_property_count_strings(np, "pins"); + if (ret < 0) + return ret; + + grp->name = np->name; + grp->npins = ret; + grp->pins = devm_kzalloc(sprd_pctl->dev, grp->npins * + sizeof(unsigned int), GFP_KERNEL); + if (!grp->pins) + return -ENOMEM; + + of_property_for_each_string(np, "pins", prop, pin_name) { + ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name); + if (ret >= 0) + grp->pins[i++] = ret; + } + + for (i = 0; i < grp->npins; i++) { + dev_dbg(sprd_pctl->dev, + "Group[%s] contains [%d] pins: id = %d\n", + grp->name, grp->npins, grp->pins[i]); + } + + return 0; +} + +static unsigned int sprd_pinctrl_get_groups(struct device_node *np) +{ + struct device_node *child; + unsigned int group_cnt, cnt; + + group_cnt = of_get_child_count(np); + + for_each_child_of_node(np, child) { + cnt = of_get_child_count(child); + if (cnt > 0) + group_cnt += cnt; + } + + return group_cnt; +} + +static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl) +{ + struct sprd_pinctrl_soc_info *info = sprd_pctl->info; + struct device_node *np = sprd_pctl->dev->of_node; + struct device_node *child, *sub_child; + struct sprd_pin_group *grp; + const char **temp; + int ret; + + if (!np) + return -ENODEV; + + info->ngroups = sprd_pinctrl_get_groups(np); + if (!info->ngroups) + return 0; + + info->groups = devm_kzalloc(sprd_pctl->dev, info->ngroups * + sizeof(struct sprd_pin_group), + GFP_KERNEL); + if (!info->groups) + return -ENOMEM; + + info->grp_names = devm_kzalloc(sprd_pctl->dev, + info->ngroups * sizeof(char *), + GFP_KERNEL); + if (!info->grp_names) + return -ENOMEM; + + temp = info->grp_names; + grp = info->groups; + + for_each_child_of_node(np, child) { + ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp); + if (ret) + return ret; + + *temp++ = grp->name; + grp++; + + if (of_get_child_count(child) > 0) { + for_each_child_of_node(child, sub_child) { + ret = sprd_pinctrl_parse_groups(sub_child, + sprd_pctl, grp); + if (ret) + return ret; + + *temp++ = grp->name; + grp++; + } + } + } + + return 0; +} + +static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl, + struct sprd_pins_info *sprd_soc_pin_info, + int pins_cnt) +{ + struct sprd_pinctrl_soc_info *info = sprd_pctl->info; + unsigned int ctrl_pin = 0, com_pin = 0; + struct sprd_pin *pin; + int i; + + info->npins = pins_cnt; + info->pins = devm_kzalloc(sprd_pctl->dev, + info->npins * sizeof(struct sprd_pin), + GFP_KERNEL); + if (!info->pins) + return -ENOMEM; + + for (i = 0, pin = info->pins; i < info->npins; i++, pin++) { + unsigned int reg; + + pin->name = sprd_soc_pin_info[i].name; + pin->type = sprd_soc_pin_info[i].type; + pin->number = sprd_soc_pin_info[i].num; + reg = sprd_soc_pin_info[i].reg; + if (pin->type == GLOBAL_CTRL_PIN) { + pin->reg = (unsigned long)sprd_pctl->base + + PINCTRL_REG_LEN * reg; + pin->bit_offset = sprd_soc_pin_info[i].bit_offset; + pin->bit_width = sprd_soc_pin_info[i].bit_width; + ctrl_pin++; + } else if (pin->type == COMMON_PIN) { + pin->reg = (unsigned long)sprd_pctl->base + + PINCTRL_REG_OFFSET + PINCTRL_REG_LEN * + (i - ctrl_pin); + com_pin++; + } else if (pin->type == MISC_PIN) { + pin->reg = (unsigned long)sprd_pctl->base + + PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN * + (i - ctrl_pin - com_pin); + } + } + + for (i = 0, pin = info->pins; i < info->npins; pin++, i++) { + dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, " + "bit offset = %ld, bit width = %ld, reg = 0x%lx\n", + pin->name, pin->number, pin->type, + pin->bit_offset, pin->bit_width, pin->reg); + } + + return 0; +} + +int sprd_pinctrl_core_probe(struct platform_device *pdev, + struct sprd_pins_info *sprd_soc_pin_info, + int pins_cnt) +{ + struct sprd_pinctrl *sprd_pctl; + struct sprd_pinctrl_soc_info *pinctrl_info; + struct pinctrl_pin_desc *pin_desc; + struct resource *res; + int ret, i; + + sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl), + GFP_KERNEL); + if (!sprd_pctl) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sprd_pctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sprd_pctl->base)) + return PTR_ERR(sprd_pctl->base); + + pinctrl_info = devm_kzalloc(&pdev->dev, + sizeof(struct sprd_pinctrl_soc_info), + GFP_KERNEL); + if (!pinctrl_info) + return -ENOMEM; + + sprd_pctl->info = pinctrl_info; + sprd_pctl->dev = &pdev->dev; + platform_set_drvdata(pdev, sprd_pctl); + + ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt); + if (ret) { + dev_err(&pdev->dev, "fail to add pins information\n"); + return ret; + } + + pin_desc = devm_kzalloc(&pdev->dev, pinctrl_info->npins * + sizeof(struct pinctrl_pin_desc), + GFP_KERNEL); + if (!pin_desc) + return -ENOMEM; + + for (i = 0; i < pinctrl_info->npins; i++) { + pin_desc[i].number = pinctrl_info->pins[i].number; + pin_desc[i].name = pinctrl_info->pins[i].name; + pin_desc[i].drv_data = pinctrl_info; + } + + sprd_pinctrl_desc.pins = pin_desc; + sprd_pinctrl_desc.name = dev_name(&pdev->dev); + sprd_pinctrl_desc.npins = pinctrl_info->npins; + + sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc, + &pdev->dev, (void *)sprd_pctl); + if (IS_ERR(sprd_pctl->pctl)) { + dev_err(&pdev->dev, "could not register pinctrl driver\n"); + return PTR_ERR(sprd_pctl->pctl); + } + + ret = sprd_pinctrl_parse_dt(sprd_pctl); + if (ret) { + dev_err(&pdev->dev, "fail to parse dt properties\n"); + pinctrl_unregister(sprd_pctl->pctl); + return ret; + } + + return 0; +} + +int sprd_pinctrl_remove(struct platform_device *pdev) +{ + struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev); + + pinctrl_unregister(sprd_pctl->pctl); + return 0; +} + +void sprd_pinctrl_shutdown(struct platform_device *pdev) +{ + struct pinctrl *pinctl = devm_pinctrl_get(&pdev->dev); + struct pinctrl_state *state; + + state = pinctrl_lookup_state(pinctl, "shutdown"); + if (!IS_ERR(state)) + pinctrl_select_state(pinctl, state); +} + +MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver"); +MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h new file mode 100644 index 000000000000..31a43fec38c4 --- /dev/null +++ b/drivers/pinctrl/sprd/pinctrl-sprd.h @@ -0,0 +1,67 @@ +/* + * Driver header file for pin controller driver + * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef __PINCTRL_SPRD_H__ +#define __PINCTRL_SPRD_H__ + +struct platform_device; + +#define NUM_OFFSET (20) +#define TYPE_OFFSET (16) +#define BIT_OFFSET (8) +#define WIDTH_OFFSET (4) + +#define SPRD_PIN_INFO(num, type, offset, width, reg) \ + (((num) & 0xFFF) << NUM_OFFSET | \ + ((type) & 0xF) << TYPE_OFFSET | \ + ((offset) & 0xFF) << BIT_OFFSET | \ + ((width) & 0xF) << WIDTH_OFFSET | \ + ((reg) & 0xF)) + +#define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin) + +#define SPRD_PINCTRL_PIN_DATA(a, b) \ + { \ + .name = b, \ + .num = (((a) >> NUM_OFFSET) & 0xfff), \ + .type = (((a) >> TYPE_OFFSET) & 0xf), \ + .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \ + .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \ + .reg = ((a) & 0xf) \ + } + +enum pin_type { + GLOBAL_CTRL_PIN, + COMMON_PIN, + MISC_PIN, +}; + +struct sprd_pins_info { + const char *name; + unsigned int num; + enum pin_type type; + + /* for global control pins configuration */ + unsigned long bit_offset; + unsigned long bit_width; + unsigned int reg; +}; + +int sprd_pinctrl_core_probe(struct platform_device *pdev, + struct sprd_pins_info *sprd_soc_pin_info, + int pins_cnt); +int sprd_pinctrl_remove(struct platform_device *pdev); +void sprd_pinctrl_shutdown(struct platform_device *pdev); + +#endif /* __PINCTRL_SPRD_H__ */ diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 06431ff49ffb..50299ad96659 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -952,7 +952,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, int npins = STM32_GPIO_PINS_PER_BANK; int bank_nr, err; - rstc = of_reset_control_get(np, NULL); + rstc = of_reset_control_get_exclusive(np, NULL); if (!IS_ERR(rstc)) reset_control_deassert(rstc); diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 31f85ca92669..bfce99d86dfc 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -7,7 +7,7 @@ config PINCTRL_SUNXI select GPIOLIB config PINCTRL_SUN4I_A10 - def_bool MACH_SUN4I || MACH_SUN7I + def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN5I diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index 47a392bc73c8..f763d8d62d6e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ SUNXI_FUNCTION(0x4, "uart2"), /* RTS */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ SUNXI_FUNCTION(0x4, "uart2"), /* CTS */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ SUNXI_FUNCTION(0x4, "uart2"), /* TX */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ SUNXI_FUNCTION(0x4, "uart2"), /* RX */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ SUNXI_FUNCTION(0x3, "spi3"), /* CLK */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD0 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ SUNXI_FUNCTION(0x3, "spi3"), /* MISO */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXCK */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ERXERR */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* MCLK */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ SUNXI_FUNCTION(0x4, "uart1"), /* TX */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXDV */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ SUNXI_FUNCTION(0x4, "uart1"), /* RX */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDC */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -116,7 +129,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "uart6"), /* TX */ SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDIO */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -124,7 +138,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "uart6"), /* RX */ SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCTL / ETXEN */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -132,9 +147,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "uart7"), /* TX */ SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXCK */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* BCLK */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -142,9 +159,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "uart7"), /* RX */ SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCK / ECRS */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* LRCK */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -152,9 +171,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "can"), /* TX */ SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GCLKIN / ECOL */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DO */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -162,14 +183,18 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x3, "can"), /* RX */ SUNXI_FUNCTION(0x4, "uart1"), /* RING */ SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION_VARIANT(0x3, "pll_lock_dbg", + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -177,11 +202,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ + SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* TX */ + SUNXI_FUNCTION_VARIANT(0x2, "ir0", /* TX */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM1 */ + PINCTRL_SUN8I_R40), /* * The SPDIF block is not referenced at all in the A10 user * manual. However it is described in the code leaked and the @@ -205,7 +238,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -213,7 +247,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* BCLK */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* BCLK */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -221,7 +256,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* LRCK */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* LRCK */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -229,7 +265,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO0 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO0 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x3, "ac97")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -237,31 +274,41 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), + SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM6 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), + SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM7 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x3, "ac97"), /* DI */ /* Undocumented mux function on A10 - See SPDIF MCLK above */ - SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */ + SUNXI_FUNCTION_VARIANT(0x4, "spdif", /* SPDIF IN */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -299,16 +346,22 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ + SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM4 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ + SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM5 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /* TX */ - SUNXI_FUNCTION(0x3, "ir1")), /* TX */ + SUNXI_FUNCTION_VARIANT(0x3, "ir1", /* TX */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -341,7 +394,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ + SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */ + SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* DS */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -375,19 +430,27 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D4 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D5 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D6 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D7 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -427,7 +490,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ + SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* RST */ + PINCTRL_SUN8I_R40)), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -728,14 +793,18 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ + SUNXI_FUNCTION(0x5, "csi0"), /* D13 */ + SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT0 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ + SUNXI_FUNCTION(0x5, "csi0"), /* D14 */ + SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT1 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -805,7 +874,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD2 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart5"), /* TX */ - SUNXI_FUNCTION(0x5, "ms"), /* BS */ + SUNXI_FUNCTION_VARIANT(0x5, "ms", /* BS */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), @@ -815,7 +886,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD3 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart5"), /* RX */ - SUNXI_FUNCTION(0x5, "ms"), /* CLK */ + SUNXI_FUNCTION_VARIANT(0x5, "ms", /* CLK */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), @@ -825,9 +898,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD4 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD3 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ - SUNXI_FUNCTION(0x5, "ms"), /* D0 */ + SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D0 */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), @@ -837,9 +913,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD5 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD2 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ - SUNXI_FUNCTION(0x5, "ms"), /* D1 */ + SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D1 */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), @@ -849,9 +928,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD6 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD1 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ - SUNXI_FUNCTION(0x5, "ms"), /* D2 */ + SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D2 */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), @@ -861,9 +943,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD7 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD0 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ - SUNXI_FUNCTION(0x5, "ms"), /* D3 */ + SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D3 */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), @@ -892,7 +977,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD10 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD3 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ @@ -904,7 +990,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD11 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD2 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ @@ -916,7 +1003,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ SUNXI_FUNCTION(0x5, "sim"), /* DET */ SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ @@ -928,7 +1016,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD13 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD0 */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ @@ -940,7 +1029,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD14 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXCK */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ SUNXI_FUNCTION(0x5, "sim"), /* SCK */ SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ @@ -952,7 +1042,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD15 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXERR */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ SUNXI_FUNCTION(0x5, "sim"), /* SDA */ SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ @@ -964,7 +1055,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAOE */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXDV */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "can"), /* TX */ SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ @@ -975,7 +1067,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADREQ */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDC */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "can"), /* RX */ SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ @@ -986,7 +1079,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADACK */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDIO */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ @@ -997,7 +1091,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS0 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXEN */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ @@ -1008,7 +1103,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS1 */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXCK */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ @@ -1019,7 +1115,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIORDY */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECRS */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ @@ -1030,7 +1127,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOR */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECOL */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ @@ -1041,7 +1139,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOW */ PINCTRL_SUN4I_A10), SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXERR */ - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ @@ -1050,23 +1149,27 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SCK */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SCK */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */ SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */ - PINCTRL_SUN7I_A20)), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -1109,7 +1212,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ SUNXI_FUNCTION(0x3, "uart6"), /* TX */ SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a", - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -1117,7 +1221,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ SUNXI_FUNCTION(0x3, "uart6"), /* RX */ SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b", - PINCTRL_SUN7I_A20), + PINCTRL_SUN7I_A20 | + PINCTRL_SUN8I_R40), SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -1162,13 +1267,21 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ + SUNXI_FUNCTION_VARIANT(0x4, "hdmi", /* HSCL */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "pwm", /* PWM2 */ + PINCTRL_SUN8I_R40)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ + SUNXI_FUNCTION_VARIANT(0x4, "hdmi", /* HSDA */ + PINCTRL_SUN4I_A10 | + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "pwm", /* PWM3 */ + PINCTRL_SUN8I_R40)), }; static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { @@ -1195,6 +1308,10 @@ static const struct of_device_id sun4i_a10_pinctrl_match[] = { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)PINCTRL_SUN7I_A20 }, + { + .compatible = "allwinner,sun8i-r40-pinctrl", + .data = (void *)PINCTRL_SUN8I_R40 + }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c index ccf9419e9418..97b48336f84a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/of_irq.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-sunxi.h" @@ -530,17 +531,36 @@ static const struct sunxi_desc_pin sun50i_h5_pins[] = { SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ }; -static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { +static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = { .pins = sun50i_h5_pins, .npins = ARRAY_SIZE(sun50i_h5_pins), .irq_banks = 2, .irq_read_needs_mux = true }; +static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = { + .pins = sun50i_h5_pins, + .npins = ARRAY_SIZE(sun50i_h5_pins), + .irq_banks = 3, + .irq_read_needs_mux = true +}; + static int sun50i_h5_pinctrl_probe(struct platform_device *pdev) { - return sunxi_pinctrl_init(pdev, - &sun50i_h5_pinctrl_data); + switch (of_irq_count(pdev->dev.of_node)) { + case 2: + dev_warn(&pdev->dev, + "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n"); + dev_warn(&pdev->dev, + "Please update the device tree, otherwise PG bank IRQ won't work.\n"); + return sunxi_pinctrl_init(pdev, + &sun50i_h5_pinctrl_data_broken); + case 3: + return sunxi_pinctrl_init(pdev, + &sun50i_h5_pinctrl_data); + default: + return -EINVAL; + } } static const struct of_device_id sun50i_h5_pinctrl_match[] = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index a22bd88a1f03..49a1deb97bb7 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -25,12 +25,12 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ + SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ + SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -113,7 +113,7 @@ static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) struct reset_control *rstc; int ret; - rstc = devm_reset_control_get(&pdev->dev, NULL); + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) { dev_err(&pdev->dev, "Reset controller missing\n"); return PTR_ERR(rstc); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 2292e05a397b..67ee6f9b3b68 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -29,13 +29,13 @@ static const struct sunxi_desc_pin sun8i_a23_r_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ - SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ - SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -100,7 +100,7 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) struct reset_control *rstc; int ret; - rstc = devm_reset_control_get(&pdev->dev, NULL); + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) { dev_err(&pdev->dev, "Reset controller missing\n"); return PTR_ERR(rstc); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c index 686ec212120b..ebfd9a26628c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c @@ -20,12 +20,12 @@ static const struct sunxi_desc_pin sun8i_h3_r_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ + SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ + SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), SUNXI_FUNCTION(0x0, "gpio_in"), diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index c86d3c42a905..496ba34e1f5f 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { .pins = sun8i_v3s_pins, .npins = ARRAY_SIZE(sun8i_v3s_pins), .irq_banks = 2, + .irq_bank_base = 1, .irq_read_needs_mux = true }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 0dfd7fa66c48..52edf3b5988d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -564,7 +564,8 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, val = arg / 10 - 1; break; case PIN_CONFIG_BIAS_DISABLE: - continue; + val = 0; + break; case PIN_CONFIG_BIAS_PULL_UP: if (arg == 0) return -EINVAL; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index ebedc2d32411..9d653c24219c 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -901,7 +901,7 @@ int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev) if (IS_ERR(padctl->regs)) return PTR_ERR(padctl->regs); - padctl->rst = devm_reset_control_get(&pdev->dev, NULL); + padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(padctl->rst)) return PTR_ERR(padctl->rst); diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 362c50918c13..5c1b6325d80d 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -716,7 +716,7 @@ static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, } #endif -static struct pinctrl_ops ti_iodelay_pinctrl_ops = { +static const struct pinctrl_ops ti_iodelay_pinctrl_ops = { .get_groups_count = pinctrl_generic_get_group_count, .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, @@ -726,7 +726,7 @@ static struct pinctrl_ops ti_iodelay_pinctrl_ops = { .dt_node_to_map = ti_iodelay_dt_node_to_map, }; -static struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = { +static const struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = { .pin_config_group_get = ti_iodelay_pinconf_group_get, .pin_config_group_set = ti_iodelay_pinconf_group_set, #ifdef CONFIG_DEBUG_FS diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index e5826eaa7170..9f2a1c666def 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -40,4 +40,8 @@ config PINCTRL_UNIPHIER_LD20 bool "UniPhier LD20 SoC pinctrl driver" default ARM64 +config PINCTRL_UNIPHIER_PXS3 + bool "UniPhier PXs3 SoC pinctrl driver" + default ARM64 + endif diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index 9f4bc8aa6f68..d592ff77d60f 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o obj-$(CONFIG_PINCTRL_UNIPHIER_LD11) += pinctrl-uniphier-ld11.o obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o +obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3) += pinctrl-uniphier-pxs3.o diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 30dec0ee7f35..f9267fabe6b0 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <linux/export.h> +#include <linux/list.h> #include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/pinctrl/pinconf.h> @@ -33,13 +33,21 @@ #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00 -#define UNIPHIER_PINCTRL_IECTRL 0x1d00 +#define UNIPHIER_PINCTRL_IECTRL_BASE 0x1d00 + +struct uniphier_pinctrl_reg_region { + struct list_head node; + unsigned int base; + unsigned int nregs; + u32 vals[0]; +}; struct uniphier_pinctrl_priv { struct pinctrl_desc pctldesc; struct pinctrl_dev *pctldev; struct regmap *regmap; struct uniphier_pinctrl_socdata *socdata; + struct list_head reg_regions; }; static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev) @@ -139,10 +147,11 @@ static const struct pinctrl_ops uniphier_pctlops = { }; static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, - const struct pin_desc *desc, + unsigned int pin, enum pin_config_param param) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum uniphier_pin_pull_dir pull_dir = uniphier_pin_get_pull_dir(desc->drv_data); unsigned int pupdctrl, reg, shift, val; @@ -189,10 +198,10 @@ static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev, } static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, - const struct pin_desc *desc, - u16 *strength) + unsigned int pin, u32 *strength) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum uniphier_pin_drv_type type = uniphier_pin_get_drv_type(desc->drv_data); const unsigned int strength_1bit[] = {4, 8}; @@ -249,46 +258,52 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, } static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev, - const struct pin_desc *desc) + unsigned int pin) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); - unsigned int val; + unsigned int reg, mask, val; int ret; if (iectrl == UNIPHIER_PIN_IECTRL_NONE) /* This pin is always input-enabled. */ return 0; - ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val); + if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) + iectrl = pin; + + reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; + mask = BIT(iectrl % 32); + + ret = regmap_read(priv->regmap, reg, &val); if (ret) return ret; - return val & BIT(iectrl) ? 0 : -EINVAL; + return val & mask ? 0 : -EINVAL; } static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs) { - const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum pin_config_param param = pinconf_to_config_param(*configs); bool has_arg = false; - u16 arg; + u32 arg; int ret; switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - ret = uniphier_conf_pin_bias_get(pctldev, desc, param); + ret = uniphier_conf_pin_bias_get(pctldev, pin, param); break; case PIN_CONFIG_DRIVE_STRENGTH: - ret = uniphier_conf_pin_drive_get(pctldev, desc, &arg); + ret = uniphier_conf_pin_drive_get(pctldev, pin, &arg); has_arg = true; break; case PIN_CONFIG_INPUT_ENABLE: - ret = uniphier_conf_pin_input_enable_get(pctldev, desc); + ret = uniphier_conf_pin_input_enable_get(pctldev, pin); break; default: /* unsupported parameter */ @@ -303,10 +318,11 @@ static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev, } static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev, - const struct pin_desc *desc, + unsigned int pin, enum pin_config_param param, u32 arg) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum uniphier_pin_pull_dir pull_dir = uniphier_pin_get_pull_dir(desc->drv_data); unsigned int pupdctrl, reg, shift; @@ -377,10 +393,10 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev, } static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, - const struct pin_desc *desc, - u16 strength) + unsigned int pin, u32 strength) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum uniphier_pin_drv_type type = uniphier_pin_get_drv_type(desc->drv_data); const unsigned int strength_1bit[] = {4, 8, -1}; @@ -438,10 +454,10 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, } static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, - const struct pin_desc *desc, - u16 enable) + unsigned int pin, u32 enable) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); + const struct pin_desc *desc = pin_desc_get(pctldev, pin); unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data); unsigned int reg, mask; @@ -457,7 +473,10 @@ static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev, if (iectrl == UNIPHIER_PIN_IECTRL_NONE) return enable ? 0 : -EINVAL; - reg = UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4; + if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) + iectrl = pin; + + reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; mask = BIT(iectrl % 32); return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); @@ -468,7 +487,6 @@ static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, unsigned long *configs, unsigned num_configs) { - const struct pin_desc *desc = pin_desc_get(pctldev, pin); int i, ret; for (i = 0; i < num_configs; i++) { @@ -481,15 +499,14 @@ static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: - ret = uniphier_conf_pin_bias_set(pctldev, desc, + ret = uniphier_conf_pin_bias_set(pctldev, pin, param, arg); break; case PIN_CONFIG_DRIVE_STRENGTH: - ret = uniphier_conf_pin_drive_set(pctldev, desc, arg); + ret = uniphier_conf_pin_drive_set(pctldev, pin, arg); break; case PIN_CONFIG_INPUT_ENABLE: - ret = uniphier_conf_pin_input_enable(pctldev, desc, - arg); + ret = uniphier_conf_pin_input_enable(pctldev, pin, arg); break; default: dev_err(pctldev->dev, @@ -569,8 +586,7 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, int ret; /* some pins need input-enabling */ - ret = uniphier_conf_pin_input_enable(pctldev, - pin_desc_get(pctldev, pin), 1); + ret = uniphier_conf_pin_input_enable(pctldev, pin, 1); if (ret) return ret; @@ -649,30 +665,27 @@ static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, unsigned offset) { struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev); - const struct uniphier_pinctrl_group *groups = priv->socdata->groups; - int groups_count = priv->socdata->groups_count; - enum uniphier_pinmux_gpio_range_type range_type; - int i, j; - - if (strstr(range->name, "irq")) - range_type = UNIPHIER_PINMUX_GPIO_RANGE_IRQ; - else - range_type = UNIPHIER_PINMUX_GPIO_RANGE_PORT; - - for (i = 0; i < groups_count; i++) { - if (groups[i].range_type != range_type) - continue; - - for (j = 0; j < groups[i].num_pins; j++) - if (groups[i].pins[j] == offset) - goto found; + unsigned int gpio_offset; + int muxval, i; + + if (range->pins) { + for (i = 0; i < range->npins; i++) + if (range->pins[i] == offset) + break; + + if (WARN_ON(i == range->npins)) + return -EINVAL; + + gpio_offset = i; + } else { + gpio_offset = offset - range->pin_base; } - dev_err(pctldev->dev, "pin %u does not support GPIO\n", offset); - return -EINVAL; + gpio_offset += range->id; + + muxval = priv->socdata->get_gpio_muxval(offset, gpio_offset); -found: - return uniphier_pmx_set_one_mux(pctldev, offset, groups[i].muxvals[j]); + return uniphier_pmx_set_one_mux(pctldev, offset, muxval); } static const struct pinmux_ops uniphier_pmxops = { @@ -684,12 +697,177 @@ static const struct pinmux_ops uniphier_pmxops = { .strict = true, }; +#ifdef CONFIG_PM_SLEEP +static int uniphier_pinctrl_suspend(struct device *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev); + struct uniphier_pinctrl_reg_region *r; + int ret; + + list_for_each_entry(r, &priv->reg_regions, node) { + ret = regmap_bulk_read(priv->regmap, r->base, r->vals, + r->nregs); + if (ret) + return ret; + } + + return 0; +} + +static int uniphier_pinctrl_resume(struct device *dev) +{ + struct uniphier_pinctrl_priv *priv = dev_get_drvdata(dev); + struct uniphier_pinctrl_reg_region *r; + int ret; + + list_for_each_entry(r, &priv->reg_regions, node) { + ret = regmap_bulk_write(priv->regmap, r->base, r->vals, + r->nregs); + if (ret) + return ret; + } + + if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { + ret = regmap_write(priv->regmap, + UNIPHIER_PINCTRL_LOAD_PINMUX, 1); + if (ret) + return ret; + } + + return 0; +} + +static int uniphier_pinctrl_add_reg_region(struct device *dev, + struct uniphier_pinctrl_priv *priv, + unsigned int base, + unsigned int count, + unsigned int width) +{ + struct uniphier_pinctrl_reg_region *region; + unsigned int nregs; + + if (!count) + return 0; + + nregs = DIV_ROUND_UP(count * width, 32); + + region = devm_kzalloc(dev, + sizeof(*region) + sizeof(region->vals[0]) * nregs, + GFP_KERNEL); + if (!region) + return -ENOMEM; + + region->base = base; + region->nregs = nregs; + + list_add_tail(®ion->node, &priv->reg_regions); + + return 0; +} +#endif + +static int uniphier_pinctrl_pm_init(struct device *dev, + struct uniphier_pinctrl_priv *priv) +{ +#ifdef CONFIG_PM_SLEEP + const struct uniphier_pinctrl_socdata *socdata = priv->socdata; + unsigned int num_drvctrl = 0; + unsigned int num_drv2ctrl = 0; + unsigned int num_drv3ctrl = 0; + unsigned int num_pupdctrl = 0; + unsigned int num_iectrl = 0; + unsigned int iectrl, drvctrl, pupdctrl; + enum uniphier_pin_drv_type drv_type; + enum uniphier_pin_pull_dir pull_dir; + int i, ret; + + for (i = 0; i < socdata->npins; i++) { + void *drv_data = socdata->pins[i].drv_data; + + drvctrl = uniphier_pin_get_drvctrl(drv_data); + drv_type = uniphier_pin_get_drv_type(drv_data); + pupdctrl = uniphier_pin_get_pupdctrl(drv_data); + pull_dir = uniphier_pin_get_pull_dir(drv_data); + iectrl = uniphier_pin_get_iectrl(drv_data); + + switch (drv_type) { + case UNIPHIER_PIN_DRV_1BIT: + num_drvctrl = max(num_drvctrl, drvctrl + 1); + break; + case UNIPHIER_PIN_DRV_2BIT: + num_drv2ctrl = max(num_drv2ctrl, drvctrl + 1); + break; + case UNIPHIER_PIN_DRV_3BIT: + num_drv3ctrl = max(num_drv3ctrl, drvctrl + 1); + break; + default: + break; + } + + if (pull_dir == UNIPHIER_PIN_PULL_UP || + pull_dir == UNIPHIER_PIN_PULL_DOWN) + num_pupdctrl = max(num_pupdctrl, pupdctrl + 1); + + if (iectrl != UNIPHIER_PIN_IECTRL_NONE) { + if (socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) + iectrl = i; + num_iectrl = max(num_iectrl, iectrl + 1); + } + } + + INIT_LIST_HEAD(&priv->reg_regions); + + ret = uniphier_pinctrl_add_reg_region(dev, priv, + UNIPHIER_PINCTRL_PINMUX_BASE, + socdata->npins, 8); + if (ret) + return ret; + + ret = uniphier_pinctrl_add_reg_region(dev, priv, + UNIPHIER_PINCTRL_DRVCTRL_BASE, + num_drvctrl, 1); + if (ret) + return ret; + + ret = uniphier_pinctrl_add_reg_region(dev, priv, + UNIPHIER_PINCTRL_DRV2CTRL_BASE, + num_drv2ctrl, 2); + if (ret) + return ret; + + ret = uniphier_pinctrl_add_reg_region(dev, priv, + UNIPHIER_PINCTRL_DRV3CTRL_BASE, + num_drv3ctrl, 3); + if (ret) + return ret; + + ret = uniphier_pinctrl_add_reg_region(dev, priv, + UNIPHIER_PINCTRL_PUPDCTRL_BASE, + num_pupdctrl, 1); + if (ret) + return ret; + + ret = uniphier_pinctrl_add_reg_region(dev, priv, + UNIPHIER_PINCTRL_IECTRL_BASE, + num_iectrl, 1); + if (ret) + return ret; +#endif + return 0; +} + +const struct dev_pm_ops uniphier_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_pinctrl_suspend, + uniphier_pinctrl_resume) +}; + int uniphier_pinctrl_probe(struct platform_device *pdev, struct uniphier_pinctrl_socdata *socdata) { struct device *dev = &pdev->dev; struct uniphier_pinctrl_priv *priv; struct device_node *parent; + int ret; if (!socdata || !socdata->pins || !socdata->npins || @@ -721,6 +899,10 @@ int uniphier_pinctrl_probe(struct platform_device *pdev, priv->pctldesc.confops = &uniphier_confops; priv->pctldesc.owner = dev->driver->owner; + ret = uniphier_pinctrl_pm_init(dev, priv); + if (ret) + return ret; + priv->pctldev = devm_pinctrl_register(dev, &priv->pctldesc, priv); if (IS_ERR(priv->pctldev)) { dev_err(dev, "failed to register UniPhier pinctrl driver\n"); @@ -731,4 +913,3 @@ int uniphier_pinctrl_probe(struct platform_device *pdev, return 0; } -EXPORT_SYMBOL_GPL(uniphier_pinctrl_probe); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index ad73db8d067b..9c5e359a63de 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -21,7 +21,7 @@ #include "pinctrl-uniphier.h" static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { - UNIPHIER_PINCTRL_PIN(0, "XECS1", 0, + UNIPHIER_PINCTRL_PIN(0, "XECS1", UNIPHIER_PIN_IECTRL_EXIST, 0, UNIPHIER_PIN_DRV_1BIT, 0, UNIPHIER_PIN_PULL_UP), UNIPHIER_PINCTRL_PIN(1, "ERXW", UNIPHIER_PIN_IECTRL_NONE, @@ -30,13 +30,13 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { UNIPHIER_PINCTRL_PIN(2, "XERWE1", UNIPHIER_PIN_IECTRL_NONE, 2, UNIPHIER_PIN_DRV_1BIT, 2, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(3, "XNFWP", 3, + UNIPHIER_PINCTRL_PIN(3, "XNFWP", UNIPHIER_PIN_IECTRL_EXIST, 3, UNIPHIER_PIN_DRV_1BIT, 3, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(4, "XNFCE0", 4, + UNIPHIER_PINCTRL_PIN(4, "XNFCE0", UNIPHIER_PIN_IECTRL_EXIST, 4, UNIPHIER_PIN_DRV_1BIT, 4, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(5, "NFRYBY0", 5, + UNIPHIER_PINCTRL_PIN(5, "NFRYBY0", UNIPHIER_PIN_IECTRL_EXIST, 5, UNIPHIER_PIN_DRV_1BIT, 5, UNIPHIER_PIN_PULL_UP), UNIPHIER_PINCTRL_PIN(6, "XNFRE", UNIPHIER_PIN_IECTRL_NONE, @@ -51,425 +51,427 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { UNIPHIER_PINCTRL_PIN(9, "NFCLE", UNIPHIER_PIN_IECTRL_NONE, 9, UNIPHIER_PIN_DRV_1BIT, 9, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(10, "NFD0", 10, + UNIPHIER_PINCTRL_PIN(10, "NFD0", UNIPHIER_PIN_IECTRL_EXIST, 10, UNIPHIER_PIN_DRV_1BIT, 10, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(11, "NFD1", 11, + UNIPHIER_PINCTRL_PIN(11, "NFD1", UNIPHIER_PIN_IECTRL_EXIST, 11, UNIPHIER_PIN_DRV_1BIT, 11, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(12, "NFD2", 12, + UNIPHIER_PINCTRL_PIN(12, "NFD2", UNIPHIER_PIN_IECTRL_EXIST, 12, UNIPHIER_PIN_DRV_1BIT, 12, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(13, "NFD3", 13, + UNIPHIER_PINCTRL_PIN(13, "NFD3", UNIPHIER_PIN_IECTRL_EXIST, 13, UNIPHIER_PIN_DRV_1BIT, 13, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(14, "NFD4", 14, + UNIPHIER_PINCTRL_PIN(14, "NFD4", UNIPHIER_PIN_IECTRL_EXIST, 14, UNIPHIER_PIN_DRV_1BIT, 14, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(15, "NFD5", 15, + UNIPHIER_PINCTRL_PIN(15, "NFD5", UNIPHIER_PIN_IECTRL_EXIST, 15, UNIPHIER_PIN_DRV_1BIT, 15, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(16, "NFD6", 16, + UNIPHIER_PINCTRL_PIN(16, "NFD6", UNIPHIER_PIN_IECTRL_EXIST, 16, UNIPHIER_PIN_DRV_1BIT, 16, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(17, "NFD7", 17, + UNIPHIER_PINCTRL_PIN(17, "NFD7", UNIPHIER_PIN_IECTRL_EXIST, 17, UNIPHIER_PIN_DRV_1BIT, 17, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(18, "XERST", 18, + UNIPHIER_PINCTRL_PIN(18, "XERST", UNIPHIER_PIN_IECTRL_EXIST, 0, UNIPHIER_PIN_DRV_2BIT, 18, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(19, "MMCCLK", 19, + UNIPHIER_PINCTRL_PIN(19, "MMCCLK", UNIPHIER_PIN_IECTRL_EXIST, 1, UNIPHIER_PIN_DRV_2BIT, 19, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(20, "MMCCMD", 20, + UNIPHIER_PINCTRL_PIN(20, "MMCCMD", UNIPHIER_PIN_IECTRL_EXIST, 2, UNIPHIER_PIN_DRV_2BIT, 20, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(21, "MMCDS", 21, + UNIPHIER_PINCTRL_PIN(21, "MMCDS", UNIPHIER_PIN_IECTRL_EXIST, 3, UNIPHIER_PIN_DRV_2BIT, 21, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(22, "MMCDAT0", 22, + UNIPHIER_PINCTRL_PIN(22, "MMCDAT0", UNIPHIER_PIN_IECTRL_EXIST, 4, UNIPHIER_PIN_DRV_2BIT, 22, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(23, "MMCDAT1", 23, + UNIPHIER_PINCTRL_PIN(23, "MMCDAT1", UNIPHIER_PIN_IECTRL_EXIST, 5, UNIPHIER_PIN_DRV_2BIT, 23, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(24, "MMCDAT2", 24, + UNIPHIER_PINCTRL_PIN(24, "MMCDAT2", UNIPHIER_PIN_IECTRL_EXIST, 6, UNIPHIER_PIN_DRV_2BIT, 24, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(25, "MMCDAT3", 25, + UNIPHIER_PINCTRL_PIN(25, "MMCDAT3", UNIPHIER_PIN_IECTRL_EXIST, 7, UNIPHIER_PIN_DRV_2BIT, 25, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(26, "MMCDAT4", 26, + UNIPHIER_PINCTRL_PIN(26, "MMCDAT4", UNIPHIER_PIN_IECTRL_EXIST, 8, UNIPHIER_PIN_DRV_2BIT, 26, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(27, "MMCDAT5", 27, + UNIPHIER_PINCTRL_PIN(27, "MMCDAT5", UNIPHIER_PIN_IECTRL_EXIST, 9, UNIPHIER_PIN_DRV_2BIT, 27, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(28, "MMCDAT6", 28, + UNIPHIER_PINCTRL_PIN(28, "MMCDAT6", UNIPHIER_PIN_IECTRL_EXIST, 10, UNIPHIER_PIN_DRV_2BIT, 28, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(29, "MMCDAT7", 29, + UNIPHIER_PINCTRL_PIN(29, "MMCDAT7", UNIPHIER_PIN_IECTRL_EXIST, 11, UNIPHIER_PIN_DRV_2BIT, 29, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(46, "USB0VBUS", 46, + UNIPHIER_PINCTRL_PIN(46, "USB0VBUS", UNIPHIER_PIN_IECTRL_EXIST, 46, UNIPHIER_PIN_DRV_1BIT, 46, UNIPHIER_PIN_PULL_DOWN), UNIPHIER_PINCTRL_PIN(47, "USB0OD", UNIPHIER_PIN_IECTRL_NONE, 47, UNIPHIER_PIN_DRV_1BIT, 47, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(48, "USB1VBUS", 48, + UNIPHIER_PINCTRL_PIN(48, "USB1VBUS", UNIPHIER_PIN_IECTRL_EXIST, 48, UNIPHIER_PIN_DRV_1BIT, 48, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(49, "USB1OD", 49, + UNIPHIER_PINCTRL_PIN(49, "USB1OD", UNIPHIER_PIN_IECTRL_EXIST, 49, UNIPHIER_PIN_DRV_1BIT, 49, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(50, "USB2VBUS", 50, + UNIPHIER_PINCTRL_PIN(50, "USB2VBUS", UNIPHIER_PIN_IECTRL_EXIST, 50, UNIPHIER_PIN_DRV_1BIT, 50, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(51, "USB2OD", 51, + UNIPHIER_PINCTRL_PIN(51, "USB2OD", UNIPHIER_PIN_IECTRL_EXIST, 51, UNIPHIER_PIN_DRV_1BIT, 51, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(54, "TXD0", 54, + UNIPHIER_PINCTRL_PIN(54, "TXD0", UNIPHIER_PIN_IECTRL_EXIST, 54, UNIPHIER_PIN_DRV_1BIT, 54, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(55, "RXD0", 55, + UNIPHIER_PINCTRL_PIN(55, "RXD0", UNIPHIER_PIN_IECTRL_EXIST, 55, UNIPHIER_PIN_DRV_1BIT, 55, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(56, "SPISYNC0", 56, + UNIPHIER_PINCTRL_PIN(56, "SPISYNC0", UNIPHIER_PIN_IECTRL_EXIST, 56, UNIPHIER_PIN_DRV_1BIT, 56, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(57, "SPISCLK0", 57, + UNIPHIER_PINCTRL_PIN(57, "SPISCLK0", UNIPHIER_PIN_IECTRL_EXIST, 57, UNIPHIER_PIN_DRV_1BIT, 57, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(58, "SPITXD0", 58, + UNIPHIER_PINCTRL_PIN(58, "SPITXD0", UNIPHIER_PIN_IECTRL_EXIST, 58, UNIPHIER_PIN_DRV_1BIT, 58, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(59, "SPIRXD0", 59, + UNIPHIER_PINCTRL_PIN(59, "SPIRXD0", UNIPHIER_PIN_IECTRL_EXIST, 59, UNIPHIER_PIN_DRV_1BIT, 59, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(60, "AGCI", 60, + UNIPHIER_PINCTRL_PIN(60, "AGCI", UNIPHIER_PIN_IECTRL_EXIST, 60, UNIPHIER_PIN_DRV_1BIT, 60, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(61, "DMDSDA0", 61, + UNIPHIER_PINCTRL_PIN(61, "DMDSDA0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(62, "DMDSCL0", 62, + UNIPHIER_PINCTRL_PIN(62, "DMDSCL0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(63, "SDA0", 63, + UNIPHIER_PINCTRL_PIN(63, "SDA0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(64, "SCL0", 64, + UNIPHIER_PINCTRL_PIN(64, "SCL0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(65, "SDA1", 65, + UNIPHIER_PINCTRL_PIN(65, "SDA1", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(66, "SCL1", 66, + UNIPHIER_PINCTRL_PIN(66, "SCL1", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(67, "HIN", 67, + UNIPHIER_PINCTRL_PIN(67, "HIN", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED5, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(68, "VIN", 68, + UNIPHIER_PINCTRL_PIN(68, "VIN", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED5, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(69, "PCA00", 69, + UNIPHIER_PINCTRL_PIN(69, "PCA00", UNIPHIER_PIN_IECTRL_EXIST, 69, UNIPHIER_PIN_DRV_1BIT, 69, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(70, "PCA01", 70, + UNIPHIER_PINCTRL_PIN(70, "PCA01", UNIPHIER_PIN_IECTRL_EXIST, 70, UNIPHIER_PIN_DRV_1BIT, 70, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(71, "PCA02", 71, + UNIPHIER_PINCTRL_PIN(71, "PCA02", UNIPHIER_PIN_IECTRL_EXIST, 71, UNIPHIER_PIN_DRV_1BIT, 71, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(72, "PCA03", 72, + UNIPHIER_PINCTRL_PIN(72, "PCA03", UNIPHIER_PIN_IECTRL_EXIST, 72, UNIPHIER_PIN_DRV_1BIT, 72, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(73, "PCA04", 73, + UNIPHIER_PINCTRL_PIN(73, "PCA04", UNIPHIER_PIN_IECTRL_EXIST, 73, UNIPHIER_PIN_DRV_1BIT, 73, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(74, "PCA05", 74, + UNIPHIER_PINCTRL_PIN(74, "PCA05", UNIPHIER_PIN_IECTRL_EXIST, 74, UNIPHIER_PIN_DRV_1BIT, 74, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(75, "PCA06", 75, + UNIPHIER_PINCTRL_PIN(75, "PCA06", UNIPHIER_PIN_IECTRL_EXIST, 75, UNIPHIER_PIN_DRV_1BIT, 75, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(76, "PCA07", 76, + UNIPHIER_PINCTRL_PIN(76, "PCA07", UNIPHIER_PIN_IECTRL_EXIST, 76, UNIPHIER_PIN_DRV_1BIT, 76, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(77, "PCA08", 77, + UNIPHIER_PINCTRL_PIN(77, "PCA08", UNIPHIER_PIN_IECTRL_EXIST, 77, UNIPHIER_PIN_DRV_1BIT, 77, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(78, "PCA09", 78, + UNIPHIER_PINCTRL_PIN(78, "PCA09", UNIPHIER_PIN_IECTRL_EXIST, 78, UNIPHIER_PIN_DRV_1BIT, 78, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(79, "PCA10", 79, + UNIPHIER_PINCTRL_PIN(79, "PCA10", UNIPHIER_PIN_IECTRL_EXIST, 79, UNIPHIER_PIN_DRV_1BIT, 79, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(80, "PCA11", 80, + UNIPHIER_PINCTRL_PIN(80, "PCA11", UNIPHIER_PIN_IECTRL_EXIST, 80, UNIPHIER_PIN_DRV_1BIT, 80, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(81, "PCA12", 81, + UNIPHIER_PINCTRL_PIN(81, "PCA12", UNIPHIER_PIN_IECTRL_EXIST, 81, UNIPHIER_PIN_DRV_1BIT, 81, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(82, "PCA13", 82, + UNIPHIER_PINCTRL_PIN(82, "PCA13", UNIPHIER_PIN_IECTRL_EXIST, 82, UNIPHIER_PIN_DRV_1BIT, 82, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(83, "PCA14", 83, + UNIPHIER_PINCTRL_PIN(83, "PCA14", UNIPHIER_PIN_IECTRL_EXIST, 83, UNIPHIER_PIN_DRV_1BIT, 83, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(84, "PC0READY", 84, + UNIPHIER_PINCTRL_PIN(84, "PC0READY", UNIPHIER_PIN_IECTRL_EXIST, 84, UNIPHIER_PIN_DRV_1BIT, 84, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(85, "PC0CD1", 85, + UNIPHIER_PINCTRL_PIN(85, "PC0CD1", UNIPHIER_PIN_IECTRL_EXIST, 85, UNIPHIER_PIN_DRV_1BIT, 85, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(86, "PC0CD2", 86, + UNIPHIER_PINCTRL_PIN(86, "PC0CD2", UNIPHIER_PIN_IECTRL_EXIST, 86, UNIPHIER_PIN_DRV_1BIT, 86, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(87, "PC0WAIT", 87, + UNIPHIER_PINCTRL_PIN(87, "PC0WAIT", UNIPHIER_PIN_IECTRL_EXIST, 87, UNIPHIER_PIN_DRV_1BIT, 87, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(88, "PC0RESET", 88, + UNIPHIER_PINCTRL_PIN(88, "PC0RESET", UNIPHIER_PIN_IECTRL_EXIST, 88, UNIPHIER_PIN_DRV_1BIT, 88, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(89, "PC0CE1", 89, + UNIPHIER_PINCTRL_PIN(89, "PC0CE1", UNIPHIER_PIN_IECTRL_EXIST, 89, UNIPHIER_PIN_DRV_1BIT, 89, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(90, "PC0WE", 90, + UNIPHIER_PINCTRL_PIN(90, "PC0WE", UNIPHIER_PIN_IECTRL_EXIST, 90, UNIPHIER_PIN_DRV_1BIT, 90, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(91, "PC0OE", 91, + UNIPHIER_PINCTRL_PIN(91, "PC0OE", UNIPHIER_PIN_IECTRL_EXIST, 91, UNIPHIER_PIN_DRV_1BIT, 91, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(92, "PC0IOWR", 92, + UNIPHIER_PINCTRL_PIN(92, "PC0IOWR", UNIPHIER_PIN_IECTRL_EXIST, 92, UNIPHIER_PIN_DRV_1BIT, 92, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(93, "PC0IORD", 93, + UNIPHIER_PINCTRL_PIN(93, "PC0IORD", UNIPHIER_PIN_IECTRL_EXIST, 93, UNIPHIER_PIN_DRV_1BIT, 93, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(94, "PCD00", 94, + UNIPHIER_PINCTRL_PIN(94, "PCD00", UNIPHIER_PIN_IECTRL_EXIST, 94, UNIPHIER_PIN_DRV_1BIT, 94, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(95, "PCD01", 95, + UNIPHIER_PINCTRL_PIN(95, "PCD01", UNIPHIER_PIN_IECTRL_EXIST, 95, UNIPHIER_PIN_DRV_1BIT, 95, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(96, "PCD02", 96, + UNIPHIER_PINCTRL_PIN(96, "PCD02", UNIPHIER_PIN_IECTRL_EXIST, 96, UNIPHIER_PIN_DRV_1BIT, 96, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(97, "PCD03", 97, + UNIPHIER_PINCTRL_PIN(97, "PCD03", UNIPHIER_PIN_IECTRL_EXIST, 97, UNIPHIER_PIN_DRV_1BIT, 97, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(98, "PCD04", 98, + UNIPHIER_PINCTRL_PIN(98, "PCD04", UNIPHIER_PIN_IECTRL_EXIST, 98, UNIPHIER_PIN_DRV_1BIT, 98, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(99, "PCD05", 99, + UNIPHIER_PINCTRL_PIN(99, "PCD05", UNIPHIER_PIN_IECTRL_EXIST, 99, UNIPHIER_PIN_DRV_1BIT, 99, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(100, "PCD06", 100, + UNIPHIER_PINCTRL_PIN(100, "PCD06", UNIPHIER_PIN_IECTRL_EXIST, 100, UNIPHIER_PIN_DRV_1BIT, 100, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(101, "PCD07", 101, + UNIPHIER_PINCTRL_PIN(101, "PCD07", UNIPHIER_PIN_IECTRL_EXIST, 101, UNIPHIER_PIN_DRV_1BIT, 101, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(102, "HS0BCLKIN", 102, + UNIPHIER_PINCTRL_PIN(102, "HS0BCLKIN", UNIPHIER_PIN_IECTRL_EXIST, 102, UNIPHIER_PIN_DRV_1BIT, 102, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(103, "HS0SYNCIN", 103, + UNIPHIER_PINCTRL_PIN(103, "HS0SYNCIN", UNIPHIER_PIN_IECTRL_EXIST, 103, UNIPHIER_PIN_DRV_1BIT, 103, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(104, "HS0VALIN", 104, + UNIPHIER_PINCTRL_PIN(104, "HS0VALIN", UNIPHIER_PIN_IECTRL_EXIST, 104, UNIPHIER_PIN_DRV_1BIT, 104, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(105, "HS0DIN0", 105, + UNIPHIER_PINCTRL_PIN(105, "HS0DIN0", UNIPHIER_PIN_IECTRL_EXIST, 105, UNIPHIER_PIN_DRV_1BIT, 105, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(106, "HS0DIN1", 106, + UNIPHIER_PINCTRL_PIN(106, "HS0DIN1", UNIPHIER_PIN_IECTRL_EXIST, 106, UNIPHIER_PIN_DRV_1BIT, 106, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(107, "HS0DIN2", 107, + UNIPHIER_PINCTRL_PIN(107, "HS0DIN2", UNIPHIER_PIN_IECTRL_EXIST, 107, UNIPHIER_PIN_DRV_1BIT, 107, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(108, "HS0DIN3", 108, + UNIPHIER_PINCTRL_PIN(108, "HS0DIN3", UNIPHIER_PIN_IECTRL_EXIST, 108, UNIPHIER_PIN_DRV_1BIT, 108, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(109, "HS0DIN4", 109, + UNIPHIER_PINCTRL_PIN(109, "HS0DIN4", UNIPHIER_PIN_IECTRL_EXIST, 109, UNIPHIER_PIN_DRV_1BIT, 109, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(110, "HS0DIN5", 110, + UNIPHIER_PINCTRL_PIN(110, "HS0DIN5", UNIPHIER_PIN_IECTRL_EXIST, 110, UNIPHIER_PIN_DRV_1BIT, 110, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(111, "HS0DIN6", 111, + UNIPHIER_PINCTRL_PIN(111, "HS0DIN6", UNIPHIER_PIN_IECTRL_EXIST, 111, UNIPHIER_PIN_DRV_1BIT, 111, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(112, "HS0DIN7", 112, + UNIPHIER_PINCTRL_PIN(112, "HS0DIN7", UNIPHIER_PIN_IECTRL_EXIST, 112, UNIPHIER_PIN_DRV_1BIT, 112, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(113, "HS0BCLKOUT", 113, + UNIPHIER_PINCTRL_PIN(113, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_EXIST, 113, UNIPHIER_PIN_DRV_1BIT, 113, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(114, "HS0SYNCOUT", 114, + UNIPHIER_PINCTRL_PIN(114, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_EXIST, 114, UNIPHIER_PIN_DRV_1BIT, 114, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(115, "HS0VALOUT", 115, + UNIPHIER_PINCTRL_PIN(115, "HS0VALOUT", UNIPHIER_PIN_IECTRL_EXIST, 115, UNIPHIER_PIN_DRV_1BIT, 115, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(116, "HS0DOUT0", 116, + UNIPHIER_PINCTRL_PIN(116, "HS0DOUT0", UNIPHIER_PIN_IECTRL_EXIST, 116, UNIPHIER_PIN_DRV_1BIT, 116, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(117, "HS0DOUT1", 117, + UNIPHIER_PINCTRL_PIN(117, "HS0DOUT1", UNIPHIER_PIN_IECTRL_EXIST, 117, UNIPHIER_PIN_DRV_1BIT, 117, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(118, "HS0DOUT2", 118, + UNIPHIER_PINCTRL_PIN(118, "HS0DOUT2", UNIPHIER_PIN_IECTRL_EXIST, 118, UNIPHIER_PIN_DRV_1BIT, 118, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(119, "HS0DOUT3", 119, + UNIPHIER_PINCTRL_PIN(119, "HS0DOUT3", UNIPHIER_PIN_IECTRL_EXIST, 119, UNIPHIER_PIN_DRV_1BIT, 119, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(120, "HS0DOUT4", 120, + UNIPHIER_PINCTRL_PIN(120, "HS0DOUT4", UNIPHIER_PIN_IECTRL_EXIST, 120, UNIPHIER_PIN_DRV_1BIT, 120, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(121, "HS0DOUT5", 121, + UNIPHIER_PINCTRL_PIN(121, "HS0DOUT5", UNIPHIER_PIN_IECTRL_EXIST, 121, UNIPHIER_PIN_DRV_1BIT, 121, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(122, "HS0DOUT6", 122, + UNIPHIER_PINCTRL_PIN(122, "HS0DOUT6", UNIPHIER_PIN_IECTRL_EXIST, 122, UNIPHIER_PIN_DRV_1BIT, 122, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(123, "HS0DOUT7", 123, + UNIPHIER_PINCTRL_PIN(123, "HS0DOUT7", UNIPHIER_PIN_IECTRL_EXIST, 123, UNIPHIER_PIN_DRV_1BIT, 123, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(124, "HS1BCLKIN", 124, + UNIPHIER_PINCTRL_PIN(124, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_EXIST, 124, UNIPHIER_PIN_DRV_1BIT, 124, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(125, "HS1SYNCIN", 125, + UNIPHIER_PINCTRL_PIN(125, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_EXIST, 125, UNIPHIER_PIN_DRV_1BIT, 125, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(126, "HS1VALIN", 126, + UNIPHIER_PINCTRL_PIN(126, "HS1VALIN", UNIPHIER_PIN_IECTRL_EXIST, 126, UNIPHIER_PIN_DRV_1BIT, 126, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(127, "HS1DIN0", 127, + UNIPHIER_PINCTRL_PIN(127, "HS1DIN0", UNIPHIER_PIN_IECTRL_EXIST, 127, UNIPHIER_PIN_DRV_1BIT, 127, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(128, "HS1DIN1", 128, + UNIPHIER_PINCTRL_PIN(128, "HS1DIN1", UNIPHIER_PIN_IECTRL_EXIST, 128, UNIPHIER_PIN_DRV_1BIT, 128, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(129, "HS1DIN2", 129, + UNIPHIER_PINCTRL_PIN(129, "HS1DIN2", UNIPHIER_PIN_IECTRL_EXIST, 129, UNIPHIER_PIN_DRV_1BIT, 129, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(130, "HS1DIN3", 130, + UNIPHIER_PINCTRL_PIN(130, "HS1DIN3", UNIPHIER_PIN_IECTRL_EXIST, 130, UNIPHIER_PIN_DRV_1BIT, 130, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(131, "HS1DIN4", 131, + UNIPHIER_PINCTRL_PIN(131, "HS1DIN4", UNIPHIER_PIN_IECTRL_EXIST, 131, UNIPHIER_PIN_DRV_1BIT, 131, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", 132, + UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", UNIPHIER_PIN_IECTRL_EXIST, 132, UNIPHIER_PIN_DRV_1BIT, 132, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(133, "HS1DIN6", 133, + UNIPHIER_PINCTRL_PIN(133, "HS1DIN6", UNIPHIER_PIN_IECTRL_EXIST, 133, UNIPHIER_PIN_DRV_1BIT, 133, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(134, "HS1DIN7", 134, + UNIPHIER_PINCTRL_PIN(134, "HS1DIN7", UNIPHIER_PIN_IECTRL_EXIST, 134, UNIPHIER_PIN_DRV_1BIT, 134, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(135, "AO1IEC", 135, + UNIPHIER_PINCTRL_PIN(135, "AO1IEC", UNIPHIER_PIN_IECTRL_EXIST, 135, UNIPHIER_PIN_DRV_1BIT, 135, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(136, "AO1ARC", 136, + UNIPHIER_PINCTRL_PIN(136, "AO1ARC", UNIPHIER_PIN_IECTRL_EXIST, 136, UNIPHIER_PIN_DRV_1BIT, 136, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(137, "AO1DACCK", 137, + UNIPHIER_PINCTRL_PIN(137, "AO1DACCK", UNIPHIER_PIN_IECTRL_EXIST, 137, UNIPHIER_PIN_DRV_1BIT, 137, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(138, "AO1BCK", 138, + UNIPHIER_PINCTRL_PIN(138, "AO1BCK", UNIPHIER_PIN_IECTRL_EXIST, 138, UNIPHIER_PIN_DRV_1BIT, 138, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(139, "AO1LRCK", 139, + UNIPHIER_PINCTRL_PIN(139, "AO1LRCK", UNIPHIER_PIN_IECTRL_EXIST, 139, UNIPHIER_PIN_DRV_1BIT, 139, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(140, "AO1D0", 140, + UNIPHIER_PINCTRL_PIN(140, "AO1D0", UNIPHIER_PIN_IECTRL_EXIST, 140, UNIPHIER_PIN_DRV_1BIT, 140, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(141, "AO1D1", 141, + UNIPHIER_PINCTRL_PIN(141, "AO1D1", UNIPHIER_PIN_IECTRL_EXIST, 141, UNIPHIER_PIN_DRV_1BIT, 141, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(142, "AO1D2", 142, + UNIPHIER_PINCTRL_PIN(142, "AO1D2", UNIPHIER_PIN_IECTRL_EXIST, 142, UNIPHIER_PIN_DRV_1BIT, 142, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(143, "XIRQ9", 143, + UNIPHIER_PINCTRL_PIN(143, "XIRQ9", UNIPHIER_PIN_IECTRL_EXIST, 143, UNIPHIER_PIN_DRV_1BIT, 143, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(144, "XIRQ10", 144, + UNIPHIER_PINCTRL_PIN(144, "XIRQ10", UNIPHIER_PIN_IECTRL_EXIST, 144, UNIPHIER_PIN_DRV_1BIT, 144, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(145, "XIRQ11", 145, + UNIPHIER_PINCTRL_PIN(145, "XIRQ11", UNIPHIER_PIN_IECTRL_EXIST, 145, UNIPHIER_PIN_DRV_1BIT, 145, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(146, "XIRQ13", 146, + UNIPHIER_PINCTRL_PIN(146, "XIRQ13", UNIPHIER_PIN_IECTRL_EXIST, 146, UNIPHIER_PIN_DRV_1BIT, 146, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(147, "PWMA", 147, + UNIPHIER_PINCTRL_PIN(147, "PWMA", UNIPHIER_PIN_IECTRL_EXIST, 147, UNIPHIER_PIN_DRV_1BIT, 147, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(148, "LR_GOUT", 148, + UNIPHIER_PINCTRL_PIN(148, "LR_GOUT", UNIPHIER_PIN_IECTRL_EXIST, 148, UNIPHIER_PIN_DRV_1BIT, 148, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(149, "XIRQ0", 149, + UNIPHIER_PINCTRL_PIN(149, "XIRQ0", UNIPHIER_PIN_IECTRL_EXIST, 149, UNIPHIER_PIN_DRV_1BIT, 149, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(150, "XIRQ1", 150, + UNIPHIER_PINCTRL_PIN(150, "XIRQ1", UNIPHIER_PIN_IECTRL_EXIST, 150, UNIPHIER_PIN_DRV_1BIT, 150, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(151, "XIRQ2", 151, + UNIPHIER_PINCTRL_PIN(151, "XIRQ2", UNIPHIER_PIN_IECTRL_EXIST, 151, UNIPHIER_PIN_DRV_1BIT, 151, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(152, "XIRQ3", 152, + UNIPHIER_PINCTRL_PIN(152, "XIRQ3", UNIPHIER_PIN_IECTRL_EXIST, 152, UNIPHIER_PIN_DRV_1BIT, 152, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(153, "XIRQ4", 153, + UNIPHIER_PINCTRL_PIN(153, "XIRQ4", UNIPHIER_PIN_IECTRL_EXIST, 153, UNIPHIER_PIN_DRV_1BIT, 153, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(154, "XIRQ5", 154, + UNIPHIER_PINCTRL_PIN(154, "XIRQ5", UNIPHIER_PIN_IECTRL_EXIST, 154, UNIPHIER_PIN_DRV_1BIT, 154, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(155, "XIRQ6", 155, + UNIPHIER_PINCTRL_PIN(155, "XIRQ6", UNIPHIER_PIN_IECTRL_EXIST, 155, UNIPHIER_PIN_DRV_1BIT, 155, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(156, "XIRQ7", 156, + UNIPHIER_PINCTRL_PIN(156, "XIRQ7", UNIPHIER_PIN_IECTRL_EXIST, 156, UNIPHIER_PIN_DRV_1BIT, 156, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(157, "XIRQ8", 157, + UNIPHIER_PINCTRL_PIN(157, "XIRQ8", UNIPHIER_PIN_IECTRL_EXIST, 157, UNIPHIER_PIN_DRV_1BIT, 157, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(158, "AGCBS", 158, + UNIPHIER_PINCTRL_PIN(158, "AGCBS", UNIPHIER_PIN_IECTRL_EXIST, 158, UNIPHIER_PIN_DRV_1BIT, 158, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(159, "XIRQ21", 159, + UNIPHIER_PINCTRL_PIN(159, "XIRQ21", UNIPHIER_PIN_IECTRL_EXIST, 159, UNIPHIER_PIN_DRV_1BIT, 159, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(160, "XIRQ22", 160, + UNIPHIER_PINCTRL_PIN(160, "XIRQ22", UNIPHIER_PIN_IECTRL_EXIST, 160, UNIPHIER_PIN_DRV_1BIT, 160, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(161, "XIRQ23", 161, + UNIPHIER_PINCTRL_PIN(161, "XIRQ23", UNIPHIER_PIN_IECTRL_EXIST, 161, UNIPHIER_PIN_DRV_1BIT, 161, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(162, "CH2CLK", 162, + UNIPHIER_PINCTRL_PIN(162, "CH2CLK", UNIPHIER_PIN_IECTRL_EXIST, 162, UNIPHIER_PIN_DRV_1BIT, 162, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(163, "CH2PSYNC", 163, + UNIPHIER_PINCTRL_PIN(163, "CH2PSYNC", UNIPHIER_PIN_IECTRL_EXIST, 163, UNIPHIER_PIN_DRV_1BIT, 163, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(164, "CH2VAL", 164, + UNIPHIER_PINCTRL_PIN(164, "CH2VAL", UNIPHIER_PIN_IECTRL_EXIST, 164, UNIPHIER_PIN_DRV_1BIT, 164, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(165, "CH2DATA", 165, + UNIPHIER_PINCTRL_PIN(165, "CH2DATA", UNIPHIER_PIN_IECTRL_EXIST, 165, UNIPHIER_PIN_DRV_1BIT, 165, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(166, "CK25O", 166, + UNIPHIER_PINCTRL_PIN(166, "CK25O", UNIPHIER_PIN_IECTRL_EXIST, 166, UNIPHIER_PIN_DRV_1BIT, 166, UNIPHIER_PIN_PULL_DOWN), }; +static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142}; +static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25}; static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29}; @@ -508,102 +510,44 @@ static const unsigned usb1_pins[] = {48, 49}; static const int usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {50, 51}; static const int usb2_muxvals[] = {0, 0}; -static const unsigned port_range0_pins[] = { +static const unsigned int gpio_range0_pins[] = { 159, 160, 161, 162, 163, 164, 165, 166, /* PORT0x */ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */ 16, 17, 18, /* PORT30-32 */ }; -static const int port_range0_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, /* PORT30-32 */ -}; -static const unsigned port_range1_pins[] = { +static const unsigned int gpio_range1_pins[] = { 46, 47, 48, 49, 50, /* PORT53-57 */ 51, /* PORT60 */ }; -static const int port_range1_muxvals[] = { - 15, 15, 15, 15, 15, /* PORT53-57 */ - 15, /* PORT60 */ -}; -static const unsigned port_range2_pins[] = { +static const unsigned int gpio_range2_pins[] = { 54, 55, 56, 57, 58, /* PORT63-67 */ 59, 60, 69, 70, 71, 72, 73, 74, /* PORT7x */ 75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */ 83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */ 91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */ }; -static const int port_range2_muxvals[] = { - 15, 15, 15, 15, 15, /* PORT63-67 */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ -}; -static const unsigned port_range3_pins[] = { +static const unsigned int gpio_range3_pins[] = { 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */ 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */ 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */ -}; -static const int port_range3_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ -}; -static const unsigned port_range4_pins[] = { + 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */ + 157, 143, 144, 145, 85, 146, 158, 84, /* XIRQ8-15 */ + 141, 142, 148, 50, 51, 159, 160, 161, /* XIRQ16-23 */ 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */ }; -static const int port_range4_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ -}; -static const unsigned port_range5_pins[] = { +static const unsigned int gpio_range4_pins[] = { 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */ 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */ 139, 140, 141, 142, /* PORT220-223 */ }; -static const int port_range5_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ - 15, 15, 15, 15, /* PORT220-223 */ -}; -static const unsigned port_range6_pins[] = { +static const unsigned int gpio_range5_pins[] = { 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */ 155, 156, 157, 143, 144, 145, 146, 158, /* PORT24x */ }; -static const int port_range6_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ -}; -static const unsigned xirq_pins[] = { - 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */ - 157, 143, 144, 145, 85, 146, 158, 84, /* XIRQ8-15 */ - 141, 142, 148, 50, 51, 159, 160, 161, /* XIRQ16-23 */ -}; -static const int xirq_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 13, 14, 14, 13, /* XIRQ8-15 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ -}; -static const unsigned xirq_alternatives_pins[] = { - 94, 95, 96, 97, 98, 99, 100, 101, /* XIRQ0-7 */ - 102, 103, 104, 105, 106, 107, /* XIRQ8-11,13,14 */ - 108, 109, 110, 111, 112, 113, 114, 115, /* XIRQ16-23 */ - 9, 10, 11, 12, 13, 14, 15, 16, /* XIRQ4-11 */ - 17, 0, 1, 2, 3, 4, 5, 6, 7, 8, /* XIRQ13,14,16-23 */ - 139, 140, 135, 147, /* XIRQ17,18,21,22 */ -}; -static const int xirq_alternatives_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 14, 14, /* XIRQ8-11,13,14 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ4-11 */ - 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ13,14,16-23 */ - 14, 14, 14, 14, /* XIRQ17,18,21,22 */ -}; static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { + UNIPHIER_PINCTRL_GROUP(aout), UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(ether_rmii), @@ -621,223 +565,15 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range4), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range5), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range6), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range1, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range1, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range1, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range1, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range2, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range2, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range2, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range2, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range2, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range2, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range2, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range2, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range2, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range2, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range2, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range2, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range2, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range2, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range2, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range2, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range2, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range2, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range2, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range2, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range2, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range2, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range2, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range2, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range2, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range2, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range2, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range2, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range2, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range2, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range2, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range2, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range2, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range2, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range2, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range2, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range2, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range3, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range3, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range3, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range3, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range3, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range3, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range3, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range3, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range3, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range3, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range3, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range3, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range3, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range3, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range3, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range3, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range3, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range3, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range3, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range3, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range3, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range3, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range3, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range3, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range4, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range4, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range4, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range4, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range4, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range4, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range4, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range4, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range5, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range5, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range5, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range5, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range5, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range5, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range5, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range5, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range5, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range5, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range5, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range5, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range5, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range5, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range5, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range5, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range5, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range5, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range5, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range5, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range6, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range6, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range6, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range6, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range6, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range6, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range6, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range6, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range6, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range6, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range6, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range6, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range6, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range6, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range6, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range6, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0b, xirq_alternatives, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1b, xirq_alternatives, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2b, xirq_alternatives, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5b, xirq_alternatives, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6b, xirq_alternatives, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7b, xirq_alternatives, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8b, xirq_alternatives, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9b, xirq_alternatives, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10b, xirq_alternatives, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11b, xirq_alternatives, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13b, xirq_alternatives, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21b, xirq_alternatives, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22b, xirq_alternatives, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23b, xirq_alternatives, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4c, xirq_alternatives, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5c, xirq_alternatives, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6c, xirq_alternatives, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7c, xirq_alternatives, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8c, xirq_alternatives, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9c, xirq_alternatives, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10c, xirq_alternatives, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11c, xirq_alternatives, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13c, xirq_alternatives, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14c, xirq_alternatives, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16c, xirq_alternatives, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19c, xirq_alternatives, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20c, xirq_alternatives, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21c, xirq_alternatives, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22c, xirq_alternatives, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23c, xirq_alternatives, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17d, xirq_alternatives, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18d, xirq_alternatives, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21d, xirq_alternatives, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22d, xirq_alternatives, 43), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range3), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range4), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5), }; +static const char * const aout_groups[] = {"aout"}; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; static const char * const ether_rmii_groups[] = {"ether_rmii"}; static const char * const i2c0_groups[] = {"i2c0"}; @@ -854,70 +590,9 @@ static const char * const uart3_groups[] = {"uart3"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", - /* port33-52 missing */ "port53", - "port54", "port55", "port56", "port57", - "port60", /* port61-62 missing*/ "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - /* port110-117 missing */ - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - /* port150-177 missing */ - "port180", "port181", "port182", "port183", - "port184", "port185", "port186", "port187", - /* port190-197 missing */ - "port200", "port201", "port202", "port203", - "port204", "port205", "port206", "port207", - "port210", "port211", "port212", "port213", - "port214", "port215", "port216", "port217", - "port220", "port221", "port222", "port223", - /* port224-227 missing */ - "port230", "port231", "port232", "port233", - "port234", "port235", "port236", "port237", - "port240", "port241", "port242", "port243", - "port244", "port245", "port246", "port247", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", "xirq13", "xirq14", "xirq15", - "xirq16", "xirq17", "xirq18", "xirq19", - "xirq20", "xirq21", "xirq22", "xirq23", - "xirq0b", "xirq1b", "xirq2b", "xirq3b", - "xirq4b", "xirq5b", "xirq6b", "xirq7b", - "xirq8b", "xirq9b", "xirq10b", "xirq11b", - /* none */ "xirq13b", "xirq14b", /* none */ - "xirq16b", "xirq17b", "xirq18b", "xirq19b", - "xirq20b", "xirq21b", "xirq22b", "xirq23b", - "xirq4c", "xirq5c", "xirq6c", "xirq7c", - "xirq8c", "xirq9c", "xirq10c", "xirq11c", - /* none */ "xirq13c", "xirq14c", /* none */ - "xirq16c", "xirq17c", "xirq18c", "xirq19c", - "xirq20c", "xirq21c", "xirq22c", "xirq23c", - "xirq17d", "xirq18d", "xirq21d", "xirq22d", -}; static const struct uniphier_pinmux_function uniphier_ld11_functions[] = { + UNIPHIER_PINMUX_FUNCTION(aout), UNIPHIER_PINMUX_FUNCTION(emmc), UNIPHIER_PINMUX_FUNCTION(ether_rmii), UNIPHIER_PINMUX_FUNCTION(i2c0), @@ -933,10 +608,20 @@ static const struct uniphier_pinmux_function uniphier_ld11_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_ld11_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset == 132 || gpio_offset == 135) /* XIRQ12, 15 */ + return 13; + + if (gpio_offset >= 120 && gpio_offset <= 143) /* XIRQx */ + return 14; + + return 15; +} + static struct uniphier_pinctrl_socdata uniphier_ld11_pindata = { .pins = uniphier_ld11_pins, .npins = ARRAY_SIZE(uniphier_ld11_pins), @@ -944,6 +629,7 @@ static struct uniphier_pinctrl_socdata uniphier_ld11_pindata = { .groups_count = ARRAY_SIZE(uniphier_ld11_groups), .functions = uniphier_ld11_functions, .functions_count = ARRAY_SIZE(uniphier_ld11_functions), + .get_gpio_muxval = uniphier_ld11_get_gpio_muxval, .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, }; @@ -962,6 +648,7 @@ static struct platform_driver uniphier_ld11_pinctrl_driver = { .driver = { .name = "uniphier-ld11-pinctrl", .of_match_table = uniphier_ld11_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_ld11_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 93006626028d..83341284dc44 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -21,536 +21,538 @@ #include "pinctrl-uniphier.h" static const struct pinctrl_pin_desc uniphier_ld20_pins[] = { - UNIPHIER_PINCTRL_PIN(0, "XECS1", 0, + UNIPHIER_PINCTRL_PIN(0, "XECS1", UNIPHIER_PIN_IECTRL_EXIST, 0, UNIPHIER_PIN_DRV_3BIT, 0, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(1, "ERXW", 1, + UNIPHIER_PINCTRL_PIN(1, "ERXW", UNIPHIER_PIN_IECTRL_EXIST, 1, UNIPHIER_PIN_DRV_3BIT, 1, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(2, "XERWE1", 2, + UNIPHIER_PINCTRL_PIN(2, "XERWE1", UNIPHIER_PIN_IECTRL_EXIST, 2, UNIPHIER_PIN_DRV_3BIT, 2, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(3, "XNFWP", 3, + UNIPHIER_PINCTRL_PIN(3, "XNFWP", UNIPHIER_PIN_IECTRL_EXIST, 3, UNIPHIER_PIN_DRV_3BIT, 3, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(4, "XNFCE0", 4, + UNIPHIER_PINCTRL_PIN(4, "XNFCE0", UNIPHIER_PIN_IECTRL_EXIST, 4, UNIPHIER_PIN_DRV_3BIT, 4, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(5, "NFRYBY0", 5, + UNIPHIER_PINCTRL_PIN(5, "NFRYBY0", UNIPHIER_PIN_IECTRL_EXIST, 5, UNIPHIER_PIN_DRV_3BIT, 5, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(6, "XNFRE", 6, + UNIPHIER_PINCTRL_PIN(6, "XNFRE", UNIPHIER_PIN_IECTRL_EXIST, 6, UNIPHIER_PIN_DRV_3BIT, 6, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(7, "XNFWE", 7, + UNIPHIER_PINCTRL_PIN(7, "XNFWE", UNIPHIER_PIN_IECTRL_EXIST, 7, UNIPHIER_PIN_DRV_3BIT, 7, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(8, "NFALE", 8, + UNIPHIER_PINCTRL_PIN(8, "NFALE", UNIPHIER_PIN_IECTRL_EXIST, 8, UNIPHIER_PIN_DRV_3BIT, 8, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(9, "NFCLE", 9, + UNIPHIER_PINCTRL_PIN(9, "NFCLE", UNIPHIER_PIN_IECTRL_EXIST, 9, UNIPHIER_PIN_DRV_3BIT, 9, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(10, "NFD0", 10, + UNIPHIER_PINCTRL_PIN(10, "NFD0", UNIPHIER_PIN_IECTRL_EXIST, 10, UNIPHIER_PIN_DRV_3BIT, 10, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(11, "NFD1", 11, + UNIPHIER_PINCTRL_PIN(11, "NFD1", UNIPHIER_PIN_IECTRL_EXIST, 11, UNIPHIER_PIN_DRV_3BIT, 11, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(12, "NFD2", 12, + UNIPHIER_PINCTRL_PIN(12, "NFD2", UNIPHIER_PIN_IECTRL_EXIST, 12, UNIPHIER_PIN_DRV_3BIT, 12, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(13, "NFD3", 13, + UNIPHIER_PINCTRL_PIN(13, "NFD3", UNIPHIER_PIN_IECTRL_EXIST, 13, UNIPHIER_PIN_DRV_3BIT, 13, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(14, "NFD4", 14, + UNIPHIER_PINCTRL_PIN(14, "NFD4", UNIPHIER_PIN_IECTRL_EXIST, 14, UNIPHIER_PIN_DRV_3BIT, 14, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(15, "NFD5", 15, + UNIPHIER_PINCTRL_PIN(15, "NFD5", UNIPHIER_PIN_IECTRL_EXIST, 15, UNIPHIER_PIN_DRV_3BIT, 15, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(16, "NFD6", 16, + UNIPHIER_PINCTRL_PIN(16, "NFD6", UNIPHIER_PIN_IECTRL_EXIST, 16, UNIPHIER_PIN_DRV_3BIT, 16, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(17, "NFD7", 17, + UNIPHIER_PINCTRL_PIN(17, "NFD7", UNIPHIER_PIN_IECTRL_EXIST, 17, UNIPHIER_PIN_DRV_3BIT, 17, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(18, "XERST", 18, + UNIPHIER_PINCTRL_PIN(18, "XERST", UNIPHIER_PIN_IECTRL_EXIST, 0, UNIPHIER_PIN_DRV_2BIT, 18, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(19, "MMCCLK", 19, + UNIPHIER_PINCTRL_PIN(19, "MMCCLK", UNIPHIER_PIN_IECTRL_EXIST, 1, UNIPHIER_PIN_DRV_2BIT, 19, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(20, "MMCCMD", 20, + UNIPHIER_PINCTRL_PIN(20, "MMCCMD", UNIPHIER_PIN_IECTRL_EXIST, 2, UNIPHIER_PIN_DRV_2BIT, 20, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(21, "MMCDS", 21, + UNIPHIER_PINCTRL_PIN(21, "MMCDS", UNIPHIER_PIN_IECTRL_EXIST, 3, UNIPHIER_PIN_DRV_2BIT, 21, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(22, "MMCDAT0", 22, + UNIPHIER_PINCTRL_PIN(22, "MMCDAT0", UNIPHIER_PIN_IECTRL_EXIST, 4, UNIPHIER_PIN_DRV_2BIT, 22, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(23, "MMCDAT1", 23, + UNIPHIER_PINCTRL_PIN(23, "MMCDAT1", UNIPHIER_PIN_IECTRL_EXIST, 5, UNIPHIER_PIN_DRV_2BIT, 23, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(24, "MMCDAT2", 24, + UNIPHIER_PINCTRL_PIN(24, "MMCDAT2", UNIPHIER_PIN_IECTRL_EXIST, 6, UNIPHIER_PIN_DRV_2BIT, 24, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(25, "MMCDAT3", 25, + UNIPHIER_PINCTRL_PIN(25, "MMCDAT3", UNIPHIER_PIN_IECTRL_EXIST, 7, UNIPHIER_PIN_DRV_2BIT, 25, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(26, "MMCDAT4", 26, + UNIPHIER_PINCTRL_PIN(26, "MMCDAT4", UNIPHIER_PIN_IECTRL_EXIST, 8, UNIPHIER_PIN_DRV_2BIT, 26, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(27, "MMCDAT5", 27, + UNIPHIER_PINCTRL_PIN(27, "MMCDAT5", UNIPHIER_PIN_IECTRL_EXIST, 9, UNIPHIER_PIN_DRV_2BIT, 27, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(28, "MMCDAT6", 28, + UNIPHIER_PINCTRL_PIN(28, "MMCDAT6", UNIPHIER_PIN_IECTRL_EXIST, 10, UNIPHIER_PIN_DRV_2BIT, 28, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(29, "MMCDAT7", 29, + UNIPHIER_PINCTRL_PIN(29, "MMCDAT7", UNIPHIER_PIN_IECTRL_EXIST, 11, UNIPHIER_PIN_DRV_2BIT, 29, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(30, "MDC", 30, + UNIPHIER_PINCTRL_PIN(30, "MDC", UNIPHIER_PIN_IECTRL_EXIST, 18, UNIPHIER_PIN_DRV_3BIT, 30, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(31, "MDIO", 31, + UNIPHIER_PINCTRL_PIN(31, "MDIO", UNIPHIER_PIN_IECTRL_EXIST, 19, UNIPHIER_PIN_DRV_3BIT, 31, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(32, "MDIO_INTL", 32, + UNIPHIER_PINCTRL_PIN(32, "MDIO_INTL", UNIPHIER_PIN_IECTRL_EXIST, 20, UNIPHIER_PIN_DRV_3BIT, 32, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(33, "PHYRSTL", 33, + UNIPHIER_PINCTRL_PIN(33, "PHYRSTL", UNIPHIER_PIN_IECTRL_EXIST, 21, UNIPHIER_PIN_DRV_3BIT, 33, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(34, "RGMII_RXCLK", 34, + UNIPHIER_PINCTRL_PIN(34, "RGMII_RXCLK", UNIPHIER_PIN_IECTRL_EXIST, 22, UNIPHIER_PIN_DRV_3BIT, 34, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(35, "RGMII_RXD0", 35, + UNIPHIER_PINCTRL_PIN(35, "RGMII_RXD0", UNIPHIER_PIN_IECTRL_EXIST, 23, UNIPHIER_PIN_DRV_3BIT, 35, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(36, "RGMII_RXD1", 36, + UNIPHIER_PINCTRL_PIN(36, "RGMII_RXD1", UNIPHIER_PIN_IECTRL_EXIST, 24, UNIPHIER_PIN_DRV_3BIT, 36, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(37, "RGMII_RXD2", 37, + UNIPHIER_PINCTRL_PIN(37, "RGMII_RXD2", UNIPHIER_PIN_IECTRL_EXIST, 25, UNIPHIER_PIN_DRV_3BIT, 37, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(38, "RGMII_RXD3", 38, + UNIPHIER_PINCTRL_PIN(38, "RGMII_RXD3", UNIPHIER_PIN_IECTRL_EXIST, 26, UNIPHIER_PIN_DRV_3BIT, 38, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(39, "RGMII_RXCTL", 39, + UNIPHIER_PINCTRL_PIN(39, "RGMII_RXCTL", UNIPHIER_PIN_IECTRL_EXIST, 27, UNIPHIER_PIN_DRV_3BIT, 39, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(40, "RGMII_TXCLK", 40, + UNIPHIER_PINCTRL_PIN(40, "RGMII_TXCLK", UNIPHIER_PIN_IECTRL_EXIST, 28, UNIPHIER_PIN_DRV_3BIT, 40, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(41, "RGMII_TXD0", 41, + UNIPHIER_PINCTRL_PIN(41, "RGMII_TXD0", UNIPHIER_PIN_IECTRL_EXIST, 29, UNIPHIER_PIN_DRV_3BIT, 41, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(42, "RGMII_TXD1", 42, + UNIPHIER_PINCTRL_PIN(42, "RGMII_TXD1", UNIPHIER_PIN_IECTRL_EXIST, 30, UNIPHIER_PIN_DRV_3BIT, 42, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(43, "RGMII_TXD2", 43, + UNIPHIER_PINCTRL_PIN(43, "RGMII_TXD2", UNIPHIER_PIN_IECTRL_EXIST, 31, UNIPHIER_PIN_DRV_3BIT, 43, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(44, "RGMII_TXD3", 44, + UNIPHIER_PINCTRL_PIN(44, "RGMII_TXD3", UNIPHIER_PIN_IECTRL_EXIST, 32, UNIPHIER_PIN_DRV_3BIT, 44, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(45, "RGMII_TXCTL", 45, + UNIPHIER_PINCTRL_PIN(45, "RGMII_TXCTL", UNIPHIER_PIN_IECTRL_EXIST, 33, UNIPHIER_PIN_DRV_3BIT, 45, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(46, "USB0VBUS", 46, + UNIPHIER_PINCTRL_PIN(46, "USB0VBUS", UNIPHIER_PIN_IECTRL_EXIST, 34, UNIPHIER_PIN_DRV_3BIT, 46, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(47, "USB0OD", 47, + UNIPHIER_PINCTRL_PIN(47, "USB0OD", UNIPHIER_PIN_IECTRL_EXIST, 35, UNIPHIER_PIN_DRV_3BIT, 47, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(48, "USB1VBUS", 48, + UNIPHIER_PINCTRL_PIN(48, "USB1VBUS", UNIPHIER_PIN_IECTRL_EXIST, 36, UNIPHIER_PIN_DRV_3BIT, 48, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(49, "USB1OD", 49, + UNIPHIER_PINCTRL_PIN(49, "USB1OD", UNIPHIER_PIN_IECTRL_EXIST, 37, UNIPHIER_PIN_DRV_3BIT, 49, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(50, "USB2VBUS", 50, + UNIPHIER_PINCTRL_PIN(50, "USB2VBUS", UNIPHIER_PIN_IECTRL_EXIST, 38, UNIPHIER_PIN_DRV_3BIT, 50, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(51, "USB2OD", 51, + UNIPHIER_PINCTRL_PIN(51, "USB2OD", UNIPHIER_PIN_IECTRL_EXIST, 39, UNIPHIER_PIN_DRV_3BIT, 51, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(52, "USB3VBUS", 52, + UNIPHIER_PINCTRL_PIN(52, "USB3VBUS", UNIPHIER_PIN_IECTRL_EXIST, 40, UNIPHIER_PIN_DRV_3BIT, 52, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(53, "USB3OD", 53, + UNIPHIER_PINCTRL_PIN(53, "USB3OD", UNIPHIER_PIN_IECTRL_EXIST, 41, UNIPHIER_PIN_DRV_3BIT, 53, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(54, "TXD0", 54, + UNIPHIER_PINCTRL_PIN(54, "TXD0", UNIPHIER_PIN_IECTRL_EXIST, 42, UNIPHIER_PIN_DRV_3BIT, 54, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(55, "RXD0", 55, + UNIPHIER_PINCTRL_PIN(55, "RXD0", UNIPHIER_PIN_IECTRL_EXIST, 43, UNIPHIER_PIN_DRV_3BIT, 55, UNIPHIER_PIN_PULL_UP), - UNIPHIER_PINCTRL_PIN(56, "SPISYNC0", 56, + UNIPHIER_PINCTRL_PIN(56, "SPISYNC0", UNIPHIER_PIN_IECTRL_EXIST, 44, UNIPHIER_PIN_DRV_3BIT, 56, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(57, "SPISCLK0", 57, + UNIPHIER_PINCTRL_PIN(57, "SPISCLK0", UNIPHIER_PIN_IECTRL_EXIST, 45, UNIPHIER_PIN_DRV_3BIT, 57, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(58, "SPITXD0", 58, + UNIPHIER_PINCTRL_PIN(58, "SPITXD0", UNIPHIER_PIN_IECTRL_EXIST, 46, UNIPHIER_PIN_DRV_3BIT, 58, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(59, "SPIRXD0", 59, + UNIPHIER_PINCTRL_PIN(59, "SPIRXD0", UNIPHIER_PIN_IECTRL_EXIST, 47, UNIPHIER_PIN_DRV_3BIT, 59, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(60, "AGCI", 60, + UNIPHIER_PINCTRL_PIN(60, "AGCI", UNIPHIER_PIN_IECTRL_EXIST, 48, UNIPHIER_PIN_DRV_3BIT, 60, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(61, "DMDSDA0", 61, + UNIPHIER_PINCTRL_PIN(61, "DMDSDA0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(62, "DMDSCL0", 62, + UNIPHIER_PINCTRL_PIN(62, "DMDSCL0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(63, "SDA0", 63, + UNIPHIER_PINCTRL_PIN(63, "SDA0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(64, "SCL0", 64, + UNIPHIER_PINCTRL_PIN(64, "SCL0", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(65, "SDA1", 65, + UNIPHIER_PINCTRL_PIN(65, "SDA1", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(66, "SCL1", 66, + UNIPHIER_PINCTRL_PIN(66, "SCL1", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(67, "HIN", 67, + UNIPHIER_PINCTRL_PIN(67, "HIN", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(68, "VIN", 68, + UNIPHIER_PINCTRL_PIN(68, "VIN", UNIPHIER_PIN_IECTRL_EXIST, -1, UNIPHIER_PIN_DRV_FIXED4, -1, UNIPHIER_PIN_PULL_NONE), - UNIPHIER_PINCTRL_PIN(69, "PCA00", 69, + UNIPHIER_PINCTRL_PIN(69, "PCA00", UNIPHIER_PIN_IECTRL_EXIST, 49, UNIPHIER_PIN_DRV_3BIT, 69, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(70, "PCA01", 70, + UNIPHIER_PINCTRL_PIN(70, "PCA01", UNIPHIER_PIN_IECTRL_EXIST, 50, UNIPHIER_PIN_DRV_3BIT, 70, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(71, "PCA02", 71, + UNIPHIER_PINCTRL_PIN(71, "PCA02", UNIPHIER_PIN_IECTRL_EXIST, 51, UNIPHIER_PIN_DRV_3BIT, 71, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(72, "PCA03", 72, + UNIPHIER_PINCTRL_PIN(72, "PCA03", UNIPHIER_PIN_IECTRL_EXIST, 52, UNIPHIER_PIN_DRV_3BIT, 72, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(73, "PCA04", 73, + UNIPHIER_PINCTRL_PIN(73, "PCA04", UNIPHIER_PIN_IECTRL_EXIST, 53, UNIPHIER_PIN_DRV_3BIT, 73, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(74, "PCA05", 74, + UNIPHIER_PINCTRL_PIN(74, "PCA05", UNIPHIER_PIN_IECTRL_EXIST, 54, UNIPHIER_PIN_DRV_3BIT, 74, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(75, "PCA06", 75, + UNIPHIER_PINCTRL_PIN(75, "PCA06", UNIPHIER_PIN_IECTRL_EXIST, 55, UNIPHIER_PIN_DRV_3BIT, 75, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(76, "PCA07", 76, + UNIPHIER_PINCTRL_PIN(76, "PCA07", UNIPHIER_PIN_IECTRL_EXIST, 56, UNIPHIER_PIN_DRV_3BIT, 76, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(77, "PCA08", 77, + UNIPHIER_PINCTRL_PIN(77, "PCA08", UNIPHIER_PIN_IECTRL_EXIST, 57, UNIPHIER_PIN_DRV_3BIT, 77, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(78, "PCA09", 78, + UNIPHIER_PINCTRL_PIN(78, "PCA09", UNIPHIER_PIN_IECTRL_EXIST, 58, UNIPHIER_PIN_DRV_3BIT, 78, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(79, "PCA10", 79, + UNIPHIER_PINCTRL_PIN(79, "PCA10", UNIPHIER_PIN_IECTRL_EXIST, 59, UNIPHIER_PIN_DRV_3BIT, 79, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(80, "PCA11", 80, + UNIPHIER_PINCTRL_PIN(80, "PCA11", UNIPHIER_PIN_IECTRL_EXIST, 60, UNIPHIER_PIN_DRV_3BIT, 80, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(81, "PCA12", 81, + UNIPHIER_PINCTRL_PIN(81, "PCA12", UNIPHIER_PIN_IECTRL_EXIST, 61, UNIPHIER_PIN_DRV_3BIT, 81, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(82, "PCA13", 82, + UNIPHIER_PINCTRL_PIN(82, "PCA13", UNIPHIER_PIN_IECTRL_EXIST, 62, UNIPHIER_PIN_DRV_3BIT, 82, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(83, "PCA14", 83, + UNIPHIER_PINCTRL_PIN(83, "PCA14", UNIPHIER_PIN_IECTRL_EXIST, 63, UNIPHIER_PIN_DRV_3BIT, 83, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(84, "PC0READY", 84, + UNIPHIER_PINCTRL_PIN(84, "PC0READY", UNIPHIER_PIN_IECTRL_EXIST, 0, UNIPHIER_PIN_DRV_1BIT, 84, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(85, "PC0CD1", 85, + UNIPHIER_PINCTRL_PIN(85, "PC0CD1", UNIPHIER_PIN_IECTRL_EXIST, 1, UNIPHIER_PIN_DRV_1BIT, 85, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(86, "PC0CD2", 86, + UNIPHIER_PINCTRL_PIN(86, "PC0CD2", UNIPHIER_PIN_IECTRL_EXIST, 2, UNIPHIER_PIN_DRV_1BIT, 86, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(87, "PC0WAIT", 87, + UNIPHIER_PINCTRL_PIN(87, "PC0WAIT", UNIPHIER_PIN_IECTRL_EXIST, 3, UNIPHIER_PIN_DRV_1BIT, 87, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(88, "PC0RESET", 88, + UNIPHIER_PINCTRL_PIN(88, "PC0RESET", UNIPHIER_PIN_IECTRL_EXIST, 4, UNIPHIER_PIN_DRV_1BIT, 88, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(89, "PC0CE1", 89, + UNIPHIER_PINCTRL_PIN(89, "PC0CE1", UNIPHIER_PIN_IECTRL_EXIST, 5, UNIPHIER_PIN_DRV_1BIT, 89, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(90, "PC0WE", 90, + UNIPHIER_PINCTRL_PIN(90, "PC0WE", UNIPHIER_PIN_IECTRL_EXIST, 6, UNIPHIER_PIN_DRV_1BIT, 90, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(91, "PC0OE", 91, + UNIPHIER_PINCTRL_PIN(91, "PC0OE", UNIPHIER_PIN_IECTRL_EXIST, 7, UNIPHIER_PIN_DRV_1BIT, 91, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(92, "PC0IOWR", 92, + UNIPHIER_PINCTRL_PIN(92, "PC0IOWR", UNIPHIER_PIN_IECTRL_EXIST, 8, UNIPHIER_PIN_DRV_1BIT, 92, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(93, "PC0IORD", 93, + UNIPHIER_PINCTRL_PIN(93, "PC0IORD", UNIPHIER_PIN_IECTRL_EXIST, 9, UNIPHIER_PIN_DRV_1BIT, 93, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(94, "PCD00", 94, + UNIPHIER_PINCTRL_PIN(94, "PCD00", UNIPHIER_PIN_IECTRL_EXIST, 10, UNIPHIER_PIN_DRV_1BIT, 94, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(95, "PCD01", 95, + UNIPHIER_PINCTRL_PIN(95, "PCD01", UNIPHIER_PIN_IECTRL_EXIST, 11, UNIPHIER_PIN_DRV_1BIT, 95, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(96, "PCD02", 96, + UNIPHIER_PINCTRL_PIN(96, "PCD02", UNIPHIER_PIN_IECTRL_EXIST, 12, UNIPHIER_PIN_DRV_1BIT, 96, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(97, "PCD03", 97, + UNIPHIER_PINCTRL_PIN(97, "PCD03", UNIPHIER_PIN_IECTRL_EXIST, 13, UNIPHIER_PIN_DRV_1BIT, 97, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(98, "PCD04", 98, + UNIPHIER_PINCTRL_PIN(98, "PCD04", UNIPHIER_PIN_IECTRL_EXIST, 14, UNIPHIER_PIN_DRV_1BIT, 98, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(99, "PCD05", 99, + UNIPHIER_PINCTRL_PIN(99, "PCD05", UNIPHIER_PIN_IECTRL_EXIST, 15, UNIPHIER_PIN_DRV_1BIT, 99, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(100, "PCD06", 100, + UNIPHIER_PINCTRL_PIN(100, "PCD06", UNIPHIER_PIN_IECTRL_EXIST, 16, UNIPHIER_PIN_DRV_1BIT, 100, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(101, "PCD07", 101, + UNIPHIER_PINCTRL_PIN(101, "PCD07", UNIPHIER_PIN_IECTRL_EXIST, 17, UNIPHIER_PIN_DRV_1BIT, 101, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(102, "HS0BCLKIN", 102, + UNIPHIER_PINCTRL_PIN(102, "HS0BCLKIN", UNIPHIER_PIN_IECTRL_EXIST, 18, UNIPHIER_PIN_DRV_1BIT, 102, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(103, "HS0SYNCIN", 103, + UNIPHIER_PINCTRL_PIN(103, "HS0SYNCIN", UNIPHIER_PIN_IECTRL_EXIST, 19, UNIPHIER_PIN_DRV_1BIT, 103, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(104, "HS0VALIN", 104, + UNIPHIER_PINCTRL_PIN(104, "HS0VALIN", UNIPHIER_PIN_IECTRL_EXIST, 20, UNIPHIER_PIN_DRV_1BIT, 104, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(105, "HS0DIN0", 105, + UNIPHIER_PINCTRL_PIN(105, "HS0DIN0", UNIPHIER_PIN_IECTRL_EXIST, 21, UNIPHIER_PIN_DRV_1BIT, 105, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(106, "HS0DIN1", 106, + UNIPHIER_PINCTRL_PIN(106, "HS0DIN1", UNIPHIER_PIN_IECTRL_EXIST, 22, UNIPHIER_PIN_DRV_1BIT, 106, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(107, "HS0DIN2", 107, + UNIPHIER_PINCTRL_PIN(107, "HS0DIN2", UNIPHIER_PIN_IECTRL_EXIST, 23, UNIPHIER_PIN_DRV_1BIT, 107, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(108, "HS0DIN3", 108, + UNIPHIER_PINCTRL_PIN(108, "HS0DIN3", UNIPHIER_PIN_IECTRL_EXIST, 24, UNIPHIER_PIN_DRV_1BIT, 108, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(109, "HS0DIN4", 109, + UNIPHIER_PINCTRL_PIN(109, "HS0DIN4", UNIPHIER_PIN_IECTRL_EXIST, 25, UNIPHIER_PIN_DRV_1BIT, 109, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(110, "HS0DIN5", 110, + UNIPHIER_PINCTRL_PIN(110, "HS0DIN5", UNIPHIER_PIN_IECTRL_EXIST, 26, UNIPHIER_PIN_DRV_1BIT, 110, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(111, "HS0DIN6", 111, + UNIPHIER_PINCTRL_PIN(111, "HS0DIN6", UNIPHIER_PIN_IECTRL_EXIST, 27, UNIPHIER_PIN_DRV_1BIT, 111, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(112, "HS0DIN7", 112, + UNIPHIER_PINCTRL_PIN(112, "HS0DIN7", UNIPHIER_PIN_IECTRL_EXIST, 28, UNIPHIER_PIN_DRV_1BIT, 112, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(113, "HS0BCLKOUT", 113, + UNIPHIER_PINCTRL_PIN(113, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_EXIST, 64, UNIPHIER_PIN_DRV_3BIT, 113, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(114, "HS0SYNCOUT", 114, + UNIPHIER_PINCTRL_PIN(114, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_EXIST, 65, UNIPHIER_PIN_DRV_3BIT, 114, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(115, "HS0VALOUT", 115, + UNIPHIER_PINCTRL_PIN(115, "HS0VALOUT", UNIPHIER_PIN_IECTRL_EXIST, 66, UNIPHIER_PIN_DRV_3BIT, 115, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(116, "HS0DOUT0", 116, + UNIPHIER_PINCTRL_PIN(116, "HS0DOUT0", UNIPHIER_PIN_IECTRL_EXIST, 67, UNIPHIER_PIN_DRV_3BIT, 116, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(117, "HS0DOUT1", 117, + UNIPHIER_PINCTRL_PIN(117, "HS0DOUT1", UNIPHIER_PIN_IECTRL_EXIST, 68, UNIPHIER_PIN_DRV_3BIT, 117, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(118, "HS0DOUT2", 118, + UNIPHIER_PINCTRL_PIN(118, "HS0DOUT2", UNIPHIER_PIN_IECTRL_EXIST, 69, UNIPHIER_PIN_DRV_3BIT, 118, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(119, "HS0DOUT3", 119, + UNIPHIER_PINCTRL_PIN(119, "HS0DOUT3", UNIPHIER_PIN_IECTRL_EXIST, 70, UNIPHIER_PIN_DRV_3BIT, 119, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(120, "HS0DOUT4", 120, + UNIPHIER_PINCTRL_PIN(120, "HS0DOUT4", UNIPHIER_PIN_IECTRL_EXIST, 71, UNIPHIER_PIN_DRV_3BIT, 120, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(121, "HS0DOUT5", 121, + UNIPHIER_PINCTRL_PIN(121, "HS0DOUT5", UNIPHIER_PIN_IECTRL_EXIST, 72, UNIPHIER_PIN_DRV_3BIT, 121, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(122, "HS0DOUT6", 122, + UNIPHIER_PINCTRL_PIN(122, "HS0DOUT6", UNIPHIER_PIN_IECTRL_EXIST, 73, UNIPHIER_PIN_DRV_3BIT, 122, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(123, "HS0DOUT7", 123, + UNIPHIER_PINCTRL_PIN(123, "HS0DOUT7", UNIPHIER_PIN_IECTRL_EXIST, 74, UNIPHIER_PIN_DRV_3BIT, 123, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(124, "HS1BCLKIN", 124, + UNIPHIER_PINCTRL_PIN(124, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_EXIST, 75, UNIPHIER_PIN_DRV_3BIT, 124, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(125, "HS1SYNCIN", 125, + UNIPHIER_PINCTRL_PIN(125, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_EXIST, 76, UNIPHIER_PIN_DRV_3BIT, 125, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(126, "HS1VALIN", 126, + UNIPHIER_PINCTRL_PIN(126, "HS1VALIN", UNIPHIER_PIN_IECTRL_EXIST, 77, UNIPHIER_PIN_DRV_3BIT, 126, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(127, "HS1DIN0", 127, + UNIPHIER_PINCTRL_PIN(127, "HS1DIN0", UNIPHIER_PIN_IECTRL_EXIST, 78, UNIPHIER_PIN_DRV_3BIT, 127, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(128, "HS1DIN1", 128, + UNIPHIER_PINCTRL_PIN(128, "HS1DIN1", UNIPHIER_PIN_IECTRL_EXIST, 79, UNIPHIER_PIN_DRV_3BIT, 128, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(129, "HS1DIN2", 129, + UNIPHIER_PINCTRL_PIN(129, "HS1DIN2", UNIPHIER_PIN_IECTRL_EXIST, 80, UNIPHIER_PIN_DRV_3BIT, 129, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(130, "HS1DIN3", 130, + UNIPHIER_PINCTRL_PIN(130, "HS1DIN3", UNIPHIER_PIN_IECTRL_EXIST, 81, UNIPHIER_PIN_DRV_3BIT, 130, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(131, "HS1DIN4", 131, + UNIPHIER_PINCTRL_PIN(131, "HS1DIN4", UNIPHIER_PIN_IECTRL_EXIST, 82, UNIPHIER_PIN_DRV_3BIT, 131, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", 132, + UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", UNIPHIER_PIN_IECTRL_EXIST, 83, UNIPHIER_PIN_DRV_3BIT, 132, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(133, "HS1DIN6", 133, + UNIPHIER_PINCTRL_PIN(133, "HS1DIN6", UNIPHIER_PIN_IECTRL_EXIST, 84, UNIPHIER_PIN_DRV_3BIT, 133, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(134, "HS1DIN7", 134, + UNIPHIER_PINCTRL_PIN(134, "HS1DIN7", UNIPHIER_PIN_IECTRL_EXIST, 85, UNIPHIER_PIN_DRV_3BIT, 134, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(135, "AO1IEC", 135, + UNIPHIER_PINCTRL_PIN(135, "AO1IEC", UNIPHIER_PIN_IECTRL_EXIST, 86, UNIPHIER_PIN_DRV_3BIT, 135, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(136, "AO1ARC", 136, + UNIPHIER_PINCTRL_PIN(136, "AO1ARC", UNIPHIER_PIN_IECTRL_EXIST, 87, UNIPHIER_PIN_DRV_3BIT, 136, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(137, "AO1DACCK", 137, + UNIPHIER_PINCTRL_PIN(137, "AO1DACCK", UNIPHIER_PIN_IECTRL_EXIST, 88, UNIPHIER_PIN_DRV_3BIT, 137, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(138, "AO1BCK", 138, + UNIPHIER_PINCTRL_PIN(138, "AO1BCK", UNIPHIER_PIN_IECTRL_EXIST, 89, UNIPHIER_PIN_DRV_3BIT, 138, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(139, "AO1LRCK", 139, + UNIPHIER_PINCTRL_PIN(139, "AO1LRCK", UNIPHIER_PIN_IECTRL_EXIST, 90, UNIPHIER_PIN_DRV_3BIT, 139, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(140, "AO1D0", 140, + UNIPHIER_PINCTRL_PIN(140, "AO1D0", UNIPHIER_PIN_IECTRL_EXIST, 91, UNIPHIER_PIN_DRV_3BIT, 140, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(141, "AO1D1", 141, + UNIPHIER_PINCTRL_PIN(141, "AO1D1", UNIPHIER_PIN_IECTRL_EXIST, 92, UNIPHIER_PIN_DRV_3BIT, 141, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(142, "AO1D2", 142, + UNIPHIER_PINCTRL_PIN(142, "AO1D2", UNIPHIER_PIN_IECTRL_EXIST, 93, UNIPHIER_PIN_DRV_3BIT, 142, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(143, "HTPDN0", 143, + UNIPHIER_PINCTRL_PIN(143, "HTPDN0", UNIPHIER_PIN_IECTRL_EXIST, 94, UNIPHIER_PIN_DRV_3BIT, 143, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(144, "LOCKN0", 144, + UNIPHIER_PINCTRL_PIN(144, "LOCKN0", UNIPHIER_PIN_IECTRL_EXIST, 95, UNIPHIER_PIN_DRV_3BIT, 144, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(145, "HTPDN1", 145, + UNIPHIER_PINCTRL_PIN(145, "HTPDN1", UNIPHIER_PIN_IECTRL_EXIST, 96, UNIPHIER_PIN_DRV_3BIT, 145, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(146, "LOCKN1", 146, + UNIPHIER_PINCTRL_PIN(146, "LOCKN1", UNIPHIER_PIN_IECTRL_EXIST, 97, UNIPHIER_PIN_DRV_3BIT, 146, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(147, "PWMA", 147, + UNIPHIER_PINCTRL_PIN(147, "PWMA", UNIPHIER_PIN_IECTRL_EXIST, 98, UNIPHIER_PIN_DRV_3BIT, 147, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(148, "LR_GOUT", 148, + UNIPHIER_PINCTRL_PIN(148, "LR_GOUT", UNIPHIER_PIN_IECTRL_EXIST, 99, UNIPHIER_PIN_DRV_3BIT, 148, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(149, "XIRQ0", 149, + UNIPHIER_PINCTRL_PIN(149, "XIRQ0", UNIPHIER_PIN_IECTRL_EXIST, 100, UNIPHIER_PIN_DRV_3BIT, 149, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(150, "XIRQ1", 150, + UNIPHIER_PINCTRL_PIN(150, "XIRQ1", UNIPHIER_PIN_IECTRL_EXIST, 101, UNIPHIER_PIN_DRV_3BIT, 150, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(151, "XIRQ2", 151, + UNIPHIER_PINCTRL_PIN(151, "XIRQ2", UNIPHIER_PIN_IECTRL_EXIST, 102, UNIPHIER_PIN_DRV_3BIT, 151, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(152, "XIRQ3", 152, + UNIPHIER_PINCTRL_PIN(152, "XIRQ3", UNIPHIER_PIN_IECTRL_EXIST, 103, UNIPHIER_PIN_DRV_3BIT, 152, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(153, "XIRQ4", 153, + UNIPHIER_PINCTRL_PIN(153, "XIRQ4", UNIPHIER_PIN_IECTRL_EXIST, 104, UNIPHIER_PIN_DRV_3BIT, 153, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(154, "XIRQ5", 154, + UNIPHIER_PINCTRL_PIN(154, "XIRQ5", UNIPHIER_PIN_IECTRL_EXIST, 105, UNIPHIER_PIN_DRV_3BIT, 154, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(155, "XIRQ6", 155, + UNIPHIER_PINCTRL_PIN(155, "XIRQ6", UNIPHIER_PIN_IECTRL_EXIST, 106, UNIPHIER_PIN_DRV_3BIT, 155, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(156, "XIRQ7", 156, + UNIPHIER_PINCTRL_PIN(156, "XIRQ7", UNIPHIER_PIN_IECTRL_EXIST, 107, UNIPHIER_PIN_DRV_3BIT, 156, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(157, "XIRQ8", 157, + UNIPHIER_PINCTRL_PIN(157, "XIRQ8", UNIPHIER_PIN_IECTRL_EXIST, 108, UNIPHIER_PIN_DRV_3BIT, 157, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(158, "XIRQ9", 158, + UNIPHIER_PINCTRL_PIN(158, "XIRQ9", UNIPHIER_PIN_IECTRL_EXIST, 109, UNIPHIER_PIN_DRV_3BIT, 158, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(159, "XIRQ10", 159, + UNIPHIER_PINCTRL_PIN(159, "XIRQ10", UNIPHIER_PIN_IECTRL_EXIST, 110, UNIPHIER_PIN_DRV_3BIT, 159, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(160, "XIRQ11", 160, + UNIPHIER_PINCTRL_PIN(160, "XIRQ11", UNIPHIER_PIN_IECTRL_EXIST, 111, UNIPHIER_PIN_DRV_3BIT, 160, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(161, "XIRQ13", 161, + UNIPHIER_PINCTRL_PIN(161, "XIRQ13", UNIPHIER_PIN_IECTRL_EXIST, 112, UNIPHIER_PIN_DRV_3BIT, 161, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(162, "XIRQ14", 162, + UNIPHIER_PINCTRL_PIN(162, "XIRQ14", UNIPHIER_PIN_IECTRL_EXIST, 113, UNIPHIER_PIN_DRV_3BIT, 162, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(163, "XIRQ16", 163, + UNIPHIER_PINCTRL_PIN(163, "XIRQ16", UNIPHIER_PIN_IECTRL_EXIST, 114, UNIPHIER_PIN_DRV_3BIT, 163, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(164, "XIRQ17", 164, + UNIPHIER_PINCTRL_PIN(164, "XIRQ17", UNIPHIER_PIN_IECTRL_EXIST, 115, UNIPHIER_PIN_DRV_3BIT, 164, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(165, "XIRQ18", 165, + UNIPHIER_PINCTRL_PIN(165, "XIRQ18", UNIPHIER_PIN_IECTRL_EXIST, 116, UNIPHIER_PIN_DRV_3BIT, 165, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(166, "XIRQ19", 166, + UNIPHIER_PINCTRL_PIN(166, "XIRQ19", UNIPHIER_PIN_IECTRL_EXIST, 117, UNIPHIER_PIN_DRV_3BIT, 166, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(167, "XIRQ20", 167, + UNIPHIER_PINCTRL_PIN(167, "XIRQ20", UNIPHIER_PIN_IECTRL_EXIST, 118, UNIPHIER_PIN_DRV_3BIT, 167, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(168, "PORT00", 168, + UNIPHIER_PINCTRL_PIN(168, "PORT00", UNIPHIER_PIN_IECTRL_EXIST, 119, UNIPHIER_PIN_DRV_3BIT, 168, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(169, "PORT01", 169, + UNIPHIER_PINCTRL_PIN(169, "PORT01", UNIPHIER_PIN_IECTRL_EXIST, 120, UNIPHIER_PIN_DRV_3BIT, 169, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(170, "PORT02", 170, + UNIPHIER_PINCTRL_PIN(170, "PORT02", UNIPHIER_PIN_IECTRL_EXIST, 121, UNIPHIER_PIN_DRV_3BIT, 170, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(171, "PORT03", 171, + UNIPHIER_PINCTRL_PIN(171, "PORT03", UNIPHIER_PIN_IECTRL_EXIST, 122, UNIPHIER_PIN_DRV_3BIT, 171, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(172, "PORT04", 172, + UNIPHIER_PINCTRL_PIN(172, "PORT04", UNIPHIER_PIN_IECTRL_EXIST, 123, UNIPHIER_PIN_DRV_3BIT, 172, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(173, "CK27FO", 173, + UNIPHIER_PINCTRL_PIN(173, "CK27FO", UNIPHIER_PIN_IECTRL_EXIST, 124, UNIPHIER_PIN_DRV_3BIT, 173, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(174, "PHSYNCO", 174, + UNIPHIER_PINCTRL_PIN(174, "PHSYNCO", UNIPHIER_PIN_IECTRL_EXIST, 125, UNIPHIER_PIN_DRV_3BIT, 174, UNIPHIER_PIN_PULL_DOWN), - UNIPHIER_PINCTRL_PIN(175, "PVSYNCO", 175, + UNIPHIER_PINCTRL_PIN(175, "PVSYNCO", UNIPHIER_PIN_IECTRL_EXIST, 126, UNIPHIER_PIN_DRV_3BIT, 175, UNIPHIER_PIN_PULL_DOWN), }; +static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142}; +static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25}; static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29}; @@ -597,7 +599,7 @@ static const unsigned usb2_pins[] = {50, 51}; static const int usb2_muxvals[] = {0, 0}; static const unsigned usb3_pins[] = {52, 53}; static const int usb3_muxvals[] = {0, 0}; -static const unsigned port_range0_pins[] = { +static const unsigned int gpio_range0_pins[] = { 168, 169, 170, 171, 172, 173, 174, 175, /* PORT0x */ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */ @@ -610,36 +612,16 @@ static const unsigned port_range0_pins[] = { 83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */ 91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */ }; -static const int port_range0_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ -}; -static const unsigned port_range1_pins[] = { +static const unsigned int gpio_range1_pins[] = { 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */ 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */ 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */ -}; -static const int port_range1_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ -}; -static const unsigned port_range2_pins[] = { + 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */ + 157, 158, 159, 160, 85, 161, 162, 84, /* XIRQ8-15 */ + 163, 164, 165, 166, 167, 146, 52, 53, /* XIRQ16-23 */ 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */ }; -static const int port_range2_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ -}; -static const unsigned port_range3_pins[] = { +static const unsigned int gpio_range2_pins[] = { 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */ 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */ 139, 140, 141, 142, 143, 144, 145, 146, /* PORT22x */ @@ -647,36 +629,9 @@ static const unsigned port_range3_pins[] = { 155, 156, 157, 158, 159, 160, 161, 162, /* PORT24x */ 163, 164, 165, 166, 167, /* PORT250-254 */ }; -static const int port_range3_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ - 15, 15, 15, 15, 15, /* PORT250-254 */ -}; -static const unsigned xirq_pins[] = { - 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */ - 157, 158, 159, 160, 85, 161, 162, 84, /* XIRQ8-15 */ - 163, 164, 165, 166, 167, 146, 52, 53, /* XIRQ16-23 */ -}; -static const int xirq_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 13, 14, 14, 13, /* XIRQ8-15 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ -}; -static const unsigned xirq_alternatives_pins[] = { - 94, 95, 96, 97, 98, 99, 100, 101, /* XIRQ0-7 */ - 102, 103, 104, 105, 106, 107, /* XIRQ8-11,13,14 */ - 108, 109, 110, 111, 112, 147, 141, 142, /* XIRQ16-23 */ -}; -static const int xirq_alternatives_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 14, 14, /* XIRQ8-11,13,14 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ -}; static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { + UNIPHIER_PINCTRL_GROUP(aout), UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(ether_rgmii), @@ -697,225 +652,12 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range2, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range2, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range2, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range2, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range2, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range2, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range2, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range2, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range3, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range3, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range3, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range3, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range3, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range3, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range3, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range3, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range3, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range3, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range3, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range3, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range3, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range3, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range3, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range3, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range3, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range3, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range3, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range3, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range3, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range3, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range3, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range3, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range3, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range3, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range3, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range3, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range3, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range3, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range3, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range3, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range3, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range3, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range3, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range3, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range3, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range3, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range3, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range3, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range3, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range3, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range3, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range3, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range3, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0b, xirq_alternatives, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1b, xirq_alternatives, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2b, xirq_alternatives, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5b, xirq_alternatives, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6b, xirq_alternatives, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7b, xirq_alternatives, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8b, xirq_alternatives, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9b, xirq_alternatives, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10b, xirq_alternatives, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11b, xirq_alternatives, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13b, xirq_alternatives, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21b, xirq_alternatives, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22b, xirq_alternatives, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23b, xirq_alternatives, 21), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; +static const char * const aout_groups[] = {"aout"}; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; static const char * const ether_rgmii_groups[] = {"ether_rgmii"}; static const char * const ether_rmii_groups[] = {"ether_rmii"}; @@ -935,69 +677,9 @@ static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - /* port110-117 missing */ - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - /* port150-177 missing */ - "port180", "port181", "port182", "port183", - "port184", "port185", "port186", "port187", - /* port190-197 missing */ - "port200", "port201", "port202", "port203", - "port204", "port205", "port206", "port207", - "port210", "port211", "port212", "port213", - "port214", "port215", "port216", "port217", - "port220", "port221", "port222", "port223", - "port224", "port225", "port226", "port227", - "port230", "port231", "port232", "port233", - "port234", "port235", "port236", "port237", - "port240", "port241", "port242", "port243", - "port244", "port245", "port246", "port247", - "port250", "port251", "port252", "port253", - "port254", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", "xirq13", "xirq14", "xirq15", - "xirq16", "xirq17", "xirq18", "xirq19", - "xirq20", "xirq21", "xirq22", "xirq23", - "xirq0b", "xirq1b", "xirq2b", "xirq3b", - "xirq4b", "xirq5b", "xirq6b", "xirq7b", - "xirq8b", "xirq9b", "xirq10b", "xirq11b", - /* none */ "xirq13b", "xirq14b", /* none */ - "xirq16b", "xirq17b", "xirq18b", "xirq19b", - "xirq20b", "xirq21b", "xirq22b", "xirq23b", -}; static const struct uniphier_pinmux_function uniphier_ld20_functions[] = { + UNIPHIER_PINMUX_FUNCTION(aout), UNIPHIER_PINMUX_FUNCTION(emmc), UNIPHIER_PINMUX_FUNCTION(ether_rgmii), UNIPHIER_PINMUX_FUNCTION(ether_rmii), @@ -1016,10 +698,20 @@ static const struct uniphier_pinmux_function uniphier_ld20_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), UNIPHIER_PINMUX_FUNCTION(usb3), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_ld20_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset == 132 || gpio_offset == 135) /* XIRQ12, 15 */ + return 13; + + if (gpio_offset >= 120 && gpio_offset <= 143) /* XIRQx */ + return 14; + + return 15; +} + static struct uniphier_pinctrl_socdata uniphier_ld20_pindata = { .pins = uniphier_ld20_pins, .npins = ARRAY_SIZE(uniphier_ld20_pins), @@ -1027,6 +719,7 @@ static struct uniphier_pinctrl_socdata uniphier_ld20_pindata = { .groups_count = ARRAY_SIZE(uniphier_ld20_groups), .functions = uniphier_ld20_functions, .functions_count = ARRAY_SIZE(uniphier_ld20_functions), + .get_gpio_muxval = uniphier_ld20_get_gpio_muxval, .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, }; @@ -1045,6 +738,7 @@ static struct platform_driver uniphier_ld20_pinctrl_driver = { .driver = { .name = "uniphier-ld20-pinctrl", .of_match_table = uniphier_ld20_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_ld20_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 8f2ad1c4c6f4..840382847212 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -606,59 +606,24 @@ static const unsigned usb2_pins[] = {155, 156}; static const int usb2_muxvals[] = {4, 4}; static const unsigned usb2b_pins[] = {67, 68}; static const int usb2b_muxvals[] = {23, 23}; -static const unsigned port_range0_pins[] = { - 135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */ - 143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */ - 151, 152, 153, 154, 155, 156, 157, 0, /* PORT2x */ - 1, 2, 3, 4, 5, 120, 121, 122, /* PORT3x */ - 24, 25, 26, 27, 28, 29, 30, 31, /* PORT4x */ - 40, 41, 42, 43, 44, 45, 46, 47, /* PORT5x */ - 48, 49, 50, 51, 52, 53, 54, 55, /* PORT6x */ - 56, 85, 84, 59, 82, 61, 64, 65, /* PORT7x */ - 8, 9, 10, 11, 12, 13, 14, 15, /* PORT8x */ - 66, 67, 68, 69, 70, 71, 72, 73, /* PORT9x */ - 74, 75, 89, 86, 78, 79, 80, 81, /* PORT10x */ - 60, 83, 58, 57, 88, 87, 77, 76, /* PORT11x */ - 90, 91, 92, 93, 94, 95, 96, 97, /* PORT12x */ - 98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */ - 103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */ -}; -static const int port_range0_muxvals[] = { - 0, 0, 0, 0, 0, 0, 0, 0, /* PORT0x */ - 0, 0, 0, 0, 0, 0, 0, 0, /* PORT1x */ - 0, 0, 0, 0, 0, 0, 0, 15, /* PORT2x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ -}; -static const unsigned port_range1_pins[] = { - 7, /* PORT166 */ -}; -static const int port_range1_muxvals[] = { - 15, /* PORT166 */ -}; -static const unsigned xirq_range0_pins[] = { - 151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */ - 130, 131, 132, 133, 62, /* XIRQ8-12 */ -}; -static const int xirq_range0_muxvals[] = { - 14, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */ - 0, 0, 0, 0, 14, /* XIRQ8-12 */ -}; -static const unsigned xirq_range1_pins[] = { - 134, 63, /* XIRQ14-15 */ -}; -static const int xirq_range1_muxvals[] = { - 0, 14, /* XIRQ14-15 */ +static const unsigned int gpio_range_pins[] = { + 135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */ + 143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */ + 151, 152, 153, 154, 155, 156, 157, 0, /* PORT2x */ + 1, 2, 3, 4, 5, 120, 121, 122, /* PORT3x */ + 24, 25, 26, 27, 28, 29, 30, 31, /* PORT4x */ + 40, 41, 42, 43, 44, 45, 46, 47, /* PORT5x */ + 48, 49, 50, 51, 52, 53, 54, 55, /* PORT6x */ + 56, 85, 84, 59, 82, 61, 64, 65, /* PORT7x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT8x */ + 66, 67, 68, 69, 70, 71, 72, 73, /* PORT9x */ + 74, 75, 89, 86, 78, 79, 80, 81, /* PORT10x */ + 60, 83, 58, 57, 88, 87, 77, 76, /* PORT11x */ + 90, 91, 92, 93, 94, 95, 96, 97, /* PORT12x */ + 98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */ + 103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */ + 151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */ + 130, 131, 132, 133, 62, 7, 134, 63, /* XIRQ8-12, PORT165, XIRQ14-15 */ }; static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = { @@ -687,146 +652,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb2b), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range), }; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; @@ -850,46 +676,6 @@ static const char * const uart3_groups[] = {"uart3"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2", "usb2b"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - "port110", "port111", "port112", "port113", - "port114", "port115", "port116", "port117", - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - /* port150-164 missing */ - /* none */ "port165", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", /* none*/ "xirq14", "xirq15", -}; static const struct uniphier_pinmux_function uniphier_ld4_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), @@ -909,10 +695,25 @@ static const struct uniphier_pinmux_function uniphier_ld4_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_ld4_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + switch (gpio_offset) { + case 0 ... 22: /* PORT00-PORT26 */ + case 121 ... 131: /* XIRQ1-XIRQ11 */ + case 134: /* XIRQ14 */ + return 0; + case 120: /* XIRQ0 */ + case 132: /* XIRQ12 */ + case 135: /* XIRQ15 */ + return 14; + default: + return 15; + } +} + static struct uniphier_pinctrl_socdata uniphier_ld4_pindata = { .pins = uniphier_ld4_pins, .npins = ARRAY_SIZE(uniphier_ld4_pins), @@ -920,6 +721,7 @@ static struct uniphier_pinctrl_socdata uniphier_ld4_pindata = { .groups_count = ARRAY_SIZE(uniphier_ld4_groups), .functions = uniphier_ld4_functions, .functions_count = ARRAY_SIZE(uniphier_ld4_functions), + .get_gpio_muxval = uniphier_ld4_get_gpio_muxval, .caps = 0, }; @@ -938,6 +740,7 @@ static struct platform_driver uniphier_ld4_pinctrl_driver = { .driver = { .name = "uniphier-ld4-pinctrl", .of_match_table = uniphier_ld4_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_ld4_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 8a0da937b670..493a90c6d733 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -803,7 +803,7 @@ static const unsigned usb2_pins[] = {60, 61}; static const int usb2_muxvals[] = {0, 0}; static const unsigned usb3_pins[] = {62, 63}; static const int usb3_muxvals[] = {0, 0}; -static const unsigned port_range0_pins[] = { +static const unsigned int gpio_range0_pins[] = { 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */ 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */ @@ -816,26 +816,13 @@ static const unsigned port_range0_pins[] = { 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */ 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */ }; -static const int port_range0_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ -}; -static const unsigned port_range1_pins[] = { +static const unsigned int gpio_range1_pins[] = { 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */ 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */ 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */ - 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */ - 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */ - 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */ + 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */ + 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */ + 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */ 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */ 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */ 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */ @@ -848,35 +835,6 @@ static const unsigned port_range1_pins[] = { 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */ 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */ }; -static const int port_range1_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */ -}; -static const unsigned xirq_pins[] = { - 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */ - 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */ - 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */ -}; -static const int xirq_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ -}; static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(adinter), @@ -907,257 +865,8 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120), - UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121), - UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122), - UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123), - UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124), - UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125), - UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126), - UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127), - UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128), - UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129), - UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130), - UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131), - UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132), - UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133), - UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134), - UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), }; static const char * const adinter_groups[] = {"adinter"}; @@ -1183,73 +892,6 @@ static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - /* port110-117 missing */ - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - "port150", "port151", "port152", "port153", - "port154", "port155", "port156", "port157", - "port160", "port161", "port162", "port163", - "port164", "port165", "port166", "port167", - "port170", "port171", "port172", "port173", - "port174", "port175", "port176", "port177", - "port180", "port181", "port182", "port183", - "port184", "port185", "port186", "port187", - "port190", "port191", "port192", "port193", - "port194", "port195", "port196", "port197", - "port200", "port201", "port202", "port203", - "port204", "port205", "port206", "port207", - "port210", "port211", "port212", "port213", - "port214", "port215", "port216", "port217", - "port220", "port221", "port222", "port223", - "port224", "port225", "port226", "port227", - "port230", "port231", "port232", "port233", - "port234", "port235", "port236", "port237", - "port240", "port241", "port242", "port243", - "port244", "port245", "port246", "port247", - "port250", "port251", "port252", "port253", - "port254", "port255", "port256", "port257", - "port260", "port261", "port262", "port263", - "port264", "port265", "port266", "port267", - "port270", "port271", "port272", "port273", - "port274", "port275", "port276", "port277", - "port280", "port281", "port282", "port283", - "port284", "port285", "port286", "port287", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", "xirq13", "xirq14", "xirq15", - "xirq16", "xirq17", "xirq18", "xirq19", - "xirq20", "xirq21", "xirq22", "xirq23", -}; static const struct uniphier_pinmux_function uniphier_ld6b_functions[] = { UNIPHIER_PINMUX_FUNCTION(adinter), /* Achip-Dchip interconnect */ @@ -1270,10 +912,18 @@ static const struct uniphier_pinmux_function uniphier_ld6b_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), UNIPHIER_PINMUX_FUNCTION(usb3), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_ld6b_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset >= 120 && gpio_offset <= 143) /* XIRQx */ + /* 15 will do because XIRQ0-23 are aliases of PORT150-177. */ + return 14; + + return 15; +} + static struct uniphier_pinctrl_socdata uniphier_ld6b_pindata = { .pins = uniphier_ld6b_pins, .npins = ARRAY_SIZE(uniphier_ld6b_pins), @@ -1281,6 +931,7 @@ static struct uniphier_pinctrl_socdata uniphier_ld6b_pindata = { .groups_count = ARRAY_SIZE(uniphier_ld6b_groups), .functions = uniphier_ld6b_functions, .functions_count = ARRAY_SIZE(uniphier_ld6b_functions), + .get_gpio_muxval = uniphier_ld6b_get_gpio_muxval, .caps = 0, }; @@ -1299,6 +950,7 @@ static struct platform_driver uniphier_ld6b_pinctrl_driver = { .driver = { .name = "uniphier-ld6b-pinctrl", .of_match_table = uniphier_ld6b_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_ld6b_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index c75e094b2d90..603204a00213 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -1086,87 +1086,38 @@ static const unsigned usb2_pins[] = {184, 185}; static const int usb2_muxvals[] = {0, 0}; static const unsigned usb3_pins[] = {187, 188}; static const int usb3_muxvals[] = {0, 0}; -static const unsigned port_range0_pins[] = { - 300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */ - 308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */ - 316, 317, 318, 16, 17, 18, 19, 20, /* PORT2x */ - 21, 22, 23, 4, 93, 94, 95, 63, /* PORT3x */ - 123, 122, 124, 125, 126, 141, 202, 203, /* PORT4x */ - 204, 226, 227, 290, 291, 233, 280, 281, /* PORT5x */ - 8, 7, 10, 29, 30, 48, 49, 50, /* PORT6x */ - 40, 41, 42, 43, 44, 45, 46, 47, /* PORT7x */ - 54, 51, 52, 53, 127, 128, 129, 130, /* PORT8x */ - 131, 132, 57, 60, 134, 133, 135, 136, /* PORT9x */ - 138, 137, 140, 139, 64, 65, 66, 67, /* PORT10x */ - 107, 106, 105, 104, 113, 112, 111, 110, /* PORT11x */ - 68, 69, 70, 71, 72, 73, 74, 75, /* PORT12x */ - 76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */ - 84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */ -}; -static const int port_range0_muxvals[] = { - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT0x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT1x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT2x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT3x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT4x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT5x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT6x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT7x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT8x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT9x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT10x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT11x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT12x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT13x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT14x */ -}; -static const unsigned port_range1_pins[] = { - 13, 14, 15, /* PORT175-177 */ - 157, 158, 156, 154, 150, 151, 152, 153, /* PORT18x */ - 326, 327, 325, 323, 319, 320, 321, 322, /* PORT19x */ - 160, 161, 162, 163, 164, 165, 166, 167, /* PORT20x */ - 168, 169, 170, 171, 172, 173, 174, 175, /* PORT21x */ - 180, 181, 182, 183, 184, 185, 187, 188, /* PORT22x */ - 193, 194, 195, 196, 197, 198, 199, 200, /* PORT23x */ - 191, 192, 215, 216, 217, 218, 219, 220, /* PORT24x */ - 222, 223, 224, 225, 228, 229, 230, 231, /* PORT25x */ - 282, 283, 284, 285, 286, 287, 288, 289, /* PORT26x */ - 292, 293, 294, 295, 296, 236, 237, 238, /* PORT27x */ - 275, 276, 277, 278, 239, 240, 249, 250, /* PORT28x */ - 251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */ - 31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */ -}; -static const int port_range1_muxvals[] = { - 7, 7, 7, /* PORT175-177 */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT18x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT19x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT20x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT21x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT22x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT23x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT24x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT25x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT26x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT27x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT28x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT29x */ - 7, 7, 7, 7, 7, 7, 7, 7, /* PORT30x */ -}; -static const unsigned xirq_pins[] = { - 11, 9, 12, 96, 97, 98, 108, 114, /* XIRQ0-7 */ - 234, 186, 99, 100, 101, 102, 184, 301, /* XIRQ8-15 */ - 302, 303, 304, 305, 306, /* XIRQ16-20 */ -}; -static const int xirq_muxvals[] = { - 7, 7, 7, 7, 7, 7, 7, 7, /* XIRQ0-7 */ - 7, 7, 7, 7, 7, 7, 2, 2, /* XIRQ8-15 */ - 2, 2, 2, 2, 2, /* XIRQ16-20 */ -}; -static const unsigned xirq_alternatives_pins[] = { - 184, 310, 316, -}; -static const int xirq_alternatives_muxvals[] = { - 2, 2, 2, +static const unsigned int gpio_range_pins[] = { + 300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */ + 308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */ + 316, 317, 318, 16, 17, 18, 19, 20, /* PORT2x */ + 21, 22, 23, 4, 93, 94, 95, 63, /* PORT3x */ + 123, 122, 124, 125, 126, 141, 202, 203, /* PORT4x */ + 204, 226, 227, 290, 291, 233, 280, 281, /* PORT5x */ + 8, 7, 10, 29, 30, 48, 49, 50, /* PORT6x */ + 40, 41, 42, 43, 44, 45, 46, 47, /* PORT7x */ + 54, 51, 52, 53, 127, 128, 129, 130, /* PORT8x */ + 131, 132, 57, 60, 134, 133, 135, 136, /* PORT9x */ + 138, 137, 140, 139, 64, 65, 66, 67, /* PORT10x */ + 107, 106, 105, 104, 113, 112, 111, 110, /* PORT11x */ + 68, 69, 70, 71, 72, 73, 74, 75, /* PORT12x */ + 76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */ + 84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */ + 11, 9, 12, 96, 97, 98, 108, 114, /* XIRQ0-7 */ + 234, 186, 99, 100, 101, 102, 300, 301, /* XIRQ8-15 */ + 302, 303, 304, 305, 306, 13, 14, 15, /* XIRQ16-20, PORT175-177 */ + 157, 158, 156, 154, 150, 151, 152, 153, /* PORT18x */ + 326, 327, 325, 323, 319, 320, 321, 322, /* PORT19x */ + 160, 161, 162, 163, 164, 165, 166, 167, /* PORT20x */ + 168, 169, 170, 171, 172, 173, 174, 175, /* PORT21x */ + 180, 181, 182, 183, 184, 185, 187, 188, /* PORT22x */ + 193, 194, 195, 196, 197, 198, 199, 200, /* PORT23x */ + 191, 192, 215, 216, 217, 218, 219, 220, /* PORT24x */ + 222, 223, 224, 225, 228, 229, 230, 231, /* PORT25x */ + 282, 283, 284, 285, 286, 287, 288, 289, /* PORT26x */ + 292, 293, 294, 295, 296, 236, 237, 238, /* PORT27x */ + 275, 276, 277, 278, 239, 240, 249, 250, /* PORT28x */ + 251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */ + 31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */ }; static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = { @@ -1202,267 +1153,13 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 2), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range), }; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; static const char * const ether_mii_groups[] = {"ether_mii"}; static const char * const ether_rgmii_groups[] = {"ether_rgmii"}; -static const char * const ether_rmii_groups[] = {"ether_rgmii", "ether_rgmiib"}; +static const char * const ether_rmii_groups[] = {"ether_rmii", "ether_rmiib"}; static const char * const i2c0_groups[] = {"i2c0"}; static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c2_groups[] = {"i2c2"}; @@ -1488,75 +1185,6 @@ static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - "port110", "port111", "port112", "port113", - "port114", "port115", "port116", "port117", - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - /* port150-174 missing */ - /* none */ "port175", "port176", "port177", - "port180", "port181", "port182", "port183", - "port184", "port185", "port186", "port187", - "port190", "port191", "port192", "port193", - "port194", "port195", "port196", "port197", - "port200", "port201", "port202", "port203", - "port204", "port205", "port206", "port207", - "port210", "port211", "port212", "port213", - "port214", "port215", "port216", "port217", - "port220", "port221", "port222", "port223", - "port224", "port225", "port226", "port227", - "port230", "port231", "port232", "port233", - "port234", "port235", "port236", "port237", - "port240", "port241", "port242", "port243", - "port244", "port245", "port246", "port247", - "port250", "port251", "port252", "port253", - "port254", "port255", "port256", "port257", - "port260", "port261", "port262", "port263", - "port264", "port265", "port266", "port267", - "port270", "port271", "port272", "port273", - "port274", "port275", "port276", "port277", - "port280", "port281", "port282", "port283", - "port284", "port285", "port286", "port287", - "port290", "port291", "port292", "port293", - "port294", "port295", "port296", "port297", - "port300", "port301", "port302", "port303", - "port304", "port305", "port306", "port307", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", "xirq13", "xirq14", "xirq15", - "xirq16", "xirq17", "xirq18", "xirq19", - "xirq20", - "xirq14b", "xirq17b", "xirq18b", -}; static const struct uniphier_pinmux_function uniphier_pro4_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), @@ -1580,10 +1208,17 @@ static const struct uniphier_pinmux_function uniphier_pro4_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), UNIPHIER_PINMUX_FUNCTION(usb3), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_pro4_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset >= 134 && gpio_offset <= 140) /* XIRQ14-20 */ + return 2; + + return 7; +} + static struct uniphier_pinctrl_socdata uniphier_pro4_pindata = { .pins = uniphier_pro4_pins, .npins = ARRAY_SIZE(uniphier_pro4_pins), @@ -1591,6 +1226,7 @@ static struct uniphier_pinctrl_socdata uniphier_pro4_pindata = { .groups_count = ARRAY_SIZE(uniphier_pro4_groups), .functions = uniphier_pro4_functions, .functions_count = ARRAY_SIZE(uniphier_pro4_functions), + .get_gpio_muxval = uniphier_pro4_get_gpio_muxval, .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE, }; @@ -1609,6 +1245,7 @@ static struct platform_driver uniphier_pro4_pinctrl_driver = { .driver = { .name = "uniphier-pro4-pinctrl", .of_match_table = uniphier_pro4_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_pro4_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 04d00c398eaf..9381a4ff4389 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -854,87 +854,38 @@ static const unsigned usb1_pins[] = {126, 127}; static const int usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {128, 129}; static const int usb2_muxvals[] = {0, 0}; -static const unsigned port_range0_pins[] = { - 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */ - 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */ - 251, 252, 253, 254, 255, 247, 248, 249, /* PORT2x */ - 39, 40, 41, 42, 43, 44, 45, 46, /* PORT3x */ - 156, 157, 158, 159, 160, 161, 162, 163, /* PORT4x */ - 164, 165, 166, 167, 168, 169, 170, 171, /* PORT5x */ - 190, 191, 192, 193, 194, 195, 196, 197, /* PORT6x */ - 198, 199, 200, 201, 202, 203, 204, 205, /* PORT7x */ - 120, 121, 122, 123, 55, 56, 57, 58, /* PORT8x */ - 124, 125, 126, 127, 49, 50, 53, 54, /* PORT9x */ - 148, 149, 150, 151, 152, 153, 154, 155, /* PORT10x */ - 133, 134, 131, 130, 138, 139, 136, 135, /* PORT11x */ - 28, 29, 30, 31, 32, 33, 34, 35, /* PORT12x */ - 179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */ - 4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */ -}; -static const int port_range0_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ -}; -static const unsigned port_range1_pins[] = { - 109, 110, 111, /* PORT175-177 */ - 206, 207, 208, 209, 210, 211, 212, 213, /* PORT18x */ - 12, 13, 14, 15, 16, 17, 107, 108, /* PORT19x */ - 140, 141, 142, 143, 144, 145, 146, 147, /* PORT20x */ - 59, 60, 61, 62, 63, 64, 65, 66, /* PORT21x */ - 214, 215, 216, 217, 218, 219, 220, 221, /* PORT22x */ - 222, 223, 224, 225, 226, 227, 228, 229, /* PORT23x */ - 19, 20, 21, 22, 23, 24, 25, 26, /* PORT24x */ - 230, 231, 232, 233, 234, 235, 236, 237, /* PORT25x */ - 239, 240, 241, 242, 243, 244, 245, 246, /* PORT26x */ - 172, 173, 174, 175, 176, 177, 178, 129, /* PORT27x */ - 0, 1, 2, 67, 85, 86, 87, 88, /* PORT28x */ - 105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */ - 183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */ -}; -static const int port_range1_muxvals[] = { - 15, 15, 15, /* PORT175-177 */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT29x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT30x */ -}; -static const unsigned xirq_pins[] = { - 68, 69, 70, 71, 72, 73, 74, 75, /* XIRQ0-7 */ - 76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */ - 84, 85, 86, 87, 88, /* XIRQ16-20 */ -}; -static const int xirq_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */ - 14, 14, 14, 14, 14, /* XIRQ16-20 */ -}; -static const unsigned xirq_alternatives_pins[] = { - 91, 92, 239, 144, 240, 156, 241, 106, 128, -}; -static const int xirq_alternatives_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, 14, +static const unsigned int gpio_range_pins[] = { + 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */ + 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */ + 251, 252, 253, 254, 255, 247, 248, 249, /* PORT2x */ + 39, 40, 41, 42, 43, 44, 45, 46, /* PORT3x */ + 156, 157, 158, 159, 160, 161, 162, 163, /* PORT4x */ + 164, 165, 166, 167, 168, 169, 170, 171, /* PORT5x */ + 190, 191, 192, 193, 194, 195, 196, 197, /* PORT6x */ + 198, 199, 200, 201, 202, 203, 204, 205, /* PORT7x */ + 120, 121, 122, 123, 55, 56, 57, 58, /* PORT8x */ + 124, 125, 126, 127, 49, 50, 53, 54, /* PORT9x */ + 148, 149, 150, 151, 152, 153, 154, 155, /* PORT10x */ + 133, 134, 131, 130, 138, 139, 136, 135, /* PORT11x */ + 28, 29, 30, 31, 32, 33, 34, 35, /* PORT12x */ + 179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */ + 4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */ + 68, 69, 70, 71, 72, 73, 74, 75, /* XIRQ0-7 */ + 76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */ + 84, 85, 86, 87, 88, 109, 110, 111, /* XIRQ16-20, PORT175-177 */ + 206, 207, 208, 209, 210, 211, 212, 213, /* PORT18x */ + 12, 13, 14, 15, 16, 17, 107, 108, /* PORT19x */ + 140, 141, 142, 143, 144, 145, 146, 147, /* PORT20x */ + 59, 60, 61, 62, 63, 64, 65, 66, /* PORT21x */ + 214, 215, 216, 217, 218, 219, 220, 221, /* PORT22x */ + 222, 223, 224, 225, 226, 227, 228, 229, /* PORT23x */ + 19, 20, 21, 22, 23, 24, 25, 26, /* PORT24x */ + 230, 231, 232, 233, 234, 235, 236, 237, /* PORT25x */ + 239, 240, 241, 242, 243, 244, 245, 246, /* PORT26x */ + 172, 173, 174, 175, 176, 177, 178, 129, /* PORT27x */ + 0, 1, 2, 67, 85, 86, 87, 88, /* PORT28x */ + 105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */ + 183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */ }; static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { @@ -968,267 +919,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 8), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range), }; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; @@ -1256,76 +947,6 @@ static const char * const uart3_groups[] = {"uart3"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - "port110", "port111", "port112", "port113", - "port114", "port115", "port116", "port117", - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - /* port150-174 missing */ - /* none */ "port175", "port176", "port177", - "port180", "port181", "port182", "port183", - "port184", "port185", "port186", "port187", - "port190", "port191", "port192", "port193", - "port194", "port195", "port196", "port197", - "port200", "port201", "port202", "port203", - "port204", "port205", "port206", "port207", - "port210", "port211", "port212", "port213", - "port214", "port215", "port216", "port217", - "port220", "port221", "port222", "port223", - "port224", "port225", "port226", "port227", - "port230", "port231", "port232", "port233", - "port234", "port235", "port236", "port237", - "port240", "port241", "port242", "port243", - "port244", "port245", "port246", "port247", - "port250", "port251", "port252", "port253", - "port254", "port255", "port256", "port257", - "port260", "port261", "port262", "port263", - "port264", "port265", "port266", "port267", - "port270", "port271", "port272", "port273", - "port274", "port275", "port276", "port277", - "port280", "port281", "port282", "port283", - "port284", "port285", "port286", "port287", - "port290", "port291", "port292", "port293", - "port294", "port295", "port296", "port297", - "port300", "port301", "port302", "port303", - "port304", "port305", "port306", "port307", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", "xirq13", "xirq14", "xirq15", - "xirq16", "xirq17", "xirq18", "xirq19", - "xirq20", - "xirq3b", "xirq4b", "xirq16b", "xirq17b", "xirq17c", - "xirq18b", "xirq18c", "xirq19b", "xirq20b", -}; static const struct uniphier_pinmux_function uniphier_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), @@ -1345,10 +966,17 @@ static const struct uniphier_pinmux_function uniphier_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_pro5_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset >= 120 && gpio_offset <= 141) /* XIRQ0-20 */ + return 14; + + return 15; +} + static struct uniphier_pinctrl_socdata uniphier_pro5_pindata = { .pins = uniphier_pro5_pins, .npins = ARRAY_SIZE(uniphier_pro5_pins), @@ -1356,6 +984,7 @@ static struct uniphier_pinctrl_socdata uniphier_pro5_pindata = { .groups_count = ARRAY_SIZE(uniphier_pro5_groups), .functions = uniphier_pro5_functions, .functions_count = ARRAY_SIZE(uniphier_pro5_functions), + .get_gpio_muxval = uniphier_pro5_get_gpio_muxval, .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE, }; @@ -1374,6 +1003,7 @@ static struct platform_driver uniphier_pro5_pinctrl_driver = { .driver = { .name = "uniphier-pro5-pinctrl", .of_match_table = uniphier_pro5_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_pro5_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 53b6b774654e..c0ef40ae99a7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -790,7 +790,7 @@ static const unsigned usb2_pins[] = {60, 61}; static const int usb2_muxvals[] = {8, 8}; static const unsigned usb3_pins[] = {62, 63}; static const int usb3_muxvals[] = {8, 8}; -static const unsigned port_range0_pins[] = { +static const unsigned int gpio_range0_pins[] = { 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */ 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */ @@ -803,26 +803,13 @@ static const unsigned port_range0_pins[] = { 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */ 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */ }; -static const int port_range0_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ -}; -static const unsigned port_range1_pins[] = { +static const unsigned int gpio_range1_pins[] = { 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */ 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */ 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */ - 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */ - 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */ - 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */ + 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */ + 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */ + 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */ 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */ 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */ 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */ @@ -835,35 +822,6 @@ static const unsigned port_range1_pins[] = { 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */ 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */ }; -static const int port_range1_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */ -}; -static const unsigned xirq_pins[] = { - 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */ - 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */ - 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */ -}; -static const int xirq_muxvals[] = { - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */ - 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */ -}; static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), @@ -892,257 +850,8 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120), - UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121), - UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122), - UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123), - UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124), - UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125), - UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126), - UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127), - UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128), - UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129), - UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130), - UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131), - UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132), - UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133), - UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134), - UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), }; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; @@ -1167,73 +876,6 @@ static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - /* port110-117 missing */ - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - "port150", "port151", "port152", "port153", - "port154", "port155", "port156", "port157", - "port160", "port161", "port162", "port163", - "port164", "port165", "port166", "port167", - "port170", "port171", "port172", "port173", - "port174", "port175", "port176", "port177", - "port180", "port181", "port182", "port183", - "port184", "port185", "port186", "port187", - "port190", "port191", "port192", "port193", - "port194", "port195", "port196", "port197", - "port200", "port201", "port202", "port203", - "port204", "port205", "port206", "port207", - "port210", "port211", "port212", "port213", - "port214", "port215", "port216", "port217", - "port220", "port221", "port222", "port223", - "port224", "port225", "port226", "port227", - "port230", "port231", "port232", "port233", - "port234", "port235", "port236", "port237", - "port240", "port241", "port242", "port243", - "port244", "port245", "port246", "port247", - "port250", "port251", "port252", "port253", - "port254", "port255", "port256", "port257", - "port260", "port261", "port262", "port263", - "port264", "port265", "port266", "port267", - "port270", "port271", "port272", "port273", - "port274", "port275", "port276", "port277", - "port280", "port281", "port282", "port283", - "port284", "port285", "port286", "port287", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", "xirq13", "xirq14", "xirq15", - "xirq16", "xirq17", "xirq18", "xirq19", - "xirq20", "xirq21", "xirq22", "xirq23", -}; static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), @@ -1257,10 +899,18 @@ static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), UNIPHIER_PINMUX_FUNCTION(usb3), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_pxs2_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset >= 120 && gpio_offset <= 143) /* XIRQx */ + /* 15 will do because XIRQ0-23 are aliases of PORT150-177. */ + return 14; + + return 15; +} + static struct uniphier_pinctrl_socdata uniphier_pxs2_pindata = { .pins = uniphier_pxs2_pins, .npins = ARRAY_SIZE(uniphier_pxs2_pins), @@ -1268,6 +918,7 @@ static struct uniphier_pinctrl_socdata uniphier_pxs2_pindata = { .groups_count = ARRAY_SIZE(uniphier_pxs2_groups), .functions = uniphier_pxs2_functions, .functions_count = ARRAY_SIZE(uniphier_pxs2_functions), + .get_gpio_muxval = uniphier_pxs2_get_gpio_muxval, .caps = 0, }; @@ -1286,6 +937,7 @@ static struct platform_driver uniphier_pxs2_pinctrl_driver = { .driver = { .name = "uniphier-pxs2-pinctrl", .of_match_table = uniphier_pxs2_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_pxs2_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c new file mode 100644 index 000000000000..d9f166f0cc86 --- /dev/null +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -0,0 +1,989 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-uniphier.h" + +static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = { + UNIPHIER_PINCTRL_PIN(0, "LPST", UNIPHIER_PIN_IECTRL_EXIST, + 0, UNIPHIER_PIN_DRV_3BIT, + 0, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(1, "ED0", UNIPHIER_PIN_IECTRL_EXIST, + 1, UNIPHIER_PIN_DRV_3BIT, + 1, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(2, "ED1", UNIPHIER_PIN_IECTRL_EXIST, + 2, UNIPHIER_PIN_DRV_3BIT, + 2, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(3, "ED2", UNIPHIER_PIN_IECTRL_EXIST, + 3, UNIPHIER_PIN_DRV_3BIT, + 3, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(4, "ED3", UNIPHIER_PIN_IECTRL_EXIST, + 4, UNIPHIER_PIN_DRV_3BIT, + 4, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(5, "ED4", UNIPHIER_PIN_IECTRL_EXIST, + 5, UNIPHIER_PIN_DRV_3BIT, + 5, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(6, "ED5", UNIPHIER_PIN_IECTRL_EXIST, + 6, UNIPHIER_PIN_DRV_3BIT, + 6, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(7, "ED6", UNIPHIER_PIN_IECTRL_EXIST, + 7, UNIPHIER_PIN_DRV_3BIT, + 7, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(8, "ED7", UNIPHIER_PIN_IECTRL_EXIST, + 8, UNIPHIER_PIN_DRV_3BIT, + 8, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(9, "XERWE0", UNIPHIER_PIN_IECTRL_EXIST, + 9, UNIPHIER_PIN_DRV_3BIT, + 9, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(10, "XERWE1", UNIPHIER_PIN_IECTRL_EXIST, + 10, UNIPHIER_PIN_DRV_3BIT, + 10, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(11, "ERXW", UNIPHIER_PIN_IECTRL_EXIST, + 11, UNIPHIER_PIN_DRV_3BIT, + 11, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(12, "ES0", UNIPHIER_PIN_IECTRL_EXIST, + 12, UNIPHIER_PIN_DRV_3BIT, + 12, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(13, "ES1", UNIPHIER_PIN_IECTRL_EXIST, + 13, UNIPHIER_PIN_DRV_3BIT, + 13, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(14, "ES2", UNIPHIER_PIN_IECTRL_EXIST, + 14, UNIPHIER_PIN_DRV_3BIT, + 14, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(15, "XECS1", UNIPHIER_PIN_IECTRL_EXIST, + 15, UNIPHIER_PIN_DRV_3BIT, + 15, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(16, "XNFWP", UNIPHIER_PIN_IECTRL_EXIST, + 16, UNIPHIER_PIN_DRV_3BIT, + 16, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(17, "XNFCE0", UNIPHIER_PIN_IECTRL_EXIST, + 17, UNIPHIER_PIN_DRV_3BIT, + 17, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(18, "NFRYBY0", UNIPHIER_PIN_IECTRL_EXIST, + 18, UNIPHIER_PIN_DRV_3BIT, + 18, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(19, "XNFRE", UNIPHIER_PIN_IECTRL_EXIST, + 19, UNIPHIER_PIN_DRV_3BIT, + 19, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(20, "XNFWE", UNIPHIER_PIN_IECTRL_EXIST, + 20, UNIPHIER_PIN_DRV_3BIT, + 20, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(21, "NFALE", UNIPHIER_PIN_IECTRL_EXIST, + 21, UNIPHIER_PIN_DRV_3BIT, + 21, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(22, "NFCLE", UNIPHIER_PIN_IECTRL_EXIST, + 22, UNIPHIER_PIN_DRV_3BIT, + 22, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(23, "NFD0", UNIPHIER_PIN_IECTRL_EXIST, + 23, UNIPHIER_PIN_DRV_3BIT, + 23, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(24, "NFD1", UNIPHIER_PIN_IECTRL_EXIST, + 24, UNIPHIER_PIN_DRV_3BIT, + 24, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(25, "NFD2", UNIPHIER_PIN_IECTRL_EXIST, + 25, UNIPHIER_PIN_DRV_3BIT, + 25, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(26, "NFD3", UNIPHIER_PIN_IECTRL_EXIST, + 26, UNIPHIER_PIN_DRV_3BIT, + 26, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(27, "NFD4", UNIPHIER_PIN_IECTRL_EXIST, + 27, UNIPHIER_PIN_DRV_3BIT, + 27, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(28, "NFD5", UNIPHIER_PIN_IECTRL_EXIST, + 28, UNIPHIER_PIN_DRV_3BIT, + 28, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(29, "NFD6", UNIPHIER_PIN_IECTRL_EXIST, + 29, UNIPHIER_PIN_DRV_3BIT, + 29, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(30, "NFD7", UNIPHIER_PIN_IECTRL_EXIST, + 30, UNIPHIER_PIN_DRV_3BIT, + 30, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(31, "XERST", UNIPHIER_PIN_IECTRL_EXIST, + 0, UNIPHIER_PIN_DRV_2BIT, + 31, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(32, "MMCCLK", UNIPHIER_PIN_IECTRL_EXIST, + 1, UNIPHIER_PIN_DRV_2BIT, + 32, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(33, "MMCCMD", UNIPHIER_PIN_IECTRL_EXIST, + 2, UNIPHIER_PIN_DRV_2BIT, + 33, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(34, "MMCDS", UNIPHIER_PIN_IECTRL_EXIST, + 3, UNIPHIER_PIN_DRV_2BIT, + 34, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(35, "MMCDAT0", UNIPHIER_PIN_IECTRL_EXIST, + 4, UNIPHIER_PIN_DRV_2BIT, + 35, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(36, "MMCDAT1", UNIPHIER_PIN_IECTRL_EXIST, + 5, UNIPHIER_PIN_DRV_2BIT, + 36, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(37, "MMCDAT2", UNIPHIER_PIN_IECTRL_EXIST, + 6, UNIPHIER_PIN_DRV_2BIT, + 37, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(38, "MMCDAT3", UNIPHIER_PIN_IECTRL_EXIST, + 7, UNIPHIER_PIN_DRV_2BIT, + 38, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(39, "MMCDAT4", UNIPHIER_PIN_IECTRL_EXIST, + 8, UNIPHIER_PIN_DRV_2BIT, + 39, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(40, "MMCDAT5", UNIPHIER_PIN_IECTRL_EXIST, + 9, UNIPHIER_PIN_DRV_2BIT, + 40, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(41, "MMCDAT6", UNIPHIER_PIN_IECTRL_EXIST, + 10, UNIPHIER_PIN_DRV_2BIT, + 41, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(42, "MMCDAT7", UNIPHIER_PIN_IECTRL_EXIST, + 11, UNIPHIER_PIN_DRV_2BIT, + 42, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(43, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST, + 12, UNIPHIER_PIN_DRV_2BIT, + 43, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(44, "SDCMD", UNIPHIER_PIN_IECTRL_EXIST, + 13, UNIPHIER_PIN_DRV_2BIT, + 44, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(45, "SDDAT0", UNIPHIER_PIN_IECTRL_EXIST, + 14, UNIPHIER_PIN_DRV_2BIT, + 45, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(46, "SDDAT1", UNIPHIER_PIN_IECTRL_EXIST, + 15, UNIPHIER_PIN_DRV_2BIT, + 46, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(47, "SDDAT2", UNIPHIER_PIN_IECTRL_EXIST, + 16, UNIPHIER_PIN_DRV_2BIT, + 47, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(48, "SDDAT3", UNIPHIER_PIN_IECTRL_EXIST, + 17, UNIPHIER_PIN_DRV_2BIT, + 48, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(49, "SDCD", UNIPHIER_PIN_IECTRL_EXIST, + 31, UNIPHIER_PIN_DRV_3BIT, + 49, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(50, "SDWP", UNIPHIER_PIN_IECTRL_EXIST, + 32, UNIPHIER_PIN_DRV_3BIT, + 50, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(51, "SDVOLC", UNIPHIER_PIN_IECTRL_EXIST, + 33, UNIPHIER_PIN_DRV_3BIT, + 51, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(52, "MDC0", UNIPHIER_PIN_IECTRL_EXIST, + 18, UNIPHIER_PIN_DRV_2BIT, + 52, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(53, "MDIO0", UNIPHIER_PIN_IECTRL_EXIST, + 19, UNIPHIER_PIN_DRV_2BIT, + 53, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(54, "MDIO0_INTL", UNIPHIER_PIN_IECTRL_EXIST, + 20, UNIPHIER_PIN_DRV_2BIT, + 54, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(55, "PHYRSTL0", UNIPHIER_PIN_IECTRL_EXIST, + 21, UNIPHIER_PIN_DRV_2BIT, + 55, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(56, "RGMII0_RXCLK", UNIPHIER_PIN_IECTRL_EXIST, + 22, UNIPHIER_PIN_DRV_2BIT, + 56, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(57, "RGMII0_RXD0", UNIPHIER_PIN_IECTRL_EXIST, + 23, UNIPHIER_PIN_DRV_2BIT, + 57, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(58, "RGMII0_RXD1", UNIPHIER_PIN_IECTRL_EXIST, + 24, UNIPHIER_PIN_DRV_2BIT, + 58, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(59, "RGMII0_RXD2", UNIPHIER_PIN_IECTRL_EXIST, + 25, UNIPHIER_PIN_DRV_2BIT, + 59, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(60, "RGMII0_RXD3", UNIPHIER_PIN_IECTRL_EXIST, + 26, UNIPHIER_PIN_DRV_2BIT, + 60, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(61, "RGMII0_RXCTL", UNIPHIER_PIN_IECTRL_EXIST, + 27, UNIPHIER_PIN_DRV_2BIT, + 61, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(62, "RGMII0_TXCLK", UNIPHIER_PIN_IECTRL_EXIST, + 28, UNIPHIER_PIN_DRV_2BIT, + 62, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(63, "RGMII0_TXD0", UNIPHIER_PIN_IECTRL_EXIST, + 29, UNIPHIER_PIN_DRV_2BIT, + 63, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(64, "RGMII0_TXD1", UNIPHIER_PIN_IECTRL_EXIST, + 30, UNIPHIER_PIN_DRV_2BIT, + 64, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(65, "RGMII0_TXD2", UNIPHIER_PIN_IECTRL_EXIST, + 31, UNIPHIER_PIN_DRV_2BIT, + 65, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(66, "RGMII0_TXD3", UNIPHIER_PIN_IECTRL_EXIST, + 32, UNIPHIER_PIN_DRV_2BIT, + 66, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(67, "RGMII0_TXCTL", UNIPHIER_PIN_IECTRL_EXIST, + 33, UNIPHIER_PIN_DRV_2BIT, + 67, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(68, "MDC1", UNIPHIER_PIN_IECTRL_EXIST, + 34, UNIPHIER_PIN_DRV_2BIT, + 68, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(69, "MDIO1", UNIPHIER_PIN_IECTRL_EXIST, + 35, UNIPHIER_PIN_DRV_2BIT, + 69, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(70, "MDIO1_INTL", UNIPHIER_PIN_IECTRL_EXIST, + 36, UNIPHIER_PIN_DRV_2BIT, + 70, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(71, "PHYRSTL1", UNIPHIER_PIN_IECTRL_EXIST, + 37, UNIPHIER_PIN_DRV_2BIT, + 71, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(72, "RGMII1_RXCLK", UNIPHIER_PIN_IECTRL_EXIST, + 38, UNIPHIER_PIN_DRV_2BIT, + 72, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(73, "RGMII1_RXD0", UNIPHIER_PIN_IECTRL_EXIST, + 39, UNIPHIER_PIN_DRV_2BIT, + 73, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(74, "RGMII1_RXD1", UNIPHIER_PIN_IECTRL_EXIST, + 40, UNIPHIER_PIN_DRV_2BIT, + 74, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(75, "RGMII1_RXD2", UNIPHIER_PIN_IECTRL_EXIST, + 41, UNIPHIER_PIN_DRV_2BIT, + 75, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(76, "RGMII1_RXD3", UNIPHIER_PIN_IECTRL_EXIST, + 42, UNIPHIER_PIN_DRV_2BIT, + 76, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(77, "RGMII1_RXCTL", UNIPHIER_PIN_IECTRL_EXIST, + 43, UNIPHIER_PIN_DRV_2BIT, + 77, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(78, "RGMII1_TXCLK", UNIPHIER_PIN_IECTRL_EXIST, + 44, UNIPHIER_PIN_DRV_2BIT, + 78, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(79, "RGMII1_TXD0", UNIPHIER_PIN_IECTRL_EXIST, + 45, UNIPHIER_PIN_DRV_2BIT, + 79, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(80, "RGMII1_TXD1", UNIPHIER_PIN_IECTRL_EXIST, + 46, UNIPHIER_PIN_DRV_2BIT, + 80, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(81, "RGMII1_TXD2", UNIPHIER_PIN_IECTRL_EXIST, + 47, UNIPHIER_PIN_DRV_2BIT, + 81, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(82, "RGMII1_TXD3", UNIPHIER_PIN_IECTRL_EXIST, + 48, UNIPHIER_PIN_DRV_2BIT, + 82, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(83, "RGMII1_TXCTL", UNIPHIER_PIN_IECTRL_EXIST, + 49, UNIPHIER_PIN_DRV_2BIT, + 83, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(84, "USB0VBUS", UNIPHIER_PIN_IECTRL_EXIST, + 34, UNIPHIER_PIN_DRV_3BIT, + 84, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(85, "USB0OD", UNIPHIER_PIN_IECTRL_EXIST, + 35, UNIPHIER_PIN_DRV_3BIT, + 85, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(86, "USB1VBUS", UNIPHIER_PIN_IECTRL_EXIST, + 36, UNIPHIER_PIN_DRV_3BIT, + 86, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(87, "USB1OD", UNIPHIER_PIN_IECTRL_EXIST, + 37, UNIPHIER_PIN_DRV_3BIT, + 87, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(88, "USB2VBUS", UNIPHIER_PIN_IECTRL_EXIST, + 38, UNIPHIER_PIN_DRV_3BIT, + 88, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(89, "USB2OD", UNIPHIER_PIN_IECTRL_EXIST, + 39, UNIPHIER_PIN_DRV_3BIT, + 89, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(90, "USB3VBUS", UNIPHIER_PIN_IECTRL_EXIST, + 40, UNIPHIER_PIN_DRV_3BIT, + 90, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(91, "USB3OD", UNIPHIER_PIN_IECTRL_EXIST, + 41, UNIPHIER_PIN_DRV_3BIT, + 91, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(92, "TXD0", UNIPHIER_PIN_IECTRL_EXIST, + 42, UNIPHIER_PIN_DRV_3BIT, + 92, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(93, "RXD0", UNIPHIER_PIN_IECTRL_EXIST, + 43, UNIPHIER_PIN_DRV_3BIT, + 93, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(94, "TXD1", UNIPHIER_PIN_IECTRL_EXIST, + 44, UNIPHIER_PIN_DRV_3BIT, + 94, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(95, "RXD1", UNIPHIER_PIN_IECTRL_EXIST, + 45, UNIPHIER_PIN_DRV_3BIT, + 95, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(96, "TXD2", UNIPHIER_PIN_IECTRL_EXIST, + 46, UNIPHIER_PIN_DRV_3BIT, + 96, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(97, "RXD2", UNIPHIER_PIN_IECTRL_EXIST, + 47, UNIPHIER_PIN_DRV_3BIT, + 97, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(98, "TXD3", UNIPHIER_PIN_IECTRL_EXIST, + 48, UNIPHIER_PIN_DRV_3BIT, + 98, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(99, "RXD3", UNIPHIER_PIN_IECTRL_EXIST, + 49, UNIPHIER_PIN_DRV_3BIT, + 99, UNIPHIER_PIN_PULL_UP), + UNIPHIER_PINCTRL_PIN(100, "SPISYNC0", UNIPHIER_PIN_IECTRL_EXIST, + 50, UNIPHIER_PIN_DRV_3BIT, + 100, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(101, "SPISCLK0", UNIPHIER_PIN_IECTRL_EXIST, + 51, UNIPHIER_PIN_DRV_3BIT, + 101, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(102, "SPITXD0", UNIPHIER_PIN_IECTRL_EXIST, + 52, UNIPHIER_PIN_DRV_3BIT, + 102, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(103, "SPIRXD0", UNIPHIER_PIN_IECTRL_EXIST, + 53, UNIPHIER_PIN_DRV_3BIT, + 103, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(104, "SDA0", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(105, "SCL0", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(106, "SDA1", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(107, "SCL1", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(108, "SDA2", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(109, "SCL2", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(110, "SDA3", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(111, "SCL3", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(112, "SMTRST0", UNIPHIER_PIN_IECTRL_EXIST, + 54, UNIPHIER_PIN_DRV_3BIT, + 112, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(113, "SMTCMD0", UNIPHIER_PIN_IECTRL_EXIST, + 55, UNIPHIER_PIN_DRV_3BIT, + 113, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(114, "SMTD0", UNIPHIER_PIN_IECTRL_EXIST, + 56, UNIPHIER_PIN_DRV_3BIT, + 114, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(115, "SMTSEL0", UNIPHIER_PIN_IECTRL_EXIST, + 57, UNIPHIER_PIN_DRV_3BIT, + 115, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(116, "SMTCLK0CG", UNIPHIER_PIN_IECTRL_EXIST, + 58, UNIPHIER_PIN_DRV_3BIT, + 116, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(117, "SMTDET0", UNIPHIER_PIN_IECTRL_EXIST, + 59, UNIPHIER_PIN_DRV_3BIT, + 117, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(118, "SMTRST1", UNIPHIER_PIN_IECTRL_EXIST, + 60, UNIPHIER_PIN_DRV_3BIT, + 118, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(119, "SMTCMD1", UNIPHIER_PIN_IECTRL_EXIST, + 61, UNIPHIER_PIN_DRV_3BIT, + 119, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(120, "SMTD1", UNIPHIER_PIN_IECTRL_EXIST, + 62, UNIPHIER_PIN_DRV_3BIT, + 120, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(121, "SMTSEL1", UNIPHIER_PIN_IECTRL_EXIST, + 63, UNIPHIER_PIN_DRV_3BIT, + 121, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(122, "SMTCLK1CG", UNIPHIER_PIN_IECTRL_EXIST, + 64, UNIPHIER_PIN_DRV_3BIT, + 122, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(123, "SMTDET1", UNIPHIER_PIN_IECTRL_EXIST, + 65, UNIPHIER_PIN_DRV_3BIT, + 123, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(124, "SMTRST2", UNIPHIER_PIN_IECTRL_EXIST, + 66, UNIPHIER_PIN_DRV_3BIT, + 124, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(125, "SMTCMD2", UNIPHIER_PIN_IECTRL_EXIST, + 67, UNIPHIER_PIN_DRV_3BIT, + 125, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(126, "SMTD2", UNIPHIER_PIN_IECTRL_EXIST, + 68, UNIPHIER_PIN_DRV_3BIT, + 126, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(127, "SMTSEL2", UNIPHIER_PIN_IECTRL_EXIST, + 69, UNIPHIER_PIN_DRV_3BIT, + 127, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(128, "SMTCLK2CG", UNIPHIER_PIN_IECTRL_EXIST, + 70, UNIPHIER_PIN_DRV_3BIT, + 128, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(129, "SMTDET2", UNIPHIER_PIN_IECTRL_EXIST, + 71, UNIPHIER_PIN_DRV_3BIT, + 129, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(130, "CH0CLK", UNIPHIER_PIN_IECTRL_EXIST, + 72, UNIPHIER_PIN_DRV_3BIT, + 130, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(131, "CH0PSYNC", UNIPHIER_PIN_IECTRL_EXIST, + 73, UNIPHIER_PIN_DRV_3BIT, + 131, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(132, "CH0VAL", UNIPHIER_PIN_IECTRL_EXIST, + 74, UNIPHIER_PIN_DRV_3BIT, + 132, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(133, "CH0DATA", UNIPHIER_PIN_IECTRL_EXIST, + 75, UNIPHIER_PIN_DRV_3BIT, + 133, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(134, "CH1CLK", UNIPHIER_PIN_IECTRL_EXIST, + 76, UNIPHIER_PIN_DRV_3BIT, + 134, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(135, "CH1PSYNC", UNIPHIER_PIN_IECTRL_EXIST, + 77, UNIPHIER_PIN_DRV_3BIT, + 135, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(136, "CH1VAL", UNIPHIER_PIN_IECTRL_EXIST, + 78, UNIPHIER_PIN_DRV_3BIT, + 136, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(137, "CH1DATA", UNIPHIER_PIN_IECTRL_EXIST, + 79, UNIPHIER_PIN_DRV_3BIT, + 137, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(138, "CH2CLK", UNIPHIER_PIN_IECTRL_EXIST, + 80, UNIPHIER_PIN_DRV_3BIT, + 138, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(139, "CH2PSYNC", UNIPHIER_PIN_IECTRL_EXIST, + 81, UNIPHIER_PIN_DRV_3BIT, + 139, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(140, "CH2VAL", UNIPHIER_PIN_IECTRL_EXIST, + 82, UNIPHIER_PIN_DRV_3BIT, + 140, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(141, "CH2DATA", UNIPHIER_PIN_IECTRL_EXIST, + 83, UNIPHIER_PIN_DRV_3BIT, + 141, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(142, "HS0BCLKIN", UNIPHIER_PIN_IECTRL_EXIST, + 84, UNIPHIER_PIN_DRV_3BIT, + 142, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(143, "HS0SYNCIN", UNIPHIER_PIN_IECTRL_EXIST, + 85, UNIPHIER_PIN_DRV_3BIT, + 143, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(144, "HS0VALIN", UNIPHIER_PIN_IECTRL_EXIST, + 86, UNIPHIER_PIN_DRV_3BIT, + 144, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(145, "HS0DIN0", UNIPHIER_PIN_IECTRL_EXIST, + 87, UNIPHIER_PIN_DRV_3BIT, + 145, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(146, "HS0DIN1", UNIPHIER_PIN_IECTRL_EXIST, + 88, UNIPHIER_PIN_DRV_3BIT, + 146, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(147, "HS0DIN2", UNIPHIER_PIN_IECTRL_EXIST, + 89, UNIPHIER_PIN_DRV_3BIT, + 147, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(148, "HS0DIN3", UNIPHIER_PIN_IECTRL_EXIST, + 90, UNIPHIER_PIN_DRV_3BIT, + 148, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(149, "HS0DIN4", UNIPHIER_PIN_IECTRL_EXIST, + 91, UNIPHIER_PIN_DRV_3BIT, + 149, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(150, "HS0DIN5", UNIPHIER_PIN_IECTRL_EXIST, + 92, UNIPHIER_PIN_DRV_3BIT, + 150, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(151, "HS0DIN6", UNIPHIER_PIN_IECTRL_EXIST, + 93, UNIPHIER_PIN_DRV_3BIT, + 151, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(152, "HS0DIN7", UNIPHIER_PIN_IECTRL_EXIST, + 94, UNIPHIER_PIN_DRV_3BIT, + 152, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(153, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_EXIST, + 95, UNIPHIER_PIN_DRV_3BIT, + 153, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(154, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_EXIST, + 96, UNIPHIER_PIN_DRV_3BIT, + 154, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(155, "HS1VALIN", UNIPHIER_PIN_IECTRL_EXIST, + 97, UNIPHIER_PIN_DRV_3BIT, + 155, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(156, "HS1DIN0", UNIPHIER_PIN_IECTRL_EXIST, + 98, UNIPHIER_PIN_DRV_3BIT, + 156, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(157, "HS1DIN1", UNIPHIER_PIN_IECTRL_EXIST, + 99, UNIPHIER_PIN_DRV_3BIT, + 157, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(158, "HS1DIN2", UNIPHIER_PIN_IECTRL_EXIST, + 100, UNIPHIER_PIN_DRV_3BIT, + 158, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(159, "HS1DIN3", UNIPHIER_PIN_IECTRL_EXIST, + 101, UNIPHIER_PIN_DRV_3BIT, + 159, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(160, "HS1DIN4", UNIPHIER_PIN_IECTRL_EXIST, + 102, UNIPHIER_PIN_DRV_3BIT, + 160, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(161, "HS1DIN5", UNIPHIER_PIN_IECTRL_EXIST, + 103, UNIPHIER_PIN_DRV_3BIT, + 161, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(162, "HS1DIN6", UNIPHIER_PIN_IECTRL_EXIST, + 104, UNIPHIER_PIN_DRV_3BIT, + 162, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(163, "HS1DIN7", UNIPHIER_PIN_IECTRL_EXIST, + 105, UNIPHIER_PIN_DRV_3BIT, + 163, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(164, "LINKCLK", UNIPHIER_PIN_IECTRL_EXIST, + 106, UNIPHIER_PIN_DRV_3BIT, + 164, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(165, "LINKREQ", UNIPHIER_PIN_IECTRL_EXIST, + 107, UNIPHIER_PIN_DRV_3BIT, + 165, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(166, "LINKCTL0", UNIPHIER_PIN_IECTRL_EXIST, + 108, UNIPHIER_PIN_DRV_3BIT, + 166, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(167, "LINKCTL1", UNIPHIER_PIN_IECTRL_EXIST, + 109, UNIPHIER_PIN_DRV_3BIT, + 167, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(168, "LINKDT0", UNIPHIER_PIN_IECTRL_EXIST, + 110, UNIPHIER_PIN_DRV_3BIT, + 168, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(169, "LINKDT1", UNIPHIER_PIN_IECTRL_EXIST, + 111, UNIPHIER_PIN_DRV_3BIT, + 169, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(170, "LINKDT2", UNIPHIER_PIN_IECTRL_EXIST, + 112, UNIPHIER_PIN_DRV_3BIT, + 170, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(171, "LINKDT3", UNIPHIER_PIN_IECTRL_EXIST, + 113, UNIPHIER_PIN_DRV_3BIT, + 171, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(172, "LINKDT4", UNIPHIER_PIN_IECTRL_EXIST, + 114, UNIPHIER_PIN_DRV_3BIT, + 172, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(173, "LINKDT5", UNIPHIER_PIN_IECTRL_EXIST, + 115, UNIPHIER_PIN_DRV_3BIT, + 173, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(174, "LINKDT6", UNIPHIER_PIN_IECTRL_EXIST, + 116, UNIPHIER_PIN_DRV_3BIT, + 174, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(175, "LINKDT7", UNIPHIER_PIN_IECTRL_EXIST, + 117, UNIPHIER_PIN_DRV_3BIT, + 175, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(176, "H0RXDDCSDA", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(177, "H0RXDDCSCL", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(178, "H0RXHPDO", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(179, "H0RX5VDETI", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(180, "H0TXDDCSDA", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(181, "H0TXDDCSCL", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(182, "H0TXHPDI", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(183, "H1TXDDCSDA", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(184, "H1TXDDCSCL", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(185, "H1TXHPDI", UNIPHIER_PIN_IECTRL_EXIST, + -1, UNIPHIER_PIN_DRV_FIXED4, + -1, UNIPHIER_PIN_PULL_NONE), + UNIPHIER_PINCTRL_PIN(186, "AI1ADCCK", UNIPHIER_PIN_IECTRL_EXIST, + 118, UNIPHIER_PIN_DRV_3BIT, + 186, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(187, "AI1BCK", UNIPHIER_PIN_IECTRL_EXIST, + 119, UNIPHIER_PIN_DRV_3BIT, + 187, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(188, "AI1LRCK", UNIPHIER_PIN_IECTRL_EXIST, + 120, UNIPHIER_PIN_DRV_3BIT, + 188, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(189, "AI1D0", UNIPHIER_PIN_IECTRL_EXIST, + 121, UNIPHIER_PIN_DRV_3BIT, + 189, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(190, "AO1IEC", UNIPHIER_PIN_IECTRL_EXIST, + 122, UNIPHIER_PIN_DRV_3BIT, + 190, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(191, "AO2IEC", UNIPHIER_PIN_IECTRL_EXIST, + 123, UNIPHIER_PIN_DRV_3BIT, + 191, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(192, "AO2DACCK", UNIPHIER_PIN_IECTRL_EXIST, + 124, UNIPHIER_PIN_DRV_3BIT, + 192, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(193, "AO2BCK", UNIPHIER_PIN_IECTRL_EXIST, + 125, UNIPHIER_PIN_DRV_3BIT, + 193, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(194, "AO2LRCK", UNIPHIER_PIN_IECTRL_EXIST, + 126, UNIPHIER_PIN_DRV_3BIT, + 194, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(195, "AO2D0", UNIPHIER_PIN_IECTRL_EXIST, + 127, UNIPHIER_PIN_DRV_3BIT, + 195, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(196, "AO2D1", UNIPHIER_PIN_IECTRL_EXIST, + 128, UNIPHIER_PIN_DRV_3BIT, + 196, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(197, "AO2D2", UNIPHIER_PIN_IECTRL_EXIST, + 129, UNIPHIER_PIN_DRV_3BIT, + 197, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(198, "AO2D3", UNIPHIER_PIN_IECTRL_EXIST, + 130, UNIPHIER_PIN_DRV_3BIT, + 198, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(199, "AO3DACCK", UNIPHIER_PIN_IECTRL_EXIST, + 131, UNIPHIER_PIN_DRV_3BIT, + 199, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(200, "AO3BCK", UNIPHIER_PIN_IECTRL_EXIST, + 132, UNIPHIER_PIN_DRV_3BIT, + 200, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(201, "AO3LRCK", UNIPHIER_PIN_IECTRL_EXIST, + 133, UNIPHIER_PIN_DRV_3BIT, + 201, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(202, "AO3D0", UNIPHIER_PIN_IECTRL_EXIST, + 134, UNIPHIER_PIN_DRV_3BIT, + 202, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(203, "VI1CLK", UNIPHIER_PIN_IECTRL_EXIST, + 135, UNIPHIER_PIN_DRV_3BIT, + 203, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(204, "VI1G2", UNIPHIER_PIN_IECTRL_EXIST, + 136, UNIPHIER_PIN_DRV_3BIT, + 204, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(205, "VI1G3", UNIPHIER_PIN_IECTRL_EXIST, + 137, UNIPHIER_PIN_DRV_3BIT, + 205, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(206, "VI1G4", UNIPHIER_PIN_IECTRL_EXIST, + 138, UNIPHIER_PIN_DRV_3BIT, + 206, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(207, "VI1G5", UNIPHIER_PIN_IECTRL_EXIST, + 139, UNIPHIER_PIN_DRV_3BIT, + 207, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(208, "VI1G6", UNIPHIER_PIN_IECTRL_EXIST, + 140, UNIPHIER_PIN_DRV_3BIT, + 208, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(209, "VI1G7", UNIPHIER_PIN_IECTRL_EXIST, + 141, UNIPHIER_PIN_DRV_3BIT, + 209, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(210, "VI1G8", UNIPHIER_PIN_IECTRL_EXIST, + 142, UNIPHIER_PIN_DRV_3BIT, + 210, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(211, "VI1G9", UNIPHIER_PIN_IECTRL_EXIST, + 143, UNIPHIER_PIN_DRV_3BIT, + 211, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(212, "FANPWM", UNIPHIER_PIN_IECTRL_EXIST, + 144, UNIPHIER_PIN_DRV_3BIT, + 212, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(213, "CK27EXO", UNIPHIER_PIN_IECTRL_EXIST, + 145, UNIPHIER_PIN_DRV_3BIT, + 213, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(214, "CK27AO", UNIPHIER_PIN_IECTRL_EXIST, + 146, UNIPHIER_PIN_DRV_3BIT, + 214, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(215, "CK27EXI", UNIPHIER_PIN_IECTRL_EXIST, + 147, UNIPHIER_PIN_DRV_3BIT, + 215, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(216, "VEXCKA", UNIPHIER_PIN_IECTRL_EXIST, + 148, UNIPHIER_PIN_DRV_3BIT, + 216, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(217, "AEXCKA", UNIPHIER_PIN_IECTRL_EXIST, + 149, UNIPHIER_PIN_DRV_3BIT, + 217, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(218, "ASEL", UNIPHIER_PIN_IECTRL_EXIST, + 150, UNIPHIER_PIN_DRV_3BIT, + 218, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(219, "XIRQ0", UNIPHIER_PIN_IECTRL_EXIST, + 151, UNIPHIER_PIN_DRV_3BIT, + 219, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(220, "XIRQ1", UNIPHIER_PIN_IECTRL_EXIST, + 152, UNIPHIER_PIN_DRV_3BIT, + 220, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(221, "XIRQ2", UNIPHIER_PIN_IECTRL_EXIST, + 153, UNIPHIER_PIN_DRV_3BIT, + 221, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(222, "XIRQ3", UNIPHIER_PIN_IECTRL_EXIST, + 154, UNIPHIER_PIN_DRV_3BIT, + 222, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(223, "XIRQ4", UNIPHIER_PIN_IECTRL_EXIST, + 155, UNIPHIER_PIN_DRV_3BIT, + 223, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(224, "XIRQ5", UNIPHIER_PIN_IECTRL_EXIST, + 156, UNIPHIER_PIN_DRV_3BIT, + 224, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(225, "XIRQ6", UNIPHIER_PIN_IECTRL_EXIST, + 157, UNIPHIER_PIN_DRV_3BIT, + 225, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(226, "XIRQ7", UNIPHIER_PIN_IECTRL_EXIST, + 158, UNIPHIER_PIN_DRV_3BIT, + 226, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(227, "XIRQ8", UNIPHIER_PIN_IECTRL_EXIST, + 159, UNIPHIER_PIN_DRV_3BIT, + 227, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(228, "XIRQ9", UNIPHIER_PIN_IECTRL_EXIST, + 160, UNIPHIER_PIN_DRV_3BIT, + 228, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(229, "XIRQ10", UNIPHIER_PIN_IECTRL_EXIST, + 161, UNIPHIER_PIN_DRV_3BIT, + 229, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(230, "XIRQ11", UNIPHIER_PIN_IECTRL_EXIST, + 162, UNIPHIER_PIN_DRV_3BIT, + 230, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(231, "XIRQ12", UNIPHIER_PIN_IECTRL_EXIST, + 163, UNIPHIER_PIN_DRV_3BIT, + 231, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(232, "XIRQ13", UNIPHIER_PIN_IECTRL_EXIST, + 164, UNIPHIER_PIN_DRV_3BIT, + 232, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(233, "XIRQ14", UNIPHIER_PIN_IECTRL_EXIST, + 165, UNIPHIER_PIN_DRV_3BIT, + 233, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(234, "XIRQ15", UNIPHIER_PIN_IECTRL_EXIST, + 166, UNIPHIER_PIN_DRV_3BIT, + 234, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(235, "PORT00", UNIPHIER_PIN_IECTRL_EXIST, + 167, UNIPHIER_PIN_DRV_3BIT, + 235, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(236, "PORT01", UNIPHIER_PIN_IECTRL_EXIST, + 168, UNIPHIER_PIN_DRV_3BIT, + 236, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(237, "PORT02", UNIPHIER_PIN_IECTRL_EXIST, + 169, UNIPHIER_PIN_DRV_3BIT, + 237, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(238, "PORT03", UNIPHIER_PIN_IECTRL_EXIST, + 170, UNIPHIER_PIN_DRV_3BIT, + 238, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(239, "PORT04", UNIPHIER_PIN_IECTRL_EXIST, + 171, UNIPHIER_PIN_DRV_3BIT, + 239, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(240, "PORT05", UNIPHIER_PIN_IECTRL_EXIST, + 172, UNIPHIER_PIN_DRV_3BIT, + 240, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(241, "PORT06", UNIPHIER_PIN_IECTRL_EXIST, + 173, UNIPHIER_PIN_DRV_3BIT, + 241, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(242, "PORT07", UNIPHIER_PIN_IECTRL_EXIST, + 174, UNIPHIER_PIN_DRV_3BIT, + 242, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(243, "PORT10", UNIPHIER_PIN_IECTRL_EXIST, + 175, UNIPHIER_PIN_DRV_3BIT, + 243, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(244, "PORT11", UNIPHIER_PIN_IECTRL_EXIST, + 176, UNIPHIER_PIN_DRV_3BIT, + 244, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(245, "PORT12", UNIPHIER_PIN_IECTRL_EXIST, + 177, UNIPHIER_PIN_DRV_3BIT, + 245, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(246, "PORT13", UNIPHIER_PIN_IECTRL_EXIST, + 178, UNIPHIER_PIN_DRV_3BIT, + 246, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(247, "PORT14", UNIPHIER_PIN_IECTRL_EXIST, + 179, UNIPHIER_PIN_DRV_3BIT, + 247, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(248, "PORT15", UNIPHIER_PIN_IECTRL_EXIST, + 180, UNIPHIER_PIN_DRV_3BIT, + 248, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(249, "PORT16", UNIPHIER_PIN_IECTRL_EXIST, + 181, UNIPHIER_PIN_DRV_3BIT, + 249, UNIPHIER_PIN_PULL_DOWN), + UNIPHIER_PINCTRL_PIN(250, "PORT17", UNIPHIER_PIN_IECTRL_EXIST, + 182, UNIPHIER_PIN_DRV_3BIT, + 250, UNIPHIER_PIN_PULL_DOWN), +}; + +static const unsigned int emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38}; +static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned int emmc_dat8_pins[] = {39, 40, 41, 42}; +static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; +static const unsigned int ether_rgmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59, + 60, 61, 62, 63, 64, 65, 66, 67}; +static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0}; +static const unsigned int ether_rmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59, + 61, 63, 64, 67}; +static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1}; +static const unsigned int ether1_rgmii_pins[] = {68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 80, 81, + 82, 83}; +static const int ether1_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0}; +static const unsigned int ether1_rmii_pins[] = {68, 69, 70, 71, 72, 73, 74, 75, + 77, 79, 80, 83}; +static const int ether1_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1}; +static const unsigned int i2c0_pins[] = {104, 105}; +static const int i2c0_muxvals[] = {0, 0}; +static const unsigned int i2c1_pins[] = {106, 107}; +static const int i2c1_muxvals[] = {0, 0}; +static const unsigned int i2c2_pins[] = {108, 109}; +static const int i2c2_muxvals[] = {0, 0}; +static const unsigned int i2c3_pins[] = {110, 111}; +static const int i2c3_muxvals[] = {0, 0}; +static const unsigned int nand_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30}; +static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned int sd_pins[] = {43, 44, 45, 46, 47, 48, 49, 50, 51}; +static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned int system_bus_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14}; +static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0}; +static const unsigned int system_bus_cs1_pins[] = {15}; +static const int system_bus_cs1_muxvals[] = {0}; +static const unsigned int uart0_pins[] = {92, 93}; +static const int uart0_muxvals[] = {0, 0}; +static const unsigned int uart1_pins[] = {94, 95}; +static const int uart1_muxvals[] = {0, 0}; +static const unsigned int uart2_pins[] = {96, 97}; +static const int uart2_muxvals[] = {0, 0}; +static const unsigned int uart3_pins[] = {98, 99}; +static const int uart3_muxvals[] = {0, 0}; +static const unsigned int usb0_pins[] = {84, 85}; +static const int usb0_muxvals[] = {0, 0}; +static const unsigned int usb1_pins[] = {86, 87}; +static const int usb1_muxvals[] = {0, 0}; +static const unsigned int usb2_pins[] = {88, 89}; +static const int usb2_muxvals[] = {0, 0}; +static const unsigned int usb3_pins[] = {90, 91}; +static const int usb3_muxvals[] = {0, 0}; +static const unsigned int gpio_range0_pins[] = { + 235, 236, 237, 238, 239, 240, 241, 242, /* PORT0x */ + 243, 244, 245, 246, 247, 248, 249, 250, /* PORT1x */ + 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */ + 16, 17, 18, 19, 20, 21, 22, 23, /* PORT4x */ + 24, 25, 26, 27, 28, 29, 30, 31, /* PORT5x */ + 43, 44, 45, 46, 47, 48, 49, 50, /* PORT6x */ + 51, 52, 53, 54, 55, 56, 57, 58, /* PORT7x */ + 59, 60, 61, 62, 63, 64, 65, 66, /* PORT8x */ + 67, 68, 69, 70, 71, 72, 73, 74, /* PORT9x */ + 75, 76, 77, 78, 79, 80, 81, 82, /* PORT10x */ +}; +static const unsigned int gpio_range1_pins[] = { + 83, 84, 85, 86, 87, 88, 89, 90, /* PORT13x */ + 91, 92, 93, 94, 95, 96, 97, 98, /* PORT14x */ + 219, 220, 221, 222, 223, 224, 225, 226, /* XIRQ0-7 */ + 227, 228, 229, 230, 231, 232, 233, 234, /* XIRQ8-15 */ + 215, 216, 217, 218, 164, 165, 166, 167, /* XIRQ16-23 */ + 104, 105, 106, 107, 108, 109, 110, 111, /* PORT18x */ + 176, 177, 178, 179, 180, 181, 182, 183, /* PORT19x */ + 184, 185, /* PORT200-201 */ +}; +static const unsigned int gpio_range2_pins[] = { + 99, 100, 101, 102, 103, 112, 113, 114, /* PORT21x */ + 115, 116, 117, 118, 119, 120, 121, 122, /* PORT22x */ + 123, 124, 125, 126, 127, 128, 129, 130, /* PORT23x */ + 131, 132, 133, 134, 135, 136, 137, 138, /* PORT24x */ + 139, 140, 141, 142, 143, 144, 145, 146, /* PORT25x */ + 147, 148, 149, 150, 151, 152, 153, 154, /* PORT26x */ + 155, 156, 157, 158, 159, 160, 161, 162, /* PORT27x */ + 163, 164, 165, 166, 167, 168, 169, 170, /* PORT28x */ + 171, 172, 173, 174, 175, 186, 187, 188, /* PORT29x */ + 189, 190, 191, 192, 193, 194, 195, 196, /* PORT30x */ + 197, 198, 199, 200, 201, 202, 203, 204, /* PORT31x */ + 205, 206, 207, 208, 209, 210, 211, 212, /* PORT32x */ + 213, 214, 215, 216, 217, 218, 219, 220, /* PORT33x */ + 221, 222, 223, 224, 225, 226, 227, 228, /* PORT34x */ + 229, 230, 231, 232, 233, 234, /* PORT350-355 */ +}; + +static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { + UNIPHIER_PINCTRL_GROUP(emmc), + UNIPHIER_PINCTRL_GROUP(emmc_dat8), + UNIPHIER_PINCTRL_GROUP(ether_rgmii), + UNIPHIER_PINCTRL_GROUP(ether_rmii), + UNIPHIER_PINCTRL_GROUP(ether1_rgmii), + UNIPHIER_PINCTRL_GROUP(ether1_rmii), + UNIPHIER_PINCTRL_GROUP(i2c0), + UNIPHIER_PINCTRL_GROUP(i2c1), + UNIPHIER_PINCTRL_GROUP(i2c2), + UNIPHIER_PINCTRL_GROUP(i2c3), + UNIPHIER_PINCTRL_GROUP(nand), + UNIPHIER_PINCTRL_GROUP(sd), + UNIPHIER_PINCTRL_GROUP(system_bus), + UNIPHIER_PINCTRL_GROUP(system_bus_cs1), + UNIPHIER_PINCTRL_GROUP(uart0), + UNIPHIER_PINCTRL_GROUP(uart1), + UNIPHIER_PINCTRL_GROUP(uart2), + UNIPHIER_PINCTRL_GROUP(uart3), + UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb2), + UNIPHIER_PINCTRL_GROUP(usb3), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), +}; + +static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; +static const char * const ether_rgmii_groups[] = {"ether_rgmii"}; +static const char * const ether_rmii_groups[] = {"ether_rmii"}; +static const char * const ether1_rgmii_groups[] = {"ether1_rgmii"}; +static const char * const ether1_rmii_groups[] = {"ether1_rmii"}; +static const char * const i2c0_groups[] = {"i2c0"}; +static const char * const i2c1_groups[] = {"i2c1"}; +static const char * const i2c2_groups[] = {"i2c2"}; +static const char * const i2c3_groups[] = {"i2c3"}; +static const char * const nand_groups[] = {"nand"}; +static const char * const sd_groups[] = {"sd"}; +static const char * const system_bus_groups[] = {"system_bus", + "system_bus_cs1"}; +static const char * const uart0_groups[] = {"uart0"}; +static const char * const uart1_groups[] = {"uart1"}; +static const char * const uart2_groups[] = {"uart2"}; +static const char * const uart3_groups[] = {"uart3"}; +static const char * const usb0_groups[] = {"usb0"}; +static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb2_groups[] = {"usb2"}; +static const char * const usb3_groups[] = {"usb3"}; + +static const struct uniphier_pinmux_function uniphier_pxs3_functions[] = { + UNIPHIER_PINMUX_FUNCTION(emmc), + UNIPHIER_PINMUX_FUNCTION(ether_rgmii), + UNIPHIER_PINMUX_FUNCTION(ether_rmii), + UNIPHIER_PINMUX_FUNCTION(ether1_rgmii), + UNIPHIER_PINMUX_FUNCTION(ether1_rmii), + UNIPHIER_PINMUX_FUNCTION(i2c0), + UNIPHIER_PINMUX_FUNCTION(i2c1), + UNIPHIER_PINMUX_FUNCTION(i2c2), + UNIPHIER_PINMUX_FUNCTION(i2c3), + UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(sd), + UNIPHIER_PINMUX_FUNCTION(system_bus), + UNIPHIER_PINMUX_FUNCTION(uart0), + UNIPHIER_PINMUX_FUNCTION(uart1), + UNIPHIER_PINMUX_FUNCTION(uart2), + UNIPHIER_PINMUX_FUNCTION(uart3), + UNIPHIER_PINMUX_FUNCTION(usb0), + UNIPHIER_PINMUX_FUNCTION(usb1), + UNIPHIER_PINMUX_FUNCTION(usb2), + UNIPHIER_PINMUX_FUNCTION(usb3), +}; + +static int uniphier_pxs3_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + if (gpio_offset >= 120 && gpio_offset <= 143) { /* XIRQx */ + if (pin >= 219 && pin <= 234) + return 0; + + return 14; + } + + return 15; +} + +static struct uniphier_pinctrl_socdata uniphier_pxs3_pindata = { + .pins = uniphier_pxs3_pins, + .npins = ARRAY_SIZE(uniphier_pxs3_pins), + .groups = uniphier_pxs3_groups, + .groups_count = ARRAY_SIZE(uniphier_pxs3_groups), + .functions = uniphier_pxs3_functions, + .functions_count = ARRAY_SIZE(uniphier_pxs3_functions), + .get_gpio_muxval = uniphier_pxs3_get_gpio_muxval, + .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL, +}; + +static int uniphier_pxs3_pinctrl_probe(struct platform_device *pdev) +{ + return uniphier_pinctrl_probe(pdev, &uniphier_pxs3_pindata); +} + +static const struct of_device_id uniphier_pxs3_pinctrl_match[] = { + { .compatible = "socionext,uniphier-pxs3-pinctrl" }, + { /* sentinel */ } +}; + +static struct platform_driver uniphier_pxs3_pinctrl_driver = { + .probe = uniphier_pxs3_pinctrl_probe, + .driver = { + .name = "uniphier-pxs3-pinctrl", + .of_match_table = uniphier_pxs3_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, + }, +}; +builtin_platform_driver(uniphier_pxs3_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 37deaf615dcf..1af430d701be 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -532,67 +532,28 @@ static const unsigned usb1_pins[] = {43, 44}; static const int usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {114, 115}; static const int usb2_muxvals[] = {1, 1}; -static const unsigned port_range0_pins[] = { - 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */ - 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */ - 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */ - 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */ - 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */ - 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */ - 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */ - 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */ - 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */ - 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */ - 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */ - 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */ - 47, 127, 20, 56, 22, /* PORT120-124 */ +static const unsigned int gpio_range0_pins[] = { + 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */ + 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */ + 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */ + 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */ + 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */ + 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */ + 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */ + 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */ + 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */ + 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */ + 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */ + 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */ + 47, 127, 20, 56, 22, /* PORT120-124 */ }; -static const int port_range0_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */ - 15, 15, 15, 15, 15, /* PORT120-124 */ +static const unsigned int gpio_range1_pins[] = { + 116, 117, /* PORT130-131 */ }; -static const unsigned port_range1_pins[] = { - 116, 117, /* PORT130-131 */ -}; -static const int port_range1_muxvals[] = { - 15, 15, /* PORT130-131 */ -}; -static const unsigned port_range2_pins[] = { - 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */ -}; -static const int port_range2_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ -}; -static const unsigned port_range3_pins[] = { - 23, /* PORT166 */ -}; -static const int port_range3_muxvals[] = { - 15, /* PORT166 */ -}; -static const unsigned xirq_range0_pins[] = { - 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */ - 82, 87, 88, 50, 51, /* XIRQ8-12 */ -}; -static const int xirq_range0_muxvals[] = { - 0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */ - 14, 14, 14, 14, 14, /* XIRQ8-12 */ -}; -static const unsigned xirq_range1_pins[] = { - 52, 58, /* XIRQ14-15 */ -}; -static const int xirq_range1_muxvals[] = { - 14, 14, /* XIRQ14-15 */ +static const unsigned int gpio_range2_pins[] = { + 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */ + 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */ + 82, 87, 88, 50, 51, 23, 52, 58, /* XIRQ8-12, PORT165, XIRQ14-15 */ }; static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = { @@ -620,139 +581,9 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88), - UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89), - UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90), - UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91), - UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92), - UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93), - UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94), - UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range2, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range2, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range2, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range2, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range2, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range2, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range2, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range2, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range3, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), + UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; @@ -777,46 +608,6 @@ static const char * const uart3_groups[] = {"uart3"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; -static const char * const port_groups[] = { - "port00", "port01", "port02", "port03", - "port04", "port05", "port06", "port07", - "port10", "port11", "port12", "port13", - "port14", "port15", "port16", "port17", - "port20", "port21", "port22", "port23", - "port24", "port25", "port26", "port27", - "port30", "port31", "port32", "port33", - "port34", "port35", "port36", "port37", - "port40", "port41", "port42", "port43", - "port44", "port45", "port46", "port47", - "port50", "port51", "port52", "port53", - "port54", "port55", "port56", "port57", - "port60", "port61", "port62", "port63", - "port64", "port65", "port66", "port67", - "port70", "port71", "port72", "port73", - "port74", "port75", "port76", "port77", - "port80", "port81", "port82", "port83", - "port84", "port85", "port86", "port87", - "port90", "port91", "port92", "port93", - "port94", "port95", "port96", "port97", - "port100", "port101", "port102", "port103", - "port104", "port105", "port106", "port107", - "port110", "port111", "port112", "port113", - "port114", "port115", "port116", "port117", - "port120", "port121", "port122", "port123", - "port124", "port125", "port126", "port127", - "port130", "port131", "port132", "port133", - "port134", "port135", "port136", "port137", - "port140", "port141", "port142", "port143", - "port144", "port145", "port146", "port147", - /* port150-164 missing */ - /* none */ "port165", -}; -static const char * const xirq_groups[] = { - "xirq0", "xirq1", "xirq2", "xirq3", - "xirq4", "xirq5", "xirq6", "xirq7", - "xirq8", "xirq9", "xirq10", "xirq11", - "xirq12", /* none*/ "xirq14", "xirq15", -}; static const struct uniphier_pinmux_function uniphier_sld8_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), @@ -836,10 +627,22 @@ static const struct uniphier_pinmux_function uniphier_sld8_functions[] = { UNIPHIER_PINMUX_FUNCTION(usb0), UNIPHIER_PINMUX_FUNCTION(usb1), UNIPHIER_PINMUX_FUNCTION(usb2), - UNIPHIER_PINMUX_FUNCTION(port), - UNIPHIER_PINMUX_FUNCTION(xirq), }; +static int uniphier_sld8_get_gpio_muxval(unsigned int pin, + unsigned int gpio_offset) +{ + switch (gpio_offset) { + case 120 ... 127: /* XIRQ0-XIRQ7 */ + return 0; + case 128 ... 132: /* XIRQ8-12 */ + case 134 ... 135: /* XIRQ14-15 */ + return 14; + default: + return 15; + } +} + static struct uniphier_pinctrl_socdata uniphier_sld8_pindata = { .pins = uniphier_sld8_pins, .npins = ARRAY_SIZE(uniphier_sld8_pins), @@ -847,6 +650,7 @@ static struct uniphier_pinctrl_socdata uniphier_sld8_pindata = { .groups_count = ARRAY_SIZE(uniphier_sld8_groups), .functions = uniphier_sld8_functions, .functions_count = ARRAY_SIZE(uniphier_sld8_functions), + .get_gpio_muxval = uniphier_sld8_get_gpio_muxval, .caps = 0, }; @@ -865,6 +669,7 @@ static struct platform_driver uniphier_sld8_pinctrl_driver = { .driver = { .name = "uniphier-sld8-pinctrl", .of_match_table = uniphier_sld8_pinctrl_match, + .pm = &uniphier_pinctrl_pm_ops, }, }; builtin_platform_driver(uniphier_sld8_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 6f2f33bf788f..c075ecb8e5db 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -25,7 +25,7 @@ struct platform_device; /* input enable control register bit */ #define UNIPHIER_PIN_IECTRL_SHIFT 0 -#define UNIPHIER_PIN_IECTRL_BITS 8 +#define UNIPHIER_PIN_IECTRL_BITS 3 #define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \ - 1) @@ -62,6 +62,7 @@ struct platform_device; #endif #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK) +#define UNIPHIER_PIN_IECTRL_EXIST 0 /* drive control type */ enum uniphier_pin_drv_type { @@ -131,18 +132,11 @@ static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data) UNIPHIER_PIN_PULL_DIR_MASK; } -enum uniphier_pinmux_gpio_range_type { - UNIPHIER_PINMUX_GPIO_RANGE_PORT, - UNIPHIER_PINMUX_GPIO_RANGE_IRQ, - UNIPHIER_PINMUX_GPIO_RANGE_NONE, -}; - struct uniphier_pinctrl_group { const char *name; const unsigned *pins; unsigned num_pins; const int *muxvals; - enum uniphier_pinmux_gpio_range_type range_type; }; struct uniphier_pinmux_function { @@ -158,6 +152,7 @@ struct uniphier_pinctrl_socdata { int groups_count; const struct uniphier_pinmux_function *functions; int functions_count; + int (*get_gpio_muxval)(unsigned int pin, unsigned int gpio_offset); unsigned int caps; #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1) #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0) @@ -170,33 +165,22 @@ struct uniphier_pinctrl_socdata { .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \ } -#define __UNIPHIER_PINCTRL_GROUP(grp, type) \ +#define __UNIPHIER_PINCTRL_GROUP(grp, mux) \ { \ .name = #grp, \ .pins = grp##_pins, \ .num_pins = ARRAY_SIZE(grp##_pins), \ - .muxvals = grp##_muxvals + \ - BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ - ARRAY_SIZE(grp##_muxvals)), \ - .range_type = type, \ + .muxvals = mux, \ } #define UNIPHIER_PINCTRL_GROUP(grp) \ - __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE) - -#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \ - __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT) - -#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \ - __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ) + __UNIPHIER_PINCTRL_GROUP(grp, \ + grp##_muxvals + \ + BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \ + ARRAY_SIZE(grp##_muxvals))) -#define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \ - { \ - .name = #grp, \ - .pins = array##_pins + ofst, \ - .num_pins = 1, \ - .muxvals = array##_muxvals + ofst, \ - } +#define UNIPHIER_PINCTRL_GROUP_GPIO(grp) \ + __UNIPHIER_PINCTRL_GROUP(grp, NULL) #define UNIPHIER_PINMUX_FUNCTION(func) \ { \ @@ -208,4 +192,6 @@ struct uniphier_pinctrl_socdata { int uniphier_pinctrl_probe(struct platform_device *pdev, struct uniphier_pinctrl_socdata *socdata); +extern const struct dev_pm_ops uniphier_pinctrl_pm_ops; + #endif /* __PINCTRL_UNIPHIER_H__ */ diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c index c207e60b734f..d73956bdc211 100644 --- a/drivers/pinctrl/vt8500/pinctrl-wmt.c +++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c @@ -163,7 +163,7 @@ static int wmt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops wmt_pinmux_ops = { +static const struct pinmux_ops wmt_pinmux_ops = { .get_functions_count = wmt_pmx_get_functions_count, .get_function_name = wmt_pmx_get_function_name, .get_function_groups = wmt_pmx_get_function_groups, @@ -409,7 +409,7 @@ fail: return err; } -static struct pinctrl_ops wmt_pctl_ops = { +static const struct pinctrl_ops wmt_pctl_ops = { .get_groups_count = wmt_get_groups_count, .get_group_name = wmt_get_group_name, .get_group_pins = wmt_get_group_pins, @@ -472,7 +472,7 @@ static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, return 0; } -static struct pinconf_ops wmt_pinconf_ops = { +static const struct pinconf_ops wmt_pinconf_ops = { .pin_config_get = wmt_pinconf_get, .pin_config_set = wmt_pinconf_set, }; @@ -546,7 +546,7 @@ static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset, return pinctrl_gpio_direction_output(chip->base + offset); } -static struct gpio_chip wmt_gpio_chip = { +static const struct gpio_chip wmt_gpio_chip = { .label = "gpio-wmt", .owner = THIS_MODULE, .request = gpiochip_generic_request, diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c index f828ee340a98..ded366bb6564 100644 --- a/drivers/pinctrl/zte/pinctrl-zx.c +++ b/drivers/pinctrl/zte/pinctrl-zx.c @@ -295,8 +295,7 @@ static int zx_pinctrl_build_state(struct platform_device *pdev) pctldev->num_groups = ngroups; /* Build function list from pin mux functions */ - functions = devm_kzalloc(&pdev->dev, info->npins * sizeof(*functions), - GFP_KERNEL); + functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL); if (!functions) return -ENOMEM; @@ -367,8 +366,10 @@ static int zx_pinctrl_build_state(struct platform_device *pdev) func->num_group_names * sizeof(*func->group_names), GFP_KERNEL); - if (!func->group_names) + if (!func->group_names) { + kfree(functions); return -ENOMEM; + } } group = func->group_names; diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h index d33f17c8a515..b8ff8824e21b 100644 --- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h @@ -98,6 +98,8 @@ #define PMIC_GPIO_FUNC_PAIRED "paired" #define PMIC_GPIO_FUNC_FUNC1 "func1" #define PMIC_GPIO_FUNC_FUNC2 "func2" +#define PMIC_GPIO_FUNC_FUNC3 "func3" +#define PMIC_GPIO_FUNC_FUNC4 "func4" #define PMIC_GPIO_FUNC_DTEST1 "dtest1" #define PMIC_GPIO_FUNC_DTEST2 "dtest2" #define PMIC_GPIO_FUNC_DTEST3 "dtest3" diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h index b7aa3646208b..ceb672305f59 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -66,7 +66,8 @@ #define EXYNOS_PIN_FUNC_4 4 #define EXYNOS_PIN_FUNC_5 5 #define EXYNOS_PIN_FUNC_6 6 -#define EXYNOS_PIN_FUNC_F 0xf +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT /* Drive strengths for Exynos7 FSYS1 block */ #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h index e5b1716f98cc..7fa5d87190c2 100644 --- a/include/linux/pinctrl/machine.h +++ b/include/linux/pinctrl/machine.h @@ -152,12 +152,12 @@ struct pinctrl_map { #ifdef CONFIG_PINCTRL -extern int pinctrl_register_mappings(struct pinctrl_map const *map, +extern int pinctrl_register_mappings(const struct pinctrl_map *map, unsigned num_maps); extern void pinctrl_provide_dummies(void); #else -static inline int pinctrl_register_mappings(struct pinctrl_map const *map, +static inline int pinctrl_register_mappings(const struct pinctrl_map *map, unsigned num_maps) { return 0; diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index e91d1b6a260d..5d8bc7f21c2a 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -86,6 +86,7 @@ * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power * supplies, the argument to this parameter (on a custom format) tells * the driver which alternative power source to use. + * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state. * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to * this parameter (on a custom format) tells the driver which alternative * slew rate to use. @@ -114,6 +115,7 @@ enum pin_config_param { PIN_CONFIG_OUTPUT_ENABLE, PIN_CONFIG_OUTPUT, PIN_CONFIG_POWER_SOURCE, + PIN_CONFIG_SLEEP_HARDWARE_STATE, PIN_CONFIG_SLEW_RATE, PIN_CONFIG_END = 0x7F, PIN_CONFIG_MAX = 0xFF, |