Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform support updates from Kevin Hilman:
 "Our SoC branch usually contains expanded support for new SoCs and
  other core platform code.  Some highlights from this round:

   - sunxi: SMP support for A23 SoC
   - socpga: big-endian support
   - pxa: conversion to common clock framework
   - bcm: SMP support for BCM63138
   - imx: support new I.MX7D SoC
   - zte: basic support for ZX296702 SoC"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
  ARM: zx: Add basic defconfig support for ZX296702
  ARM: dts: zx: add an initial zx296702 dts and doc
  clk: zx: add clock support to zx296702
  dt-bindings: Add #defines for ZTE ZX296702 clocks
  ARM: socfpga: fix build error due to secondary_startup
  MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
  ARM: ep93xx: simone: support for SPI-based MMC/SD cards
  MAINTAINERS: update Shawn's email to use kernel.org one
  ARM: socfpga: support suspend to ram
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
  ARM: EXYNOS: register power domain driver from core_initcall
  ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
  ARM: SAMSUNG: Constify platform_device_id
  ARM: EXYNOS: Constify irq_domain_ops
  ARM: EXYNOS: add coupled cpuidle support for Exynos3250
  ARM: EXYNOS: add exynos_get_boot_addr() helper
  ARM: EXYNOS: add exynos_set_boot_addr() helper
  ARM: EXYNOS: make exynos_core_restart() less verbose
  ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
  ...

1 files changed, 0 insertions, 75 deletions

diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
deleted file mode 100644
index df12b5307175..000000000000
--- a/arch/arm/mach-imx/clk.c
+++ /dev/null
@@ -1,75 +0,0 @@
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include "clk.h"
-
-DEFINE_SPINLOCK(imx_ccm_lock);
-
-void __init imx_check_clocks(struct clk *clks[], unsigned int count)
-{
-	unsigned i;
-
-	for (i = 0; i < count; i++)
-		if (IS_ERR(clks[i]))
-			pr_err("i.MX clk %u: register failed with %ld\n",
-			       i, PTR_ERR(clks[i]));
-}
-
-static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
-{
-	struct of_phandle_args phandle;
-	struct clk *clk = ERR_PTR(-ENODEV);
-	char *path;
-
-	path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
-	if (!path)
-		return ERR_PTR(-ENOMEM);
-
-	phandle.np = of_find_node_by_path(path);
-	kfree(path);
-
-	if (phandle.np) {
-		clk = of_clk_get_from_provider(&phandle);
-		of_node_put(phandle.np);
-	}
-	return clk;
-}
-
-struct clk * __init imx_obtain_fixed_clock(
-			const char *name, unsigned long rate)
-{
-	struct clk *clk;
-
-	clk = imx_obtain_fixed_clock_from_dt(name);
-	if (IS_ERR(clk))
-		clk = imx_clk_fixed(name, rate);
-	return clk;
-}
-
-/*
- * This fixups the register CCM_CSCMR1 write value.
- * The write/read/divider values of the aclk_podf field
- * of that register have the relationship described by
- * the following table:
- *
- * write value       read value        divider
- * 3b'000            3b'110            7
- * 3b'001            3b'111            8
- * 3b'010            3b'100            5
- * 3b'011            3b'101            6
- * 3b'100            3b'010            3
- * 3b'101            3b'011            4
- * 3b'110            3b'000            1
- * 3b'111            3b'001            2(default)
- *
- * That's why we do the xor operation below.
- */
-#define CSCMR1_FIXUP	0x00600000
-
-void imx_cscmr1_fixup(u32 *val)
-{
-	*val ^= CSCMR1_FIXUP;
-	return;
-}