diff options
| author | Mark Salter <msalter@redhat.com> | 2012-08-15 11:52:01 -0400 |
|---|---|---|
| committer | Mark Salter <msalter@redhat.com> | 2012-08-15 12:26:54 -0400 |
| commit | 6330c790dae1229bb33571c48984ca42a8a4c250 (patch) | |
| tree | b1a2c54ac6dd5bda4f2b167bf80230a2de889ee9 /arch/c6x/include | |
| parent | 28a33cbc24e4256c143dce96c7d93bf423229f92 (diff) | |
| download | linux-6330c790dae1229bb33571c48984ca42a8a4c250.tar.gz linux-6330c790dae1229bb33571c48984ca42a8a4c250.tar.xz | |
C6X: add Lx_CACHE_SHIFT defines
C6X currently lacks Lx_CACHE_SHIFT defines which are needed in a
few places in the generic kernel. This patch adds _SHIFT defines
for the various caches and bases the Lx_CACHE_BYTES defines on
them.
Signed-off-by: Mark Salter <msalter@redhat.com>
Diffstat (limited to 'arch/c6x/include')
| -rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h @@ -1,7 +1,7 @@ /* * Port on Texas Instruments TMS320C6x architecture * - * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated + * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) * * This program is free software; you can redistribute it and/or modify @@ -16,9 +16,14 @@ /* * Cache line size */ -#define L1D_CACHE_BYTES 64 -#define L1P_CACHE_BYTES 32 -#define L2_CACHE_BYTES 128 +#define L1D_CACHE_SHIFT 6 +#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) + +#define L1P_CACHE_SHIFT 5 +#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) + +#define L2_CACHE_SHIFT 7 +#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) /* * L2 used as cache @@ -29,7 +34,8 @@ * For practical reasons the L1_CACHE_BYTES defines should not be smaller than * the L2 line size */ -#define L1_CACHE_BYTES L2_CACHE_BYTES +#define L1_CACHE_SHIFT L2_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L2_CACHE_ALIGN_LOW(x) \ (((x) & ~(L2_CACHE_BYTES - 1))) |