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author | Ralf Baechle <ralf@linux-mips.org> | 2015-04-13 16:03:32 +0200 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-13 16:03:32 +0200 |
commit | 3e20a26b02bd4f24945c87407df51948dd488620 (patch) | |
tree | f466d3b2a47a98ec2910724e17ee2f3a93c1a49e /arch/mips/include/asm/pgtable-32.h | |
parent | 98b0429b7abd5c05efdb23f3eba02ec3f696748e (diff) | |
parent | 5306a5450824691e27d68f711758515debedeeac (diff) | |
download | linux-3e20a26b02bd4f24945c87407df51948dd488620.tar.gz linux-3e20a26b02bd4f24945c87407df51948dd488620.tar.xz |
Merge branch '4.0-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm/pgtable-32.h')
-rw-r--r-- | arch/mips/include/asm/pgtable-32.h | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index a6be006b6f75..7d56686c0e62 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -105,13 +105,16 @@ static inline void pmd_clear(pmd_t *pmdp) #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) #define pte_page(x) pfn_to_page(pte_pfn(x)) -#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) +#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT)) static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) { pte_t pte; - pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); - pte.pte_low = pgprot_val(prot); + + pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) | + (pgprot_val(prot) & ~_PFNX_MASK); + pte.pte_high = (pfn << _PFN_SHIFT) | + (pgprot_val(prot) & ~_PFN_MASK); return pte; } @@ -166,9 +169,9 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) /* Swap entries must have VALID and GLOBAL bits cleared. */ -#define __swp_type(x) (((x).val >> 2) & 0x1f) -#define __swp_offset(x) ((x).val >> 7) -#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) +#define __swp_type(x) (((x).val >> 4) & 0x1f) +#define __swp_offset(x) ((x).val >> 9) +#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) |