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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2015-05-25 22:39:50 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-06-01 16:53:55 +0200 |
| commit | 08b085a07efe12568d86dff064e6f089e2971744 (patch) | |
| tree | 10b738bac955c058ad06db2955aae4b0a69208ad /drivers/gpio/gpio-crystalcove.c | |
| parent | b6ac1280b6969607c5a01e316cc4ab693490c333 (diff) | |
| download | linux-08b085a07efe12568d86dff064e6f089e2971744.tar.gz linux-08b085a07efe12568d86dff064e6f089e2971744.tar.xz | |
gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs
0x3 only masks two bits, but three bits have to be allowed. This fixes
GPHY0 LED2 (which is the highest bit of phy2) on my board.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-crystalcove.c')
0 files changed, 0 insertions, 0 deletions