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| author | Yixun Lan <yixun.lan@amlogic.com> | 2017-11-07 22:12:23 +0800 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2017-11-27 14:33:38 +0100 |
| commit | 75eccf5ed83250c0aeaeeb76f7288254ac0a87b4 (patch) | |
| tree | 7603ed91f756fa2b47e2e6f05b64b7a0e35c7f9c /drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
| download | linux-75eccf5ed83250c0aeaeeb76f7288254ac0a87b4.tar.gz linux-75eccf5ed83250c0aeaeeb76f7288254ac0a87b4.tar.xz | |
clk: meson: gxbb: fix wrong clock for SARADC/SANA
According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].
Test passed at gxl-s905x-p212 board.
The following published datasheets are wrong and should be updated
[1] GXBB v1.1.4
[2] GXL v0.3_20170314
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Tested-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c')
0 files changed, 0 insertions, 0 deletions