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| author | Ernst Sjöstrand <ernstp@gmail.com> | 2017-11-19 18:52:46 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:48:00 -0500 |
| commit | 8cdbad98c52380bde20ea5753533640d2cdcc005 (patch) | |
| tree | cb4b476b41cf3ecc48a092ba78ced093fe692a9b /drivers/gpu/drm/amd/amdgpu/si_dpm.c | |
| parent | 47e8788b4924b0e3348caf4ad08de5a162bfc4cd (diff) | |
| download | linux-8cdbad98c52380bde20ea5753533640d2cdcc005.tar.gz linux-8cdbad98c52380bde20ea5753533640d2cdcc005.tar.xz | |
drm/amd/powerplay: Followup fixes to mc_reg_address
This is a followup to:
drm/amd/powerplay: Fix buffer overflows with mc_reg_address
Rework *_set_mc_special_registers for the other architectures to
use the same logic as the first patch. This allows the last entry
of the array to be filled without an error message for example.
This doesn't fix any known problems, perhaps avoided by luck.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/si_dpm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/si_dpm.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index 51fd0c9a20a5..299cb3161b2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -5845,9 +5845,9 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); j++; + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) return -EINVAL; - temp_reg = RREG32(MC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; @@ -5859,18 +5859,16 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) table->mc_reg_table_entry[k].mc_data[j] = (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; } break; case MC_SEQ_RESERVE_M: @@ -5882,8 +5880,6 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; default: break; |