diff options
| author | Ding Wang <Ding.Wang@amd.com> | 2017-01-10 12:47:37 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:09:30 -0400 |
| commit | 0ea9e02af5572323f79b493ec8d6bfa55effb2f7 (patch) | |
| tree | df6aa51946136769d7abe223ab25f2fd0e08e402 /drivers/gpu/drm/amd | |
| parent | 3e183c5f083125986dd0cd0ab609252349983f0e (diff) | |
| download | linux-0ea9e02af5572323f79b493ec8d6bfa55effb2f7.tar.gz linux-0ea9e02af5572323f79b493ec8d6bfa55effb2f7.tar.xz | |
drm/amd/display: Use DTO as clock on DP if not
Use DVO as pixel clock for DP before enabling link
PHY. Otherwise, when switching from HDMI passive dongle
to DP on the same connector, the PHY PLL is used as
pixel clock, and CRTC would stop working.
Signed-off-by: Ding Wang <Ding.Wang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index da49be0672d7..55d96656e54b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -61,6 +61,31 @@ void dp_enable_link_phy( { struct link_encoder *link_enc = link->link_enc; + struct pipe_ctx *pipes = + link->dc->current_context->res_ctx.pipe_ctx; + struct clock_source *dp_cs = + link->dc->res_pool->dp_clock_source; + unsigned int i; + /* If the current pixel clock source is not DTO(happens after + * switching from HDMI passive dongle to DP on the same connector), + * switch the pixel clock source to DTO. + */ + for (i = 0; i < MAX_PIPES; i++) { + if (pipes[i].stream != NULL && + pipes[i].stream->sink != NULL && + pipes[i].stream->sink->link == link) { + if (pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { + pipes[i].clock_source = dp_cs; + pipes[i].pix_clk_params.requested_pix_clk = + pipes[i].stream->public.timing.pix_clk_khz; + pipes[i].clock_source->funcs->program_pix_clk( + pipes[i].clock_source, + &pipes[i].pix_clk_params, + &pipes[i].pll_settings); + } + } + } + if (dc_is_dp_sst_signal(signal)) { if (signal == SIGNAL_TYPE_EDP) { link_enc->funcs->power_control(link_enc, true); |