diff options
| author | Lendacky, Thomas <Thomas.Lendacky@amd.com> | 2017-06-28 13:43:18 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-06-29 15:14:19 -0400 |
| commit | 7e1e6b86a5d96ca13834fbc6b6e54a9228f308e1 (patch) | |
| tree | c53ead63dc615f9f12b00300ae3a12c871b31dc6 /drivers/net/ethernet/amd/xgbe/xgbe-common.h | |
| parent | 9916716a1bb677be8371f602f53989bf04a70d7f (diff) | |
| download | linux-7e1e6b86a5d96ca13834fbc6b6e54a9228f308e1.tar.gz linux-7e1e6b86a5d96ca13834fbc6b6e54a9228f308e1.tar.xz | |
amd-xgbe: Simplify the burst length settings
Currently the driver hardcodes the PBLx8 setting. Remove the need for
specifying the PBLx8 setting and automatically calculate based on the
specified PBL value. Since the PBLx8 setting applies to both Tx and Rx
use the same PBL value for both of them.
Also, the driver currently uses a bit field to set the AXI master burst
len setting. Change to the full bit field range and set the burst length
based on the specified value.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/amd/xgbe/xgbe-common.h')
| -rw-r--r-- | drivers/net/ethernet/amd/xgbe/xgbe-common.h | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h index dc098832e0fe..6b5c72d27655 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h @@ -137,12 +137,19 @@ #define DMA_MR_SWR_WIDTH 1 #define DMA_SBMR_EAME_INDEX 11 #define DMA_SBMR_EAME_WIDTH 1 -#define DMA_SBMR_BLEN_256_INDEX 7 -#define DMA_SBMR_BLEN_256_WIDTH 1 +#define DMA_SBMR_BLEN_INDEX 1 +#define DMA_SBMR_BLEN_WIDTH 7 #define DMA_SBMR_UNDEF_INDEX 0 #define DMA_SBMR_UNDEF_WIDTH 1 /* DMA register values */ +#define DMA_SBMR_BLEN_256 256 +#define DMA_SBMR_BLEN_128 128 +#define DMA_SBMR_BLEN_64 64 +#define DMA_SBMR_BLEN_32 32 +#define DMA_SBMR_BLEN_16 16 +#define DMA_SBMR_BLEN_8 8 +#define DMA_SBMR_BLEN_4 4 #define DMA_DSR_RPS_WIDTH 4 #define DMA_DSR_TPS_WIDTH 4 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) |