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| author | Josh Poimboeuf <jpoimboe@redhat.com> | 2016-07-28 19:14:59 -0500 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2016-07-29 16:57:16 +0200 |
| commit | 8d94c2f9198301bd78feb1d9ad6c08a8ee7b5d1c (patch) | |
| tree | 1b30d92d631bb98d881de97adba70f922c839659 /tools/objtool/arch/x86/insn/insn.c | |
| parent | 6d01f28bc08814abc7b8f8973cc71195537f4c80 (diff) | |
| download | linux-8d94c2f9198301bd78feb1d9ad6c08a8ee7b5d1c.tar.gz linux-8d94c2f9198301bd78feb1d9ad6c08a8ee7b5d1c.tar.xz | |
objtool: Resync x86 instruction decoder with the kernel's
This fixes the following warning:
Warning: objtool: x86 instruction decoder differs from kernel
Unfortunately we have three identical copies of the x86 instruction
decoder in the kernel tree that have to be manually kept in sync.
It's on my TODO list to at least library-ize the ones in the tools
subdir so we'd only have two of them instead of three. In the meantime,
here's another manual sync.
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Fixes: c61f4d5ebaf0 ("perf tools: Add AVX-512 support to the instruction decoder used by Intel PT")
Link: http://lkml.kernel.org/r/d7f74b4d91fed25b0be33cd5c86f5131fa1a7529.1469751119.git.jpoimboe@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'tools/objtool/arch/x86/insn/insn.c')
| -rw-r--r-- | tools/objtool/arch/x86/insn/insn.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/tools/objtool/arch/x86/insn/insn.c b/tools/objtool/arch/x86/insn/insn.c index 9f26eae6c9f0..ca983e2bea8b 100644 --- a/tools/objtool/arch/x86/insn/insn.c +++ b/tools/objtool/arch/x86/insn/insn.c @@ -155,14 +155,24 @@ found: /* * In 32-bits mode, if the [7:6] bits (mod bits of * ModRM) on the second byte are not 11b, it is - * LDS or LES. + * LDS or LES or BOUND. */ if (X86_MODRM_MOD(b2) != 3) goto vex_end; } insn->vex_prefix.bytes[0] = b; insn->vex_prefix.bytes[1] = b2; - if (inat_is_vex3_prefix(attr)) { + if (inat_is_evex_prefix(attr)) { + b2 = peek_nbyte_next(insn_byte_t, insn, 2); + insn->vex_prefix.bytes[2] = b2; + b2 = peek_nbyte_next(insn_byte_t, insn, 3); + insn->vex_prefix.bytes[3] = b2; + insn->vex_prefix.nbytes = 4; + insn->next_byte += 4; + if (insn->x86_64 && X86_VEX_W(b2)) + /* VEX.W overrides opnd_size */ + insn->opnd_bytes = 8; + } else if (inat_is_vex3_prefix(attr)) { b2 = peek_nbyte_next(insn_byte_t, insn, 2); insn->vex_prefix.bytes[2] = b2; insn->vex_prefix.nbytes = 3; @@ -221,7 +231,9 @@ void insn_get_opcode(struct insn *insn) m = insn_vex_m_bits(insn); p = insn_vex_p_bits(insn); insn->attr = inat_get_avx_attribute(op, m, p); - if (!inat_accept_vex(insn->attr) && !inat_is_group(insn->attr)) + if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) || + (!inat_accept_vex(insn->attr) && + !inat_is_group(insn->attr))) insn->attr = 0; /* This instruction is bad */ goto end; /* VEX has only 1 byte for opcode */ } |