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Diffstat (limited to 'drivers/gpu/drm/stm')
-rw-r--r--drivers/gpu/drm/stm/drv.c20
-rw-r--r--drivers/gpu/drm/stm/dw_mipi_dsi-stm.c53
-rw-r--r--drivers/gpu/drm/stm/ltdc.c118
-rw-r--r--drivers/gpu/drm/stm/ltdc.h1
4 files changed, 165 insertions, 27 deletions
diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
index 8fe954c27fba..8bc7e8418b8d 100644
--- a/drivers/gpu/drm/stm/drv.c
+++ b/drivers/gpu/drm/stm/drv.c
@@ -31,6 +31,24 @@ static const struct drm_mode_config_funcs drv_mode_config_funcs = {
.atomic_commit = drm_atomic_helper_commit,
};
+static int stm_gem_cma_dumb_create(struct drm_file *file,
+ struct drm_device *dev,
+ struct drm_mode_create_dumb *args)
+{
+#ifdef CONFIG_MMU
+ unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+
+ /*
+ * in order to optimize data transfer, pitch is aligned on
+ * 128 bytes, height is aligned on 4 bytes
+ */
+ args->pitch = roundup(min_pitch, 128);
+ args->height = roundup(args->height, 4);
+#endif
+
+ return drm_gem_cma_dumb_create_internal(file, dev, args);
+}
+
DEFINE_DRM_GEM_CMA_FOPS(drv_driver_fops);
static struct drm_driver drv_driver = {
@@ -44,7 +62,7 @@ static struct drm_driver drv_driver = {
.minor = 0,
.patchlevel = 0,
.fops = &drv_driver_fops,
- .dumb_create = drm_gem_cma_dumb_create,
+ .dumb_create = stm_gem_cma_dumb_create,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_free_object_unlocked = drm_gem_cma_free_object,
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index fd02506274da..a514b593f37c 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -14,7 +14,14 @@
#include <drm/bridge/dw_mipi_dsi.h>
#include <video/mipi_display.h>
-/* DSI wrapper register & bit definitions */
+#define HWVER_130 0x31333000 /* IP version 1.30 */
+#define HWVER_131 0x31333100 /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION 0x00
+#define VERSION GENMASK(31, 8)
+
+/* DSI wrapper registers & bit definitions */
/* Note: registers are named as in the Reference Manual */
#define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */
#define WCFGR_DSIM BIT(0) /* DSI Mode */
@@ -65,6 +72,10 @@ enum dsi_color {
struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+ struct dw_mipi_dsi *dsi;
+ u32 hw_version;
+ int lane_min_kbps;
+ int lane_max_kbps;
};
static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -121,7 +132,8 @@ static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor);
}
-static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
+static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi,
+ int clkin_khz, int clkout_khz,
int *idf, int *ndiv, int *odf)
{
int i, o, n, n_min, n_max;
@@ -131,8 +143,8 @@ static int dsi_pll_get_params(int clkin_khz, int clkout_khz,
if (clkin_khz <= 0 || clkout_khz <= 0)
return -EINVAL;
- fvco_min = LANE_MIN_KBPS * 2 * ODF_MAX;
- fvco_max = LANE_MAX_KBPS * 2 * ODF_MIN;
+ fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
+ fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
best_delta = 1000000; /* big started value (1000000khz) */
@@ -212,6 +224,15 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
int ret, bpp;
u32 val;
+ /* Update lane capabilities according to hw version */
+ dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+ dsi->lane_min_kbps = LANE_MIN_KBPS;
+ dsi->lane_max_kbps = LANE_MAX_KBPS;
+ if (dsi->hw_version == HWVER_131) {
+ dsi->lane_min_kbps *= 2;
+ dsi->lane_max_kbps *= 2;
+ }
+
pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
/* Compute requested pll out */
@@ -219,12 +240,12 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
pll_out_khz = mode->clock * bpp / lanes;
/* Add 20% to pll out to be higher than pixel bw (burst mode only) */
pll_out_khz = (pll_out_khz * 12) / 10;
- if (pll_out_khz > LANE_MAX_KBPS) {
- pll_out_khz = LANE_MAX_KBPS;
+ if (pll_out_khz > dsi->lane_max_kbps) {
+ pll_out_khz = dsi->lane_max_kbps;
DRM_WARN("Warning max phy mbps is used\n");
}
- if (pll_out_khz < LANE_MIN_KBPS) {
- pll_out_khz = LANE_MIN_KBPS;
+ if (pll_out_khz < dsi->lane_min_kbps) {
+ pll_out_khz = dsi->lane_min_kbps;
DRM_WARN("Warning min phy mbps is used\n");
}
@@ -232,7 +253,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct drm_display_mode *mode,
idf = 0;
ndiv = 0;
odf = 0;
- ret = dsi_pll_get_params(pll_in_khz, pll_out_khz, &idf, &ndiv, &odf);
+ ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
+ &idf, &ndiv, &odf);
if (ret)
DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
@@ -312,21 +334,24 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
- ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
- if (ret) {
+ platform_set_drvdata(pdev, dsi);
+
+ dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+ if (IS_ERR(dsi->dsi)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+ return PTR_ERR(dsi->dsi);
}
- return ret;
+ return 0;
}
static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
{
- struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
+ struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
clk_disable_unprepare(dsi->pllref_clk);
- dw_mipi_dsi_remove(pdev);
+ dw_mipi_dsi_remove(dsi->dsi);
return 0;
}
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 6dc5d4ec4e17..1a3277e483d5 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -175,6 +175,8 @@
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
+#define CLUT_SIZE 256
+
#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
#define BF1_CA 0x400 /* Constant Alpha */
@@ -326,6 +328,26 @@ static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
}
}
+static inline u32 get_pixelformat_without_alpha(u32 drm)
+{
+ switch (drm) {
+ case DRM_FORMAT_ARGB4444:
+ return DRM_FORMAT_XRGB4444;
+ case DRM_FORMAT_RGBA4444:
+ return DRM_FORMAT_RGBX4444;
+ case DRM_FORMAT_ARGB1555:
+ return DRM_FORMAT_XRGB1555;
+ case DRM_FORMAT_RGBA5551:
+ return DRM_FORMAT_RGBX5551;
+ case DRM_FORMAT_ARGB8888:
+ return DRM_FORMAT_XRGB8888;
+ case DRM_FORMAT_RGBA8888:
+ return DRM_FORMAT_RGBX8888;
+ default:
+ return 0;
+ }
+}
+
static irqreturn_t ltdc_irq_thread(int irq, void *arg)
{
struct drm_device *ddev = arg;
@@ -363,6 +385,28 @@ static irqreturn_t ltdc_irq(int irq, void *arg)
* DRM_CRTC
*/
+static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_color_lut *lut;
+ u32 val;
+ int i;
+
+ if (!crtc || !crtc->state)
+ return;
+
+ if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
+ return;
+
+ lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
+
+ for (i = 0; i < CLUT_SIZE; i++, lut++) {
+ val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
+ (lut->blue >> 8) | (i << 24);
+ reg_write(ldev->regs, LTDC_L1CLUTWR, val);
+ }
+}
+
static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
@@ -404,12 +448,35 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
}
+static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ int rate = mode->clock * 1000;
+
+ /*
+ * TODO clk_round_rate() does not work yet. When ready, it can
+ * be used instead of clk_set_rate() then clk_get_rate().
+ */
+
+ clk_disable(ldev->pixel_clk);
+ if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
+ DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
+ return false;
+ }
+ clk_enable(ldev->pixel_clk);
+
+ adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
+
+ return true;
+}
+
static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
struct videomode vm;
- int rate = mode->clock * 1000;
u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
u32 total_width, total_height;
u32 val;
@@ -432,15 +499,6 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
total_width = accum_act_w + vm.hfront_porch;
total_height = accum_act_h + vm.vfront_porch;
- clk_disable(ldev->pixel_clk);
-
- if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
- DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
- return;
- }
-
- clk_enable(ldev->pixel_clk);
-
/* Configures the HS, VS, DE and PC polarities. Default Active Low */
val = 0;
@@ -486,6 +544,8 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
DRM_DEBUG_ATOMIC("\n");
+ ltdc_crtc_update_clut(crtc);
+
/* Commit shadow registers = update planes at next vblank */
reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
@@ -502,6 +562,7 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
}
static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
+ .mode_fixup = ltdc_crtc_mode_fixup,
.mode_set_nofb = ltdc_crtc_mode_set_nofb,
.atomic_flush = ltdc_crtc_atomic_flush,
.atomic_enable = ltdc_crtc_atomic_enable,
@@ -533,6 +594,7 @@ static const struct drm_crtc_funcs ltdc_crtc_funcs = {
.reset = drm_atomic_helper_crtc_reset,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .gamma_set = drm_atomic_helper_legacy_gamma_set,
};
/*
@@ -638,6 +700,14 @@ static void ltdc_plane_atomic_update(struct drm_plane *plane,
/* Specifies the blending factors */
val = BF1_PAXCA | BF2_1PAXCA;
+ if (!fb->format->has_alpha)
+ val = BF1_CA | BF2_1CA;
+
+ /* Manage hw-specific capabilities */
+ if (ldev->caps.non_alpha_only_l1 &&
+ plane->type != DRM_PLANE_TYPE_PRIMARY)
+ val = BF1_PAXCA | BF2_1PAXCA;
+
reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
LXBFCR_BF2 | LXBFCR_BF1, val);
@@ -705,8 +775,8 @@ static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
struct device *dev = ddev->dev;
struct drm_plane *plane;
unsigned int i, nb_fmt = 0;
- u32 formats[NB_PF];
- u32 drm_fmt;
+ u32 formats[NB_PF * 2];
+ u32 drm_fmt, drm_fmt_no_alpha;
int ret;
/* Get supported pixel formats */
@@ -715,6 +785,18 @@ static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
if (!drm_fmt)
continue;
formats[nb_fmt++] = drm_fmt;
+
+ /* Add the no-alpha related format if any & supported */
+ drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
+ if (!drm_fmt_no_alpha)
+ continue;
+
+ /* Manage hw-specific capabilities */
+ if (ldev->caps.non_alpha_only_l1 &&
+ type != DRM_PLANE_TYPE_PRIMARY)
+ continue;
+
+ formats[nb_fmt++] = drm_fmt_no_alpha;
}
plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
@@ -765,6 +847,9 @@ static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
+ drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
+ drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
+
DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
/* Add planes. Note : the first layer is used by primary plane */
@@ -839,10 +924,19 @@ static int ltdc_get_caps(struct drm_device *ddev)
case HWVER_10300:
ldev->caps.reg_ofs = REG_OFS_NONE;
ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
+ /*
+ * Hw older versions support non-alpha color formats derived
+ * from native alpha color formats only on the primary layer.
+ * For instance, RG16 native format without alpha works fine
+ * on 2nd layer but XR24 (derived color format from AR24)
+ * does not work on 2nd layer.
+ */
+ ldev->caps.non_alpha_only_l1 = true;
break;
case HWVER_20101:
ldev->caps.reg_ofs = REG_OFS_4;
ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
+ ldev->caps.non_alpha_only_l1 = false;
break;
default:
return -ENODEV;
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index edd1c0a446d1..edb268129c54 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -17,6 +17,7 @@ struct ltdc_caps {
u32 reg_ofs; /* register offset for applicable regs */
u32 bus_width; /* bus width (32 or 64 bits) */
const u32 *pix_fmt_hw; /* supported pixel formats */
+ bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
};
struct ltdc_device {
generated by cgit v1.2.1 (git 2.18.0) at 2025-04-11 21:11:53 +0000