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path: root/drivers/clk/sunxi-ng
Commit message (Expand)AuthorAge
* clk: sunxi-ng: Add A80 CCUChen-Yu Tsai2017-01-30
* clk: sunxi-ng: Support separately grouped PLL lock status registerChen-Yu Tsai2017-01-30
* clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENTChen-Yu Tsai2017-01-30
* clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flagChen-Yu Tsai2017-01-30
* clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividersChen-Yu Tsai2017-01-30
* clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPUMaxime Ripard2017-01-27
* clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard2017-01-27
* clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard2017-01-23
* clk: sunxi-ng: Implement global pre-dividerMaxime Ripard2017-01-23
* clk: sunxi-ng: Implement multiplier maximumMaxime Ripard2017-01-23
* clk: sunxi-ng: mult: Fix minimum in round rateMaxime Ripard2017-01-23
* clk: sunxi-ng: Implement factors offsetsMaxime Ripard2017-01-23
* clk: sunxi-ng: multiplier: Add fractional supportMaxime Ripard2017-01-23
* clk: sunxi-ng: add support for V3s CCUIcenowy Zheng2017-01-20
* clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-digMylène Josserand2017-01-17
* clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-01-02
* clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33Icenowy Zheng2017-01-02
* clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng2017-01-02
* clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman2017-01-02
* Merge branch 'clk-fixes' into clk-nextStephen Boyd2016-11-23
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| * clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clockIcenowy Zheng2016-11-23
| * clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai2016-11-21
* | clk: sunxi-ng: Mark structs static and cleanup spacesStephen Boyd2016-11-16
* | Merge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd2016-11-16
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| * clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai2016-11-11
| * clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai2016-11-11
| * clk: sunxi-ng: Add A64 clocksMaxime Ripard2016-11-03
| * clk: sunxi-ng: Implement minimum for multipliersMaxime Ripard2016-10-25
| * clk: sunxi-ng: Add minimums for all the relevant structures and clocksMaxime Ripard2016-10-25
| * clk: sunxi-ng: Finish to convert to structures for argumentsMaxime Ripard2016-10-25
| * clk: sunxi-ng: Remove the use of rational computationsMaxime Ripard2016-10-25
| * clk: sunxi-ng: Rename the internal structuresMaxime Ripard2016-10-20
* | clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parentChen-Yu Tsai2016-10-19
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* clk: sunxi-ng: Fix reset offset for the A23 and A33Maxime Ripard2016-09-20
* clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clkChen-Yu Tsai2016-09-16
* clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLsChen-Yu Tsai2016-09-16
* clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocksChen-Yu Tsai2016-09-16
* Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/...Stephen Boyd2016-09-14
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| * clk: sunxi-ng: Add hardware dependencyJean Delvare2016-09-10
| * clk: sunxi-ng: Add A23 CCUMaxime Ripard2016-09-10
| * clk: sunxi-ng: Add A33 CCU supportMaxime Ripard2016-09-10
| * clk: sunxi-ng: Add N-class clocks supportMaxime Ripard2016-09-10
| * clk: sunxi-ng: mux: Add mux table macroMaxime Ripard2016-09-10
| * clk: sunxi-ng: div: Allow to set a maximumMaxime Ripard2016-09-10
| * clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structureMaxime Ripard2016-09-10
| * clk: sunxi-ng: div: Add mux table macrosMaxime Ripard2016-09-10
| * clk: sunxi-ng: Add A31/A31s clocksChen-Yu Tsai2016-08-25
| * clk: sunxi-ng: mux: Add clk notifier functionsChen-Yu Tsai2016-08-25
| * clk: sunxi-ng: mux: support fixed pre-dividers on multiple parentsChen-Yu Tsai2016-08-25
| * clk: sunxi-ng: mux: Add support for mux tablesChen-Yu Tsai2016-08-25
generated by cgit v1.2.1 (git 2.18.0) at 2025-02-23 04:47:43 +0000